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drm/sun4i: sun8i-hdmi-phy: Separate A83T and H3 PHY ops
Since the driver already needs to support multiple sets of ops, we can drop the mid-layer used by the A83T and H3 PHYs. They share only a small amount of code; factor this out as sun8i_hdmi_phy_set_polarity. For clarity, this commit keeps the existing function order. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220615045543.62813-6-samuel@sholland.org
This commit is contained in:
parent
cdf3e5e15a
commit
ef2731e48b
2 changed files with 46 additions and 48 deletions
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@ -156,11 +156,6 @@ struct sun8i_hdmi_phy_variant {
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const struct dw_hdmi_phy_config *phy_cfg;
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const struct dw_hdmi_phy_ops *phy_ops;
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void (*phy_init)(struct sun8i_hdmi_phy *phy);
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void (*phy_disable)(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy);
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int (*phy_config)(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy,
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unsigned int clk_rate);
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};
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struct sun8i_hdmi_phy {
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@ -123,10 +123,18 @@ static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy,
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unsigned int clk_rate)
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static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy,
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const struct drm_display_mode *mode);
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static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *display,
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const struct drm_display_mode *mode)
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{
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unsigned int clk_rate = mode->crtc_clock * 1000;
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struct sun8i_hdmi_phy *phy = data;
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sun8i_hdmi_phy_set_polarity(phy, mode);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
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@ -185,10 +193,12 @@ static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
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return 0;
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}
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static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy,
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unsigned int clk_rate)
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static int sun8i_h3_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *display,
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const struct drm_display_mode *mode)
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{
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unsigned int clk_rate = mode->crtc_clock * 1000;
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struct sun8i_hdmi_phy *phy = data;
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u32 pll_cfg1_init;
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u32 pll_cfg2_init;
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u32 ana_cfg1_end;
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@ -197,6 +207,11 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
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u32 b_offset = 0;
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u32 val;
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if (phy->variant->has_phy_clk)
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clk_set_rate(phy->clk_phy, clk_rate);
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sun8i_hdmi_phy_set_polarity(phy, mode);
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/* bandwidth / frequency independent settings */
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pll_cfg1_init = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN |
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@ -333,11 +348,9 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
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return 0;
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}
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static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *display,
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const struct drm_display_mode *mode)
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static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy,
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const struct drm_display_mode *mode)
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{
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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u32 val = 0;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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@ -348,16 +361,12 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
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if (phy->variant->has_phy_clk)
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clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
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return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
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};
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static void sun8i_hdmi_phy_disable_a83t(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy)
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static void sun8i_a83t_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
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{
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struct sun8i_hdmi_phy *phy = data;
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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@ -365,9 +374,10 @@ static void sun8i_hdmi_phy_disable_a83t(struct dw_hdmi *hdmi,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
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}
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static void sun8i_hdmi_phy_disable_h3(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy)
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static void sun8i_h3_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
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{
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struct sun8i_hdmi_phy *phy = data;
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
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SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
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@ -375,19 +385,20 @@ static void sun8i_hdmi_phy_disable_h3(struct dw_hdmi *hdmi,
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regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
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}
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static void sun8i_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
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{
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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static const struct dw_hdmi_phy_ops sun8i_a83t_hdmi_phy_ops = {
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.init = sun8i_a83t_hdmi_phy_config,
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.disable = sun8i_a83t_hdmi_phy_disable,
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.read_hpd = dw_hdmi_phy_read_hpd,
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.update_hpd = dw_hdmi_phy_update_hpd,
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.setup_hpd = dw_hdmi_phy_setup_hpd,
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};
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phy->variant->phy_disable(hdmi, phy);
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}
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static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
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.init = &sun8i_hdmi_phy_config,
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.disable = &sun8i_hdmi_phy_disable,
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.read_hpd = &dw_hdmi_phy_read_hpd,
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.update_hpd = &dw_hdmi_phy_update_hpd,
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.setup_hpd = &dw_hdmi_phy_setup_hpd,
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static const struct dw_hdmi_phy_ops sun8i_h3_hdmi_phy_ops = {
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.init = sun8i_h3_hdmi_phy_config,
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.disable = sun8i_h3_hdmi_phy_disable,
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.read_hpd = dw_hdmi_phy_read_hpd,
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.update_hpd = dw_hdmi_phy_update_hpd,
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.setup_hpd = dw_hdmi_phy_setup_hpd,
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};
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static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
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@ -587,35 +598,27 @@ static const struct regmap_config sun8i_hdmi_phy_regmap_config = {
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};
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static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
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.phy_ops = &sun8i_hdmi_phy_ops,
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.phy_ops = &sun8i_a83t_hdmi_phy_ops,
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.phy_init = &sun8i_hdmi_phy_init_a83t,
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.phy_disable = &sun8i_hdmi_phy_disable_a83t,
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.phy_config = &sun8i_hdmi_phy_config_a83t,
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};
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static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
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.has_phy_clk = true,
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.phy_ops = &sun8i_hdmi_phy_ops,
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.phy_ops = &sun8i_h3_hdmi_phy_ops,
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.phy_init = &sun8i_hdmi_phy_init_h3,
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.phy_disable = &sun8i_hdmi_phy_disable_h3,
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.phy_config = &sun8i_hdmi_phy_config_h3,
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};
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static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
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.has_phy_clk = true,
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.has_second_pll = true,
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.phy_ops = &sun8i_hdmi_phy_ops,
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.phy_ops = &sun8i_h3_hdmi_phy_ops,
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.phy_init = &sun8i_hdmi_phy_init_h3,
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.phy_disable = &sun8i_hdmi_phy_disable_h3,
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.phy_config = &sun8i_hdmi_phy_config_h3,
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};
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static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
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.has_phy_clk = true,
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.phy_ops = &sun8i_hdmi_phy_ops,
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.phy_ops = &sun8i_h3_hdmi_phy_ops,
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.phy_init = &sun8i_hdmi_phy_init_h3,
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.phy_disable = &sun8i_hdmi_phy_disable_h3,
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.phy_config = &sun8i_hdmi_phy_config_h3,
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};
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static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = {
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