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x86/MCE/AMD: Clear DFR errors found in THR handler
commitbc1b705b0e
upstream. AMD's MCA Thresholding feature counts errors of all severity levels, not just correctable errors. If a deferred error causes the threshold limit to be reached (it was the error that caused the overflow), then both a deferred error interrupt and a thresholding interrupt will be triggered. The order of the interrupts is not guaranteed. If the threshold interrupt handler is executed first, then it will clear MCA_STATUS for the error. It will not check or clear MCA_DESTAT which also holds a copy of the deferred error. When the deferred error interrupt handler runs it will not find an error in MCA_STATUS, but it will find the error in MCA_DESTAT. This will cause two errors to be logged. Check for deferred errors when handling a threshold interrupt. If a bank contains a deferred error, then clear the bank's MCA_DESTAT register. Define a new helper function to do the deferred error check and clearing of MCA_DESTAT. [ bp: Simplify, convert comment to passive voice. ] Fixes:37d43acfd7
("x86/mce/AMD: Redo error logging from APIC LVT interrupt handlers") Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220621155943.33623-1-yazen.ghannam@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 20 additions and 13 deletions
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@ -788,6 +788,24 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
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return status & MCI_STATUS_DEFERRED;
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}
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static bool _log_error_deferred(unsigned int bank, u32 misc)
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{
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if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),
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mca_msr_reg(bank, MCA_ADDR), misc))
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return false;
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/*
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* Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers.
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* Return true here to avoid accessing these registers.
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*/
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if (!mce_flags.smca)
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return true;
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/* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */
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wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
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return true;
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}
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/*
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* We have three scenarios for checking for Deferred errors:
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*
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@ -799,20 +817,9 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
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*/
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static void log_error_deferred(unsigned int bank)
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{
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bool defrd;
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defrd = _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),
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mca_msr_reg(bank, MCA_ADDR), 0);
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if (!mce_flags.smca)
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if (_log_error_deferred(bank, 0))
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return;
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/* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
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if (defrd) {
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wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
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return;
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}
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/*
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* Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
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* for a valid error.
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@ -832,7 +839,7 @@ static void amd_deferred_error_interrupt(void)
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static void log_error_thresholding(unsigned int bank, u64 misc)
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{
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_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), mca_msr_reg(bank, MCA_ADDR), misc);
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_log_error_deferred(bank, misc);
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}
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static void log_and_reset_block(struct threshold_block *block)
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