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crypto: caam - Add definition of rd/wr_reg64 for little endian platform
CAAM IP has certain 64 bit registers . 32 bit architectures cannot force atomic-64 operations. This patch adds definition of these atomic-64 operations for little endian platforms. The definitions which existed previously were for big endian platforms. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -84,6 +84,7 @@
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#endif
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#ifndef CONFIG_64BIT
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#ifdef __BIG_ENDIAN
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static inline void wr_reg64(u64 __iomem *reg, u64 data)
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{
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wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
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@ -95,6 +96,21 @@ static inline u64 rd_reg64(u64 __iomem *reg)
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return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
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((u64)rd_reg32((u32 __iomem *)reg + 1));
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}
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#else
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#ifdef __LITTLE_ENDIAN
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static inline void wr_reg64(u64 __iomem *reg, u64 data)
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{
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wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32);
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wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull);
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}
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static inline u64 rd_reg64(u64 __iomem *reg)
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{
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return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) |
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((u64)rd_reg32((u32 __iomem *)reg));
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}
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#endif
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#endif
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#endif
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/*
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