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phy: qcom-qmp: Add support for QMP V3 USB3 PHY
QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY with dual RX/TX lanes to support type-c. There is a separate block DP_COM for configuration related to type-c or DP. Add support for dp_com region and secondary rx/tx lanes initialization. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Manu Gautam
Kishon Vijay Abraham I
parent
8587b220f0
commit
efb05a50c9
1 changed files with 220 additions and 3 deletions
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@ -47,6 +47,21 @@
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/* QPHY_COM_PCS_READY_STATUS bit */
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#define PCS_READY BIT(0)
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/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
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/* DP PHY soft reset */
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#define SW_DPPHY_RESET BIT(0)
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/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
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#define SW_DPPHY_RESET_MUX BIT(1)
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/* USB3 PHY soft reset */
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#define SW_USB3PHY_RESET BIT(2)
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/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
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#define SW_USB3PHY_RESET_MUX BIT(3)
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/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
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#define USB3_MODE BIT(0) /* enables USB3 mode */
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#define DP_MODE BIT(1) /* enables DP mode */
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#define PHY_INIT_COMPLETE_TIMEOUT 1000
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#define POWER_DOWN_DELAY_US_MIN 10
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#define POWER_DOWN_DELAY_US_MAX 11
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@ -122,6 +137,12 @@ static const unsigned int usb3phy_regs_layout[] = {
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[QPHY_PCS_READY_STATUS] = 0x17c,
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};
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static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
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[QPHY_SW_RESET] = 0x00,
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[QPHY_START_CTRL] = 0x08,
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[QPHY_PCS_READY_STATUS] = 0x174,
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};
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static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
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@ -350,6 +371,112 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
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QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
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/* FLL settings */
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
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/* Lock Det settings */
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
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};
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/* struct qmp_phy_cfg - per-PHY initialization config */
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struct qmp_phy_cfg {
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/* phy-type - PCIE/UFS/USB */
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@ -394,6 +521,12 @@ struct qmp_phy_cfg {
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/* power_down delay in usec */
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int pwrdn_delay_min;
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int pwrdn_delay_max;
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/* true, if PHY has a separate DP_COM control block */
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bool has_phy_dp_com_ctrl;
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/* Register offset of secondary tx/rx lanes for USB DP combo PHY */
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unsigned int tx_b_lane_offset;
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unsigned int rx_b_lane_offset;
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};
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/**
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@ -424,6 +557,7 @@ struct qmp_phy {
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*
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* @dev: device
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* @serdes: iomapped memory space for phy's serdes
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* @dp_com: iomapped memory space for phy's dp_com control block
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*
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* @clks: array of clocks required by phy
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* @resets: array of resets required by phy
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@ -437,6 +571,7 @@ struct qmp_phy {
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struct qcom_qmp {
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struct device *dev;
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void __iomem *serdes;
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void __iomem *dp_com;
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struct clk_bulk_data *clks;
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struct reset_control **resets;
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@ -478,6 +613,10 @@ static const char * const msm8996_phy_clk_l[] = {
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"aux", "cfg_ahb", "ref",
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};
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static const char * const qmp_v3_phy_clk_l[] = {
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"aux", "cfg_ahb", "ref", "com_aux",
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};
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/* list of resets */
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static const char * const msm8996_pciephy_reset_l[] = {
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"phy", "common", "cfg",
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@ -584,6 +723,38 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
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.pwrdn_delay_max = 1005, /* us */
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};
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static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
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.type = PHY_TYPE_USB3,
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.nlanes = 1,
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.serdes_tbl = qmp_v3_usb3_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
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.tx_tbl = qmp_v3_usb3_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
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.rx_tbl = qmp_v3_usb3_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
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.pcs_tbl = qmp_v3_usb3_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
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.clk_list = qmp_v3_phy_clk_l,
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.num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
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.reset_list = msm8996_usb3phy_reset_l,
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.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
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.vreg_list = msm8996_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
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.regs = qmp_v3_usb3phy_regs_layout,
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN,
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.mask_pcs_ready = PHYSTATUS,
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.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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.has_phy_dp_com_ctrl = true,
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.tx_b_lane_offset = 0x400,
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.rx_b_lane_offset = 0x400,
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};
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static void qcom_qmp_phy_configure(void __iomem *base,
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const unsigned int *regs,
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const struct qmp_phy_init_tbl tbl[],
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@ -620,6 +791,7 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
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{
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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void __iomem *serdes = qmp->serdes;
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void __iomem *dp_com = qmp->dp_com;
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int ret, i;
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mutex_lock(&qmp->phy_mutex);
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@ -663,6 +835,23 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp)
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qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
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SW_PWRDN);
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if (cfg->has_phy_dp_com_ctrl) {
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qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
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SW_PWRDN);
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/* override hardware control for reset of qmp phy */
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qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
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SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
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SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
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qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
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USB3_MODE | DP_MODE);
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/* bring both QMP USB and QMP DP PHYs PCS block out of reset */
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qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
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SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
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SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
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}
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/* Serdes configuration */
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qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
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cfg->serdes_tbl_num);
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@ -746,6 +935,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
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void __iomem *tx = qphy->tx;
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void __iomem *rx = qphy->rx;
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void __iomem *pcs = qphy->pcs;
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void __iomem *dp_com = qmp->dp_com;
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void __iomem *status;
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unsigned int mask, val;
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int ret;
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@ -767,7 +957,16 @@ static int qcom_qmp_phy_init(struct phy *phy)
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/* Tx, Rx, and PCS configurations */
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qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
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/* Configuration for other LANE for USB-DP combo PHY */
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if (cfg->has_phy_dp_com_ctrl)
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qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs,
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cfg->tx_tbl, cfg->tx_tbl_num);
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qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
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if (cfg->has_phy_dp_com_ctrl)
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qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs,
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cfg->rx_tbl, cfg->rx_tbl_num);
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qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
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/*
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@ -781,6 +980,8 @@ static int qcom_qmp_phy_init(struct phy *phy)
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/* Pull PHY out of reset state */
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qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
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if (cfg->has_phy_dp_com_ctrl)
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||||
qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
|
||||
|
||||
/* start SerDes and Phy-Coding-Sublayer */
|
||||
qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
|
||||
|
|
@ -1031,6 +1232,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
|
|||
}, {
|
||||
.compatible = "qcom,ipq8074-qmp-pcie-phy",
|
||||
.data = &ipq8074_pciephy_cfg,
|
||||
}, {
|
||||
.compatible = "qcom,qmp-v3-usb3-phy",
|
||||
.data = &qmp_v3_usb3phy_cfg,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
|
@ -1054,6 +1258,11 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
|
|||
qmp->dev = dev;
|
||||
dev_set_drvdata(dev, qmp);
|
||||
|
||||
/* Get the specific init parameters of QMP phy */
|
||||
qmp->cfg = of_device_get_match_data(dev);
|
||||
if (!qmp->cfg)
|
||||
return -EINVAL;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
|
|
@ -1062,10 +1271,18 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
|
|||
/* per PHY serdes; usually located at base address */
|
||||
qmp->serdes = base;
|
||||
|
||||
mutex_init(&qmp->phy_mutex);
|
||||
/* per PHY dp_com; if PHY has dp_com control block */
|
||||
if (qmp->cfg->has_phy_dp_com_ctrl) {
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"dp_com");
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
/* Get the specific init parameters of QMP phy */
|
||||
qmp->cfg = of_device_get_match_data(dev);
|
||||
qmp->dp_com = base;
|
||||
}
|
||||
|
||||
mutex_init(&qmp->phy_mutex);
|
||||
|
||||
ret = qcom_qmp_phy_clk_init(dev);
|
||||
if (ret)
|
||||
|
|
|
|||
Loading…
Reference in a new issue