mirror of
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arm64: dts: Amlogic updates for v5.4 (round 2)
- new board: Khadas VIM3L (SM1/S905D3 SoC) - support power domains on G12[AB] and SM1 SoCs - DT binding fixups based on YAML schema - add a bunch of remote control keymap - enable DVFS on SM1/SEI610 board -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl1oX4gACgkQWTcYmtP7 xmVgmA//bj9MUuKJYgXJ6ZSdtSFK7tL3MwqMmwJpt8PPRt+KTUEr3x6Ix+ZvkpYB YsiUYvA0URIL5gcibsIP6UsO6c0QAwnW6NaWGl96cHPwGAB6cBdWY5msxHEC6KaN GzBOjlsTTv1gFptz9vLd8RvEXeH/M92pdIwWQrIE1c9LXKfLoLhC5dHlw9iHG7kN ja7Qsv9J3GkuTPYoPh04X2q44NPGwUtxhMNqGbn9S9T5YCqXkKa4RWgyvs/Iam72 hs/humUMdlciH4pSFikKQd0Xouf2cYnEIsVqWFuHFgDs5KuYrSlOAutVgkcFOcnb bG61iKV5urue0sxnar8Fx0OR6aeT04A9zGHWEPH6Tq2kfl5VQNZUKZb5XUZJWgWe vj0kTG6L7wk5oem19TtHOTZTpwRTdk3Bkth+dt9RZtmVC/HL1C79Fkt1BKpCYesQ 7tsUmNnTprz0unUQIbY6UMfzpD8JixGM/ak5ODJ+pQivFlbgu/eQTDNRAOsEjszn w7AZtyp2AANJN/u5Vxf8IqonOzF1UhMyrIa39D6vAQn0xfCMlFh0RcV5Afs4qows GRJ17JMVL7da/cbyoG17gCyQSYYTWPkPIbqOEyUOTqOzEGVgHweNsBOWBkEwolNv v0+rIJHjw11527ibqdBxMIKIrSIfhN63j343zN0RrwMdZbHroJg= =7yjy -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2.1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.4 (round 2) - new board: Khadas VIM3L (SM1/S905D3 SoC) - support power domains on G12[AB] and SM1 SoCs - DT binding fixups based on YAML schema - add a bunch of remote control keymap - enable DVFS on SM1/SEI610 board * tag 'amlogic-dt64-2.1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (44 commits) arm64: dts: meson-sm1-sei610: add stdout-path property back arm64: dts: meson-sm1-sei610: enable DVFS arm64: dts: khadas-vim3: add support for the SM1 based VIM3L dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi arm64: dts: meson: g12a: add reset to tdm formatters arm64: dts: meson: g12a: audio clock controller provides resets arm64: dts: meson-sm1-sei610: enable DVFS arm64: dts: meson-gxm-khadas-vim2: use rc-khadas keymap arm64: dts: meson-gxl-s905w-tx3-mini: add rc-tx3mini keymap arm64: dts: meson-gxl-s905x-khadas-vim: use rc-khadas keymap arm64: dts: meson-gxbb-wetek-play2: add rc-wetek-play2 keymap arm64: dts: meson-gxbb-wetek-hub: add rc-wetek-hub keymap arm64: dts: meson-g12a-x96-max: add rc-x96max keymap arm64: dts: meson-g12b-odroid-n2: add rc-odroid keymap arm64: dts: meson-sm1-sei610: add USB support arm64: dts: meson-sm1-sei610: add HDMI display support arm64: dts: meson-g12: add Everything-Else power domain controller arm64: dts: meson: fix boards regulators states format arm64: dts: meson-gxbb-p201: fix snps, reset-delays-us format ... Link: https://patchwork.kernel.org/patch/11122331/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
f02bd65a5b
42 changed files with 1553 additions and 443 deletions
|
@ -150,9 +150,10 @@ properties:
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|||
- const: amlogic,s922x
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- const: amlogic,g12b
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- description: Boards with the Amlogic Meson SM1 S905X3 SoC
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- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
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items:
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- enum:
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- seirobotics,sei610
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- khadas,vim3l
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- const: amlogic,sm1
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...
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|
|
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@ -22,6 +22,7 @@ Required Properties:
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|||
components.
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- resets : phandle of the internal reset line
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- #clock-cells : should be 1.
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- #reset-cells : should be 1 on the g12a (and following) soc family
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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|
|
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@ -11,6 +11,7 @@ Required Properties:
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"amlogic,axg-clkc" for AXG SoC.
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"amlogic,g12a-clkc" for G12A SoC.
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"amlogic,g12b-clkc" for G12B SoC.
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"amlogic,sm1-clkc" for SM1 SoC.
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- clocks : list of clock phandle, one for each entry clock-names.
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- clock-names : should contain the following:
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* "xtal": the platform xtal
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@ -0,0 +1,93 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/power/amlogic,meson-ee-pwrc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson Everything-Else Power Domains
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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description: |+
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The Everything-Else Power Domains node should be the child of a syscon
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node with the required property:
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- compatible: Should be the following:
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"amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"
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Refer to the the bindings described in
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Documentation/devicetree/bindings/mfd/syscon.txt
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properties:
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compatible:
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enum:
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- amlogic,meson-g12a-pwrc
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- amlogic,meson-sm1-pwrc
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clocks:
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minItems: 2
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clock-names:
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items:
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- const: vpu
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- const: vapb
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resets:
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minItems: 11
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reset-names:
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items:
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- const: viu
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- const: venc
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- const: vcbus
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- const: bt656
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- const: rdma
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- const: venci
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- const: vencp
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- const: vdac
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- const: vdi6
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- const: vencl
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- const: vid_lock
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"#power-domain-cells":
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const: 1
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amlogic,ao-sysctrl:
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description: phandle to the AO sysctrl node
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allOf:
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- $ref: /schemas/types.yaml#/definitions/phandle
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required:
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- compatible
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- clocks
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- clock-names
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- resets
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- reset-names
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- "#power-domain-cells"
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- amlogic,ao-sysctrl
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examples:
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- |
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pwrc: power-controller {
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compatible = "amlogic,meson-sm1-pwrc";
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#power-domain-cells = <1>;
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amlogic,ao-sysctrl = <&rti>;
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resets = <&reset_viu>,
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<&reset_venc>,
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<&reset_vcbus>,
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<&reset_bt656>,
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<&reset_rdma>,
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<&reset_venci>,
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<&reset_vencp>,
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<&reset_vdac>,
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<&reset_vdi6>,
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<&reset_vencl>,
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<&reset_vid_lock>;
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reset-names = "viu", "venc", "vcbus", "bt656",
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"rdma", "venci", "vencp", "vdac",
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"vdi6", "vencl", "vid_lock";
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clocks = <&clk_vpu>, <&clk_vapb>;
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clock-names = "vpu", "vapb";
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};
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@ -11,6 +11,7 @@ Required properties:
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|||
"amlogic,meson8b-clk-measure" for Meson8b SoCs
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"amlogic,meson-axg-clk-measure" for AXG SoCs
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"amlogic,meson-g12a-clk-measure" for G12a SoCs
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"amlogic,meson-sm1-clk-measure" for SM1 SoCs
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- reg: base address and size of the Clock Measurer register space.
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Example:
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|
|
|
@ -35,3 +35,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
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dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
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|
|
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@ -174,8 +174,8 @@ ethmac: ethernet@ff3f0000 {
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compatible = "amlogic,meson-axg-dwmac",
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"snps,dwmac-3.70a",
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"snps,dwmac";
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reg = <0x0 0xff3f0000 0x0 0x10000
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0x0 0xff634540 0x0 0x8>;
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reg = <0x0 0xff3f0000 0x0 0x10000>,
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<0x0 0xff634540 0x0 0x8>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_ETH>,
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@ -1118,7 +1118,7 @@ clkc: clock-controller {
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|||
};
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mailbox: mailbox@ff63c404 {
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compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
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compatible = "amlogic,meson-gxbb-mhu";
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reg = <0 0xff63c404 0 0x4c>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
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|
|
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@ -11,6 +11,7 @@
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|||
#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
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#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
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#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
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/ {
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@ -98,8 +99,8 @@ ethmac: ethernet@ff3f0000 {
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compatible = "amlogic,meson-axg-dwmac",
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"snps,dwmac-3.70a",
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"snps,dwmac";
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reg = <0x0 0xff3f0000 0x0 0x10000
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0x0 0xff634540 0x0 0x8>;
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reg = <0x0 0xff3f0000 0x0 0x10000>,
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<0x0 0xff634540 0x0 0x8>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_ETH>,
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@ -1406,6 +1407,53 @@ clkc: clock-controller {
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clocks = <&xtal>;
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clock-names = "xtal";
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};
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pwrc: power-controller {
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compatible = "amlogic,meson-g12a-pwrc";
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#power-domain-cells = <1>;
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amlogic,ao-sysctrl = <&rti>;
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resets = <&reset RESET_VIU>,
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<&reset RESET_VENC>,
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<&reset RESET_VCBUS>,
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<&reset RESET_BT656>,
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<&reset RESET_RDMA>,
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<&reset RESET_VENCI>,
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<&reset RESET_VENCP>,
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<&reset RESET_VDAC>,
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<&reset RESET_VDI6>,
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<&reset RESET_VENCL>,
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<&reset RESET_VID_LOCK>;
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reset-names = "viu", "venc", "vcbus", "bt656",
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"rdma", "venci", "vencp", "vdac",
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"vdi6", "vencl", "vid_lock";
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clocks = <&clkc CLKID_VPU>,
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<&clkc CLKID_VAPB>;
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clock-names = "vpu", "vapb";
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/*
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* VPU clocking is provided by two identical clock paths
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* VPU_0 and VPU_1 muxed to a single clock by a glitch
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* free mux to safely change frequency while running.
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* Same for VAPB but with a final gate after the glitch free mux.
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*/
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assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_VPU>, /* Glitch free mux */
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<&clkc CLKID_VAPB_0_SEL>,
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<&clkc CLKID_VAPB_0>,
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<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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<0>, /* Do Nothing */
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_FCLK_DIV4>,
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<0>, /* Do Nothing */
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<&clkc CLKID_VAPB_0>;
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assigned-clock-rates = <0>, /* Do Nothing */
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<666666666>,
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<0>, /* Do Nothing */
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<0>, /* Do Nothing */
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<250000000>,
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||||
<0>; /* Do Nothing */
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};
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||||
};
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||||
};
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@ -1434,6 +1482,7 @@ clkc_audio: clock-controller@0 {
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|||
compatible = "amlogic,g12a-audio-clkc";
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||||
reg = <0x0 0x0 0x0 0xb4>;
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||||
#clock-cells = <1>;
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||||
#reset-cells = <1>;
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||||
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||||
clocks = <&clkc CLKID_AUDIO>,
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||||
<&clkc CLKID_MPLL0>,
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||||
|
@ -1542,6 +1591,7 @@ tdmin_a: audio-controller@300 {
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|||
"amlogic,axg-tdmin";
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||||
reg = <0x0 0x300 0x0 0x40>;
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||||
sound-name-prefix = "TDMIN_A";
|
||||
resets = <&clkc_audio AUD_RESET_TDMIN_A>;
|
||||
clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
|
||||
<&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
|
||||
<&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
|
||||
|
@ -1557,6 +1607,7 @@ tdmin_b: audio-controller@340 {
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|||
"amlogic,axg-tdmin";
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||||
reg = <0x0 0x340 0x0 0x40>;
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||||
sound-name-prefix = "TDMIN_B";
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resets = <&clkc_audio AUD_RESET_TDMIN_B>;
|
||||
clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
|
||||
<&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
|
||||
<&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
|
||||
|
@ -1572,6 +1623,7 @@ tdmin_c: audio-controller@380 {
|
|||
"amlogic,axg-tdmin";
|
||||
reg = <0x0 0x380 0x0 0x40>;
|
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sound-name-prefix = "TDMIN_C";
|
||||
resets = <&clkc_audio AUD_RESET_TDMIN_C>;
|
||||
clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
|
||||
<&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
|
||||
<&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
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||||
|
@ -1587,6 +1639,7 @@ tdmin_lb: audio-controller@3c0 {
|
|||
"amlogic,axg-tdmin";
|
||||
reg = <0x0 0x3c0 0x0 0x40>;
|
||||
sound-name-prefix = "TDMIN_LB";
|
||||
resets = <&clkc_audio AUD_RESET_TDMIN_LB>;
|
||||
clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
|
||||
<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
|
||||
<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
|
||||
|
@ -1626,6 +1679,7 @@ tdmout_a: audio-controller@500 {
|
|||
compatible = "amlogic,g12a-tdmout";
|
||||
reg = <0x0 0x500 0x0 0x40>;
|
||||
sound-name-prefix = "TDMOUT_A";
|
||||
resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
|
||||
clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
|
||||
<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
|
||||
<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
|
||||
|
@ -1640,6 +1694,7 @@ tdmout_b: audio-controller@540 {
|
|||
compatible = "amlogic,g12a-tdmout";
|
||||
reg = <0x0 0x540 0x0 0x40>;
|
||||
sound-name-prefix = "TDMOUT_B";
|
||||
resets = <&clkc_audio AUD_RESET_TDMOUT_B>;
|
||||
clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
|
||||
<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
|
||||
<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
|
||||
|
@ -1654,6 +1709,7 @@ tdmout_c: audio-controller@580 {
|
|||
compatible = "amlogic,g12a-tdmout";
|
||||
reg = <0x0 0x580 0x0 0x40>;
|
||||
sound-name-prefix = "TDMOUT_C";
|
||||
resets = <&clkc_audio AUD_RESET_TDMOUT_C>;
|
||||
clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
|
||||
<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
|
||||
<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
|
||||
|
@ -1753,50 +1809,6 @@ clkc_AO: clock-controller {
|
|||
clock-names = "xtal", "mpeg-clk";
|
||||
};
|
||||
|
||||
pwrc_vpu: power-controller-vpu {
|
||||
compatible = "amlogic,meson-g12a-pwrc-vpu";
|
||||
#power-domain-cells = <0>;
|
||||
amlogic,hhi-sysctrl = <&hhi>;
|
||||
resets = <&reset RESET_VIU>,
|
||||
<&reset RESET_VENC>,
|
||||
<&reset RESET_VCBUS>,
|
||||
<&reset RESET_BT656>,
|
||||
<&reset RESET_RDMA>,
|
||||
<&reset RESET_VENCI>,
|
||||
<&reset RESET_VENCP>,
|
||||
<&reset RESET_VDAC>,
|
||||
<&reset RESET_VDI6>,
|
||||
<&reset RESET_VENCL>,
|
||||
<&reset RESET_VID_LOCK>;
|
||||
clocks = <&clkc CLKID_VPU>,
|
||||
<&clkc CLKID_VAPB>;
|
||||
clock-names = "vpu", "vapb";
|
||||
/*
|
||||
* VPU clocking is provided by two identical clock paths
|
||||
* VPU_0 and VPU_1 muxed to a single clock by a glitch
|
||||
* free mux to safely change frequency while running.
|
||||
* Same for VAPB but with a final gate after the glitch free mux.
|
||||
*/
|
||||
assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
|
||||
<&clkc CLKID_VPU_0>,
|
||||
<&clkc CLKID_VPU>, /* Glitch free mux */
|
||||
<&clkc CLKID_VAPB_0_SEL>,
|
||||
<&clkc CLKID_VAPB_0>,
|
||||
<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
|
||||
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_VPU_0>,
|
||||
<&clkc CLKID_FCLK_DIV4>,
|
||||
<0>, /* Do Nothing */
|
||||
<&clkc CLKID_VAPB_0>;
|
||||
assigned-clock-rates = <0>, /* Do Nothing */
|
||||
<666666666>,
|
||||
<0>, /* Do Nothing */
|
||||
<0>, /* Do Nothing */
|
||||
<250000000>,
|
||||
<0>; /* Do Nothing */
|
||||
};
|
||||
|
||||
ao_pinctrl: pinctrl@14 {
|
||||
compatible = "amlogic,meson-g12a-aobus-pinctrl";
|
||||
#address-cells = <2>;
|
||||
|
@ -2045,6 +2057,11 @@ mux {
|
|||
};
|
||||
};
|
||||
|
||||
vrtc: rtc@0a8 {
|
||||
compatible = "amlogic,meson-vrtc";
|
||||
reg = <0x0 0x000a8 0x0 0x4>;
|
||||
};
|
||||
|
||||
cec_AO: cec@100 {
|
||||
compatible = "amlogic,meson-gx-ao-cec";
|
||||
reg = <0x0 0x00100 0x0 0x14>;
|
||||
|
@ -2144,7 +2161,6 @@ vpu: vpu@ff900000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
amlogic,canvas = <&canvas>;
|
||||
power-domains = <&pwrc_vpu>;
|
||||
|
||||
/* CVBS VDAC output port */
|
||||
cvbs_vdac_port: port@0 {
|
||||
|
@ -2182,8 +2198,7 @@ cbus: bus@ffd00000 {
|
|||
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
|
||||
|
||||
reset: reset-controller@1004 {
|
||||
compatible = "amlogic,meson-g12a-reset",
|
||||
"amlogic,meson-axg-reset";
|
||||
compatible = "amlogic,meson-axg-reset";
|
||||
reg = <0x0 0x1004 0x0 0x9c>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
|
||||
|
||||
/ {
|
||||
compatible = "amediatech,x96-max", "amlogic,u200", "amlogic,g12a";
|
||||
compatible = "amediatech,x96-max", "amlogic,g12a";
|
||||
model = "Shenzhen Amediatech Technology Co., Ltd X96 Max";
|
||||
|
||||
aliases {
|
||||
|
@ -321,6 +321,7 @@ &ir {
|
|||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
linux,rc-map-name = "rc-x96max";
|
||||
};
|
||||
|
||||
&pwm_AO_cd {
|
||||
|
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include "meson-g12-common.dtsi"
|
||||
#include <dt-bindings/power/meson-g12a-power.h>
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,g12a";
|
||||
|
@ -110,6 +111,14 @@ opp-1800000000 {
|
|||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
power-domains = <&pwrc PWRC_G12A_ETH_ID>;
|
||||
};
|
||||
|
||||
&vpu {
|
||||
power-domains = <&pwrc PWRC_G12A_VPU_ID>;
|
||||
};
|
||||
|
||||
&sd_emmc_a {
|
||||
amlogic,dram-access-quirk;
|
||||
};
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "meson-g12b-a311d.dtsi"
|
||||
#include "meson-khadas-vim3.dtsi"
|
||||
#include "meson-g12b-khadas-vim3.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
|
@ -5,116 +5,9 @@
|
|||
* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/meson-g12a-gpio.h>
|
||||
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
|
||||
|
||||
/ {
|
||||
model = "Khadas VIM3";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
ethernet0 = ðmac;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 2>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1710000>;
|
||||
|
||||
button-function {
|
||||
label = "Function";
|
||||
linux,code = <KEY_FN>;
|
||||
press-threshold-microvolt = <10000>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
white {
|
||||
label = "vim3:white:sys";
|
||||
gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
red {
|
||||
label = "vim3:red";
|
||||
gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
gpio-keys-polled {
|
||||
compatible = "gpio-keys-polled";
|
||||
poll-interval = <100>;
|
||||
|
||||
power-button {
|
||||
label = "power";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&wifi32k>;
|
||||
clock-names = "ext_clock";
|
||||
};
|
||||
|
||||
dc_in: regulator-dc_in {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "DC_IN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_5v: regulator-vcc_5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_in>;
|
||||
|
||||
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-vcc_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_3v3: regulator-vcc_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
/* FIXME: actually controlled by VDDCPU_B_EN */
|
||||
};
|
||||
|
||||
vddcpu_a: regulator-vddcpu-a {
|
||||
/*
|
||||
* MP8756GD Regulator.
|
||||
|
@ -153,62 +46,6 @@ vddcpu_b: regulator-vddcpu-b {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddao_1v8: regulator-vddao_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_AO1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
emmc_1v8: regulator-emmc_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "EMMC_AO1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vsys_3v3: regulator-vsys_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSYS_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_in>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
usb_pwr: regulator-usb_pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB_PWR";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_5v>;
|
||||
|
||||
gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wifi32k: wifi32k {
|
||||
compatible = "pwm-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "amlogic,axg-sound-card";
|
||||
model = "G12A-KHADAS-VIM3";
|
||||
|
@ -269,20 +106,6 @@ &arb {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
pinctrl-0 = <&cec_ao_a_h_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cecb_AO {
|
||||
pinctrl-0 = <&cec_ao_b_h_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&clkc_audio {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -329,31 +152,6 @@ &cpu103 {
|
|||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&ext_mdio {
|
||||
external_phy: ethernet-phy@0 {
|
||||
/* Realtek RTL8211F (0x001cc916) */
|
||||
reg = <0>;
|
||||
max-speed = <1000>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
/* MAC_INTR on GPIOZ_14 */
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&external_phy>;
|
||||
amlogic,tx-delay-ns = <2>;
|
||||
};
|
||||
|
||||
&frddr_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&frddr_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -362,46 +160,6 @@ &frddr_c {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-supply = <&vcc_5v>;
|
||||
};
|
||||
|
||||
&hdmi_tx_tmds_port {
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
gpio_expander: gpio-controller@20 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x20>;
|
||||
vcc-supply = <&vcc_3v3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
linux,rc-map-name = "rc-khadas";
|
||||
};
|
||||
|
||||
&pwm_ab {
|
||||
pinctrl-0 = <&pwm_a_e_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -418,81 +176,6 @@ &pwm_AO_cd {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm_ef {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_e_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vddao_1v8>;
|
||||
};
|
||||
|
||||
/* SDIO */
|
||||
&sd_emmc_a {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
pinctrl-1 = <&sdio_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr50;
|
||||
max-frequency = <100000000>;
|
||||
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
|
||||
vmmc-supply = <&vsys_3v3>;
|
||||
vqmmc-supply = <&vddao_1v8>;
|
||||
|
||||
brcmf: wifi@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
};
|
||||
};
|
||||
|
||||
/* SD card */
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcard_c_pins>;
|
||||
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <50000000>;
|
||||
disable-wp;
|
||||
|
||||
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <&vsys_3v3>;
|
||||
vqmmc-supply = <&vsys_3v3>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
max-frequency = <200000000>;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&emmc_1v8>;
|
||||
};
|
||||
|
||||
&tdmif_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -504,41 +187,3 @@ &tdmout_b {
|
|||
&tohdmitx {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
|
||||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
|
||||
max-speed = <2000000>;
|
||||
clocks = <&wifi32k>;
|
||||
clock-names = "lpo";
|
||||
};
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
phy-supply = <&dc_in>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
phy-supply = <&usb_pwr>;
|
||||
};
|
||||
|
||||
&usb3_pcie_phy {
|
||||
phy-supply = <&usb_pwr>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
|
|
@ -66,8 +66,8 @@ tf_io: gpio-regulator-tf_io {
|
|||
gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0>;
|
||||
|
||||
states = <3300000 0
|
||||
1800000 1>;
|
||||
states = <3300000 0>,
|
||||
<1800000 1>;
|
||||
};
|
||||
|
||||
flash_1v8: regulator-flash_1v8 {
|
||||
|
@ -395,6 +395,7 @@ &ir {
|
|||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
linux,rc-map-name = "rc-odroid";
|
||||
};
|
||||
|
||||
&pwm_ab {
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "meson-g12b-s922x.dtsi"
|
||||
#include "meson-khadas-vim3.dtsi"
|
||||
#include "meson-g12b-khadas-vim3.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
|
@ -5,6 +5,7 @@
|
|||
*/
|
||||
|
||||
#include "meson-g12-common.dtsi"
|
||||
#include <dt-bindings/power/meson-g12a-power.h>
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,g12b";
|
||||
|
@ -101,6 +102,14 @@ &clkc {
|
|||
compatible = "amlogic,g12b-clkc";
|
||||
};
|
||||
|
||||
ðmac {
|
||||
power-domains = <&pwrc PWRC_G12A_ETH_ID>;
|
||||
};
|
||||
|
||||
&vpu {
|
||||
power-domains = <&pwrc PWRC_G12A_VPU_ID>;
|
||||
};
|
||||
|
||||
&sd_emmc_a {
|
||||
amlogic,dram-access-quirk;
|
||||
};
|
||||
|
|
|
@ -220,7 +220,7 @@ gpio_intc: interrupt-controller@9880 {
|
|||
};
|
||||
|
||||
reset: reset-controller@4404 {
|
||||
compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
|
||||
compatible = "amlogic,meson-gxbb-reset";
|
||||
reg = <0x0 0x04404 0x0 0x9c>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
@ -317,7 +317,7 @@ spicc: spi@8d80 {
|
|||
};
|
||||
|
||||
spifc: spi@8c80 {
|
||||
compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
|
||||
compatible = "amlogic,meson-gxbb-spifc";
|
||||
reg = <0x0 0x08c80 0x0 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -325,7 +325,7 @@ spifc: spi@8c80 {
|
|||
};
|
||||
|
||||
watchdog@98d0 {
|
||||
compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
|
||||
compatible = "amlogic,meson-gxbb-wdt";
|
||||
reg = <0x0 0x098d0 0x0 0x10>;
|
||||
clocks = <&xtal>;
|
||||
};
|
||||
|
@ -451,7 +451,7 @@ vdec: video-codec@c8820000 {
|
|||
amlogic,canvas = <&canvas>;
|
||||
};
|
||||
|
||||
periphs: periphs@c8834000 {
|
||||
periphs: bus@c8834000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc8834000 0x0 0x2000>;
|
||||
#address-cells = <2>;
|
||||
|
@ -490,7 +490,7 @@ sysctrl: system-controller@0 {
|
|||
};
|
||||
|
||||
mailbox: mailbox@404 {
|
||||
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
|
||||
compatible = "amlogic,meson-gxbb-mhu";
|
||||
reg = <0 0x404 0 0x4c>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
|
||||
|
@ -503,8 +503,8 @@ ethmac: ethernet@c9410000 {
|
|||
compatible = "amlogic,meson-gxbb-dwmac",
|
||||
"snps,dwmac-3.70a",
|
||||
"snps,dwmac";
|
||||
reg = <0x0 0xc9410000 0x0 0x10000
|
||||
0x0 0xc8834540 0x0 0x4>;
|
||||
reg = <0x0 0xc9410000 0x0 0x10000>,
|
||||
<0x0 0xc8834540 0x0 0x4>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
rx-fifo-depth = <4096>;
|
||||
|
@ -544,9 +544,8 @@ sd_emmc_c: mmc@74000 {
|
|||
vpu: vpu@d0100000 {
|
||||
compatible = "amlogic,meson-gx-vpu";
|
||||
reg = <0x0 0xd0100000 0x0 0x100000>,
|
||||
<0x0 0xc883c000 0x0 0x1000>,
|
||||
<0x0 0xc8838000 0x0 0x1000>;
|
||||
reg-names = "vpu", "hhi", "dmc";
|
||||
<0x0 0xc883c000 0x0 0x1000>;
|
||||
reg-names = "vpu", "hhi";
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
|
||||
/ {
|
||||
compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
|
||||
model = "FriendlyARM NanoPi K2";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
|
|
|
@ -75,8 +75,8 @@ vddio_card: gpio-regulator {
|
|||
gpios-states = <1>;
|
||||
|
||||
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
|
||||
states = <1800000 0
|
||||
3300000 1>;
|
||||
states = <1800000 0>,
|
||||
<3300000 1>;
|
||||
};
|
||||
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
|
|
|
@ -77,8 +77,8 @@ tf_io: gpio-regulator-tf_io {
|
|||
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0>;
|
||||
|
||||
states = <3300000 0
|
||||
1800000 1>;
|
||||
states = <3300000 0>,
|
||||
<1800000 1>;
|
||||
};
|
||||
|
||||
vcc1v8: regulator-vcc1v8 {
|
||||
|
|
|
@ -21,6 +21,6 @@ ðmac {
|
|||
phy-mode = "rmii";
|
||||
|
||||
snps,reset-gpio = <&gpio GPIOZ_14 0>;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
snps,reset-delays-us = <0>, <10000>, <1000000>;
|
||||
snps,reset-active-low;
|
||||
};
|
||||
|
|
|
@ -46,8 +46,8 @@ vddio_card: gpio-regulator {
|
|||
gpios-states = <1>;
|
||||
|
||||
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
|
||||
states = <1800000 0
|
||||
3300000 1>;
|
||||
states = <1800000 0>,
|
||||
<3300000 1>;
|
||||
|
||||
regulator-settling-time-up-us = <10000>;
|
||||
regulator-settling-time-down-us = <150000>;
|
||||
|
|
|
@ -12,3 +12,7 @@ / {
|
|||
compatible = "wetek,hub", "amlogic,meson-gxbb";
|
||||
model = "WeTek Hub";
|
||||
};
|
||||
|
||||
&ir {
|
||||
linux,rc-map-name = "rc-wetek-hub";
|
||||
};
|
||||
|
|
|
@ -54,3 +54,7 @@ &usb1_phy {
|
|||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ir {
|
||||
linux,rc-map-name = "rc-wetek-play2";
|
||||
};
|
||||
|
|
|
@ -20,3 +20,7 @@ memory@0 {
|
|||
reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */
|
||||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
linux,rc-map-name = "rc-tanix-tx3mini";
|
||||
};
|
||||
|
|
|
@ -38,8 +38,8 @@ vddio_card: gpio-regulator {
|
|||
gpios-states = <1>;
|
||||
|
||||
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
|
||||
states = <1800000 0
|
||||
3300000 1>;
|
||||
states = <1800000 0>,
|
||||
<3300000 1>;
|
||||
};
|
||||
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
|
|
|
@ -110,7 +110,7 @@ rtc: rtc@51 {
|
|||
};
|
||||
|
||||
&ir {
|
||||
linux,rc-map-name = "rc-geekbox";
|
||||
linux,rc-map-name = "rc-khadas";
|
||||
};
|
||||
|
||||
&gpio_ao {
|
||||
|
|
|
@ -38,8 +38,8 @@ vddio_card: gpio-regulator {
|
|||
gpios-states = <1>;
|
||||
|
||||
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
|
||||
states = <1800000 0
|
||||
3300000 1>;
|
||||
states = <1800000 0>,
|
||||
<3300000 1>;
|
||||
};
|
||||
|
||||
vddio_boot: regulator-vddio_boot {
|
||||
|
|
|
@ -80,9 +80,6 @@ &efuse {
|
|||
};
|
||||
|
||||
ðmac {
|
||||
reg = <0x0 0xc9410000 0x0 0x10000
|
||||
0x0 0xc8834540 0x0 0x4>;
|
||||
|
||||
clocks = <&clkc CLKID_ETH>,
|
||||
<&clkc CLKID_FCLK_DIV2>,
|
||||
<&clkc CLKID_MPLL2>;
|
||||
|
@ -712,7 +709,7 @@ internal_mdio: mdio@e40908ff {
|
|||
#size-cells = <0>;
|
||||
|
||||
internal_phy: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
|
||||
compatible = "ethernet-phy-id0181.4400";
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <8>;
|
||||
max-speed = <100>;
|
||||
|
|
|
@ -299,7 +299,7 @@ &ir {
|
|||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
linux,rc-map-name = "rc-geekbox";
|
||||
linux,rc-map-name = "rc-khadas";
|
||||
};
|
||||
|
||||
&pwm_AO_ab {
|
||||
|
|
360
arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
Normal file
360
arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
Normal file
|
@ -0,0 +1,360 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/meson-g12a-gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Khadas VIM3";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
ethernet0 = ðmac;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 2>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1710000>;
|
||||
|
||||
button-function {
|
||||
label = "Function";
|
||||
linux,code = <KEY_FN>;
|
||||
press-threshold-microvolt = <10000>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
white {
|
||||
label = "vim3:white:sys";
|
||||
gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
red {
|
||||
label = "vim3:red";
|
||||
gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
gpio-keys-polled {
|
||||
compatible = "gpio-keys-polled";
|
||||
poll-interval = <100>;
|
||||
|
||||
power-button {
|
||||
label = "power";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&wifi32k>;
|
||||
clock-names = "ext_clock";
|
||||
};
|
||||
|
||||
dc_in: regulator-dc_in {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "DC_IN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_5v: regulator-vcc_5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_in>;
|
||||
|
||||
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-vcc_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_3v3: regulator-vcc_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
/* FIXME: actually controlled by VDDCPU_B_EN */
|
||||
};
|
||||
|
||||
vddao_1v8: regulator-vddao_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_AO1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
emmc_1v8: regulator-emmc_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "EMMC_AO1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vsys_3v3: regulator-vsys_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSYS_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_in>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
usb_pwr: regulator-usb_pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB_PWR";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_5v>;
|
||||
|
||||
gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wifi32k: wifi32k {
|
||||
compatible = "pwm-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
|
||||
};
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
pinctrl-0 = <&cec_ao_a_h_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cecb_AO {
|
||||
pinctrl-0 = <&cec_ao_b_h_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&ext_mdio {
|
||||
external_phy: ethernet-phy@0 {
|
||||
/* Realtek RTL8211F (0x001cc916) */
|
||||
reg = <0>;
|
||||
max-speed = <1000>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
/* MAC_INTR on GPIOZ_14 */
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&external_phy>;
|
||||
amlogic,tx-delay-ns = <2>;
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-supply = <&vcc_5v>;
|
||||
};
|
||||
|
||||
&hdmi_tx_tmds_port {
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
gpio_expander: gpio-controller@20 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x20>;
|
||||
vcc-supply = <&vcc_3v3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
linux,rc-map-name = "rc-khadas";
|
||||
};
|
||||
|
||||
&pwm_ef {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_e_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vddao_1v8>;
|
||||
};
|
||||
|
||||
/* SDIO */
|
||||
&sd_emmc_a {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
pinctrl-1 = <&sdio_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
sd-uhs-sdr50;
|
||||
max-frequency = <100000000>;
|
||||
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
|
||||
vmmc-supply = <&vsys_3v3>;
|
||||
vqmmc-supply = <&vddao_1v8>;
|
||||
|
||||
brcmf: wifi@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
};
|
||||
};
|
||||
|
||||
/* SD card */
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcard_c_pins>;
|
||||
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <50000000>;
|
||||
disable-wp;
|
||||
|
||||
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <&vsys_3v3>;
|
||||
vqmmc-supply = <&vsys_3v3>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
max-frequency = <200000000>;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&emmc_1v8>;
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
|
||||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
|
||||
max-speed = <2000000>;
|
||||
clocks = <&wifi32k>;
|
||||
clock-names = "lpo";
|
||||
};
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
phy-supply = <&dc_in>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
phy-supply = <&usb_pwr>;
|
||||
};
|
||||
|
||||
&usb3_pcie_phy {
|
||||
phy-supply = <&usb_pwr>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
};
|
70
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
Normal file
70
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
Normal file
|
@ -0,0 +1,70 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-sm1.dtsi"
|
||||
#include "meson-khadas-vim3.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "khadas,vim3l", "amlogic,sm1";
|
||||
model = "Khadas VIM3L";
|
||||
|
||||
vddcpu: regulator-vddcpu {
|
||||
/*
|
||||
* Silergy SY8030DEC Regulator.
|
||||
*/
|
||||
compatible = "pwm-regulator";
|
||||
|
||||
regulator-name = "VDDCPU";
|
||||
regulator-min-microvolt = <690000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
|
||||
vin-supply = <&vsys_3v3>;
|
||||
|
||||
pwms = <&pwm_AO_cd 1 1250 0>;
|
||||
pwm-dutycycle-range = <100 0>;
|
||||
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vddcpu>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
clocks = <&clkc CLKID_CPU_CLK>;
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vddcpu>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
clocks = <&clkc CLKID_CPU1_CLK>;
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vddcpu>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
clocks = <&clkc CLKID_CPU2_CLK>;
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vddcpu>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
clocks = <&clkc CLKID_CPU3_CLK>;
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&pwm_AO_cd {
|
||||
pinctrl-0 = <&pwm_ao_d_e_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&xtal>;
|
||||
clock-names = "clkin1";
|
||||
status = "okay";
|
||||
};
|
|
@ -51,6 +51,17 @@ key3 {
|
|||
};
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
|
@ -125,6 +136,25 @@ vddao_3v3_t: regulator-vddao_3v3_t {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddcpu: regulator-vddcpu {
|
||||
/*
|
||||
* SY8120B1ABC DC/DC Regulator.
|
||||
*/
|
||||
compatible = "pwm-regulator";
|
||||
|
||||
regulator-name = "VDDCPU";
|
||||
regulator-min-microvolt = <690000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
|
||||
vin-supply = <&dc_in>;
|
||||
|
||||
pwms = <&pwm_AO_cd 1 1500 0>;
|
||||
pwm-dutycycle-range = <100 0>;
|
||||
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddio_ao1v8: regulator-vddio_ao1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDIO_AO1V8";
|
||||
|
@ -171,12 +201,52 @@ &cecb_AO {
|
|||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vddcpu>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
clocks = <&clkc CLKID_CPU_CLK>;
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vddcpu>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
clocks = <&clkc CLKID_CPU1_CLK>;
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vddcpu>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
clocks = <&clkc CLKID_CPU2_CLK>;
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vddcpu>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
clocks = <&clkc CLKID_CPU3_CLK>;
|
||||
clock-latency = <50000>;
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
phy-handle = <&internal_ephy>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hdmi_tx_tmds_port {
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
|
||||
|
@ -197,6 +267,14 @@ &pwm_AO_ab {
|
|||
clock-names = "clkin0";
|
||||
};
|
||||
|
||||
&pwm_AO_cd {
|
||||
pinctrl-0 = <&pwm_ao_d_e_pins>;
|
||||
pinctrl-names = "default";
|
||||
clocks = <&xtal>;
|
||||
clock-names = "clkin1";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm_ef {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pwm_e_pins>;
|
||||
|
@ -298,3 +376,8 @@ &uart_AO {
|
|||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
|
|
@ -5,6 +5,7 @@
|
|||
*/
|
||||
|
||||
#include "meson-g12-common.dtsi"
|
||||
#include <dt-bindings/power/meson-sm1-power.h>
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,sm1";
|
||||
|
@ -49,6 +50,71 @@ l2: l2-cache0 {
|
|||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <730000>;
|
||||
};
|
||||
|
||||
opp-250000000 {
|
||||
opp-hz = /bits/ 64 <250000000>;
|
||||
opp-microvolt = <730000>;
|
||||
};
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <730000>;
|
||||
};
|
||||
|
||||
opp-667000000 {
|
||||
opp-hz = /bits/ 64 <666666666>;
|
||||
opp-microvolt = <750000>;
|
||||
};
|
||||
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <770000>;
|
||||
};
|
||||
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <780000>;
|
||||
};
|
||||
|
||||
opp-1404000000 {
|
||||
opp-hz = /bits/ 64 <1404000000>;
|
||||
opp-microvolt = <790000>;
|
||||
};
|
||||
|
||||
opp-1512000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
||||
opp-1608000000 {
|
||||
opp-hz = /bits/ 64 <1608000000>;
|
||||
opp-microvolt = <810000>;
|
||||
};
|
||||
|
||||
opp-1704000000 {
|
||||
opp-hz = /bits/ 64 <1704000000>;
|
||||
opp-microvolt = <850000>;
|
||||
};
|
||||
|
||||
opp-1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
|
||||
opp-1908000000 {
|
||||
opp-hz = /bits/ 64 <1908000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cecb_AO {
|
||||
|
@ -59,10 +125,23 @@ &clk_msr {
|
|||
compatible = "amlogic,meson-sm1-clk-measure";
|
||||
};
|
||||
|
||||
&pwrc_vpu {
|
||||
status = "disabled";
|
||||
|
||||
&clkc {
|
||||
compatible = "amlogic,sm1-clkc";
|
||||
};
|
||||
|
||||
ðmac {
|
||||
power-domains = <&pwrc PWRC_SM1_ETH_ID>;
|
||||
};
|
||||
|
||||
&pwrc {
|
||||
compatible = "amlogic,meson-sm1-pwrc";
|
||||
};
|
||||
|
||||
&vpu {
|
||||
status = "disabled";
|
||||
power-domains = <&pwrc PWRC_SM1_VPU_ID>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
power-domains = <&pwrc PWRC_SM1_USB_ID>;
|
||||
};
|
||||
|
|
|
@ -37,6 +37,17 @@ config MESON_GX_PM_DOMAINS
|
|||
Say yes to expose Amlogic Meson GX Power Domains as
|
||||
Generic Power Domains.
|
||||
|
||||
config MESON_EE_PM_DOMAINS
|
||||
bool "Amlogic Meson Everything-Else Power Domains driver"
|
||||
depends on ARCH_MESON || COMPILE_TEST
|
||||
depends on PM && OF
|
||||
default ARCH_MESON
|
||||
select PM_GENERIC_DOMAINS
|
||||
select PM_GENERIC_DOMAINS_OF
|
||||
help
|
||||
Say yes to expose Amlogic Meson Everything-Else Power Domains as
|
||||
Generic Power Domains.
|
||||
|
||||
config MESON_MX_SOCINFO
|
||||
bool "Amlogic Meson MX SoC Information driver"
|
||||
depends on ARCH_MESON || COMPILE_TEST
|
||||
|
|
|
@ -4,3 +4,4 @@ obj-$(CONFIG_MESON_CLK_MEASURE) += meson-clk-measure.o
|
|||
obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
|
||||
obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
|
||||
obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
|
||||
obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o
|
||||
|
|
|
@ -11,6 +11,8 @@
|
|||
#include <linux/debugfs.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
static DEFINE_MUTEX(measure_lock);
|
||||
|
||||
#define MSR_CLK_DUTY 0x0
|
||||
#define MSR_CLK_REG0 0x4
|
||||
#define MSR_CLK_REG1 0x8
|
||||
|
@ -322,6 +324,8 @@ static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = {
|
|||
CLK_MSR_ID(84, "co_tx"),
|
||||
CLK_MSR_ID(89, "hdmi_todig"),
|
||||
CLK_MSR_ID(90, "hdmitx_sys"),
|
||||
CLK_MSR_ID(91, "sys_cpub_div16"),
|
||||
CLK_MSR_ID(92, "sys_pll_cpub_div16"),
|
||||
CLK_MSR_ID(94, "eth_phy_rx"),
|
||||
CLK_MSR_ID(95, "eth_phy_pll"),
|
||||
CLK_MSR_ID(96, "vpu_b"),
|
||||
|
@ -353,6 +357,136 @@ static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = {
|
|||
CLK_MSR_ID(122, "audio_pdm_dclk"),
|
||||
};
|
||||
|
||||
static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = {
|
||||
CLK_MSR_ID(0, "ring_osc_out_ee_0"),
|
||||
CLK_MSR_ID(1, "ring_osc_out_ee_1"),
|
||||
CLK_MSR_ID(2, "ring_osc_out_ee_2"),
|
||||
CLK_MSR_ID(3, "ring_osc_out_ee_3"),
|
||||
CLK_MSR_ID(4, "gp0_pll"),
|
||||
CLK_MSR_ID(5, "gp1_pll"),
|
||||
CLK_MSR_ID(6, "enci"),
|
||||
CLK_MSR_ID(7, "clk81"),
|
||||
CLK_MSR_ID(8, "encp"),
|
||||
CLK_MSR_ID(9, "encl"),
|
||||
CLK_MSR_ID(10, "vdac"),
|
||||
CLK_MSR_ID(11, "eth_tx"),
|
||||
CLK_MSR_ID(12, "hifi_pll"),
|
||||
CLK_MSR_ID(13, "mod_tcon"),
|
||||
CLK_MSR_ID(14, "fec_0"),
|
||||
CLK_MSR_ID(15, "fec_1"),
|
||||
CLK_MSR_ID(16, "fec_2"),
|
||||
CLK_MSR_ID(17, "sys_pll_div16"),
|
||||
CLK_MSR_ID(18, "sys_cpu_div16"),
|
||||
CLK_MSR_ID(19, "lcd_an_ph2"),
|
||||
CLK_MSR_ID(20, "rtc_osc_out"),
|
||||
CLK_MSR_ID(21, "lcd_an_ph3"),
|
||||
CLK_MSR_ID(22, "eth_phy_ref"),
|
||||
CLK_MSR_ID(23, "mpll_50m"),
|
||||
CLK_MSR_ID(24, "eth_125m"),
|
||||
CLK_MSR_ID(25, "eth_rmii"),
|
||||
CLK_MSR_ID(26, "sc_int"),
|
||||
CLK_MSR_ID(27, "in_mac"),
|
||||
CLK_MSR_ID(28, "sar_adc"),
|
||||
CLK_MSR_ID(29, "pcie_inp"),
|
||||
CLK_MSR_ID(30, "pcie_inn"),
|
||||
CLK_MSR_ID(31, "mpll_test_out"),
|
||||
CLK_MSR_ID(32, "vdec"),
|
||||
CLK_MSR_ID(34, "eth_mpll_50m"),
|
||||
CLK_MSR_ID(35, "mali"),
|
||||
CLK_MSR_ID(36, "hdmi_tx_pixel"),
|
||||
CLK_MSR_ID(37, "cdac"),
|
||||
CLK_MSR_ID(38, "vdin_meas"),
|
||||
CLK_MSR_ID(39, "bt656"),
|
||||
CLK_MSR_ID(40, "arm_ring_osc_out_4"),
|
||||
CLK_MSR_ID(41, "eth_rx_or_rmii"),
|
||||
CLK_MSR_ID(42, "mp0_out"),
|
||||
CLK_MSR_ID(43, "fclk_div5"),
|
||||
CLK_MSR_ID(44, "pwm_b"),
|
||||
CLK_MSR_ID(45, "pwm_a"),
|
||||
CLK_MSR_ID(46, "vpu"),
|
||||
CLK_MSR_ID(47, "ddr_dpll_pt"),
|
||||
CLK_MSR_ID(48, "mp1_out"),
|
||||
CLK_MSR_ID(49, "mp2_out"),
|
||||
CLK_MSR_ID(50, "mp3_out"),
|
||||
CLK_MSR_ID(51, "sd_emmc_c"),
|
||||
CLK_MSR_ID(52, "sd_emmc_b"),
|
||||
CLK_MSR_ID(53, "sd_emmc_a"),
|
||||
CLK_MSR_ID(54, "vpu_clkc"),
|
||||
CLK_MSR_ID(55, "vid_pll_div_out"),
|
||||
CLK_MSR_ID(56, "wave420l_a"),
|
||||
CLK_MSR_ID(57, "wave420l_c"),
|
||||
CLK_MSR_ID(58, "wave420l_b"),
|
||||
CLK_MSR_ID(59, "hcodec"),
|
||||
CLK_MSR_ID(60, "arm_ring_osc_out_5"),
|
||||
CLK_MSR_ID(61, "gpio_msr"),
|
||||
CLK_MSR_ID(62, "hevcb"),
|
||||
CLK_MSR_ID(63, "dsi_meas"),
|
||||
CLK_MSR_ID(64, "spicc_1"),
|
||||
CLK_MSR_ID(65, "spicc_0"),
|
||||
CLK_MSR_ID(66, "vid_lock"),
|
||||
CLK_MSR_ID(67, "dsi_phy"),
|
||||
CLK_MSR_ID(68, "hdcp22_esm"),
|
||||
CLK_MSR_ID(69, "hdcp22_skp"),
|
||||
CLK_MSR_ID(70, "pwm_f"),
|
||||
CLK_MSR_ID(71, "pwm_e"),
|
||||
CLK_MSR_ID(72, "pwm_d"),
|
||||
CLK_MSR_ID(73, "pwm_c"),
|
||||
CLK_MSR_ID(74, "arm_ring_osc_out_6"),
|
||||
CLK_MSR_ID(75, "hevcf"),
|
||||
CLK_MSR_ID(76, "arm_ring_osc_out_7"),
|
||||
CLK_MSR_ID(77, "rng_ring_osc_0"),
|
||||
CLK_MSR_ID(78, "rng_ring_osc_1"),
|
||||
CLK_MSR_ID(79, "rng_ring_osc_2"),
|
||||
CLK_MSR_ID(80, "rng_ring_osc_3"),
|
||||
CLK_MSR_ID(81, "vapb"),
|
||||
CLK_MSR_ID(82, "ge2d"),
|
||||
CLK_MSR_ID(83, "co_rx"),
|
||||
CLK_MSR_ID(84, "co_tx"),
|
||||
CLK_MSR_ID(85, "arm_ring_osc_out_8"),
|
||||
CLK_MSR_ID(86, "arm_ring_osc_out_9"),
|
||||
CLK_MSR_ID(87, "mipi_dsi_phy"),
|
||||
CLK_MSR_ID(88, "cis2_adapt"),
|
||||
CLK_MSR_ID(89, "hdmi_todig"),
|
||||
CLK_MSR_ID(90, "hdmitx_sys"),
|
||||
CLK_MSR_ID(91, "nna_core"),
|
||||
CLK_MSR_ID(92, "nna_axi"),
|
||||
CLK_MSR_ID(93, "vad"),
|
||||
CLK_MSR_ID(94, "eth_phy_rx"),
|
||||
CLK_MSR_ID(95, "eth_phy_pll"),
|
||||
CLK_MSR_ID(96, "vpu_b"),
|
||||
CLK_MSR_ID(97, "cpu_b_tmp"),
|
||||
CLK_MSR_ID(98, "ts"),
|
||||
CLK_MSR_ID(99, "arm_ring_osc_out_10"),
|
||||
CLK_MSR_ID(100, "arm_ring_osc_out_11"),
|
||||
CLK_MSR_ID(101, "arm_ring_osc_out_12"),
|
||||
CLK_MSR_ID(102, "arm_ring_osc_out_13"),
|
||||
CLK_MSR_ID(103, "arm_ring_osc_out_14"),
|
||||
CLK_MSR_ID(104, "arm_ring_osc_out_15"),
|
||||
CLK_MSR_ID(105, "arm_ring_osc_out_16"),
|
||||
CLK_MSR_ID(106, "ephy_test"),
|
||||
CLK_MSR_ID(107, "au_dac_g128x"),
|
||||
CLK_MSR_ID(108, "audio_locker_out"),
|
||||
CLK_MSR_ID(109, "audio_locker_in"),
|
||||
CLK_MSR_ID(110, "audio_tdmout_c_sclk"),
|
||||
CLK_MSR_ID(111, "audio_tdmout_b_sclk"),
|
||||
CLK_MSR_ID(112, "audio_tdmout_a_sclk"),
|
||||
CLK_MSR_ID(113, "audio_tdmin_lb_sclk"),
|
||||
CLK_MSR_ID(114, "audio_tdmin_c_sclk"),
|
||||
CLK_MSR_ID(115, "audio_tdmin_b_sclk"),
|
||||
CLK_MSR_ID(116, "audio_tdmin_a_sclk"),
|
||||
CLK_MSR_ID(117, "audio_resample"),
|
||||
CLK_MSR_ID(118, "audio_pdm_sys"),
|
||||
CLK_MSR_ID(119, "audio_spdifout_b"),
|
||||
CLK_MSR_ID(120, "audio_spdifout"),
|
||||
CLK_MSR_ID(121, "audio_spdifin"),
|
||||
CLK_MSR_ID(122, "audio_pdm_dclk"),
|
||||
CLK_MSR_ID(123, "audio_resampled"),
|
||||
CLK_MSR_ID(124, "earcrx_pll"),
|
||||
CLK_MSR_ID(125, "earcrx_pll_test"),
|
||||
CLK_MSR_ID(126, "csi_phy0"),
|
||||
CLK_MSR_ID(127, "csi2_data"),
|
||||
};
|
||||
|
||||
static int meson_measure_id(struct meson_msr_id *clk_msr_id,
|
||||
unsigned int duration)
|
||||
{
|
||||
|
@ -360,6 +494,10 @@ static int meson_measure_id(struct meson_msr_id *clk_msr_id,
|
|||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
ret = mutex_lock_interruptible(&measure_lock);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap_write(priv->regmap, MSR_CLK_REG0, 0);
|
||||
|
||||
/* Set measurement duration */
|
||||
|
@ -377,8 +515,10 @@ static int meson_measure_id(struct meson_msr_id *clk_msr_id,
|
|||
|
||||
ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0,
|
||||
val, !(val & MSR_BUSY), 10, 10000);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
mutex_unlock(&measure_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Disable */
|
||||
regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0);
|
||||
|
@ -386,6 +526,8 @@ static int meson_measure_id(struct meson_msr_id *clk_msr_id,
|
|||
/* Get the value in multiple of gate time counts */
|
||||
regmap_read(priv->regmap, MSR_CLK_REG2, &val);
|
||||
|
||||
mutex_unlock(&measure_lock);
|
||||
|
||||
if (val >= MSR_VAL_MASK)
|
||||
return -EINVAL;
|
||||
|
||||
|
@ -533,6 +675,10 @@ static const struct of_device_id meson_msr_match_table[] = {
|
|||
.compatible = "amlogic,meson-g12a-clk-measure",
|
||||
.data = (void *)clk_msr_g12a,
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-sm1-clk-measure",
|
||||
.data = (void *)clk_msr_sm1,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
492
drivers/soc/amlogic/meson-ee-pwrc.c
Normal file
492
drivers/soc/amlogic/meson-ee-pwrc.c
Normal file
|
@ -0,0 +1,492 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/clk.h>
|
||||
#include <dt-bindings/power/meson-g12a-power.h>
|
||||
#include <dt-bindings/power/meson-sm1-power.h>
|
||||
|
||||
/* AO Offsets */
|
||||
|
||||
#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
|
||||
#define AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
|
||||
|
||||
/* HHI Offsets */
|
||||
|
||||
#define HHI_MEM_PD_REG0 (0x40 << 2)
|
||||
#define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
|
||||
#define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
|
||||
#define HHI_VPU_MEM_PD_REG3 (0x43 << 2)
|
||||
#define HHI_VPU_MEM_PD_REG4 (0x44 << 2)
|
||||
#define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2)
|
||||
#define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2)
|
||||
#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
|
||||
#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
|
||||
|
||||
struct meson_ee_pwrc;
|
||||
struct meson_ee_pwrc_domain;
|
||||
|
||||
struct meson_ee_pwrc_mem_domain {
|
||||
unsigned int reg;
|
||||
unsigned int mask;
|
||||
};
|
||||
|
||||
struct meson_ee_pwrc_top_domain {
|
||||
unsigned int sleep_reg;
|
||||
unsigned int sleep_mask;
|
||||
unsigned int iso_reg;
|
||||
unsigned int iso_mask;
|
||||
};
|
||||
|
||||
struct meson_ee_pwrc_domain_desc {
|
||||
char *name;
|
||||
unsigned int reset_names_count;
|
||||
unsigned int clk_names_count;
|
||||
struct meson_ee_pwrc_top_domain *top_pd;
|
||||
unsigned int mem_pd_count;
|
||||
struct meson_ee_pwrc_mem_domain *mem_pd;
|
||||
bool (*get_power)(struct meson_ee_pwrc_domain *pwrc_domain);
|
||||
};
|
||||
|
||||
struct meson_ee_pwrc_domain_data {
|
||||
unsigned int count;
|
||||
struct meson_ee_pwrc_domain_desc *domains;
|
||||
};
|
||||
|
||||
/* TOP Power Domains */
|
||||
|
||||
static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
|
||||
.sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
|
||||
.sleep_mask = BIT(8),
|
||||
.iso_reg = AO_RTI_GEN_PWR_SLEEP0,
|
||||
.iso_mask = BIT(9),
|
||||
};
|
||||
|
||||
#define SM1_EE_PD(__bit) \
|
||||
{ \
|
||||
.sleep_reg = AO_RTI_GEN_PWR_SLEEP0, \
|
||||
.sleep_mask = BIT(__bit), \
|
||||
.iso_reg = AO_RTI_GEN_PWR_ISO0, \
|
||||
.iso_mask = BIT(__bit), \
|
||||
}
|
||||
|
||||
static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
|
||||
static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
|
||||
static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
|
||||
static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
|
||||
static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
|
||||
|
||||
/* Memory PD Domains */
|
||||
|
||||
#define VPU_MEMPD(__reg) \
|
||||
{ __reg, GENMASK(1, 0) }, \
|
||||
{ __reg, GENMASK(3, 2) }, \
|
||||
{ __reg, GENMASK(5, 4) }, \
|
||||
{ __reg, GENMASK(7, 6) }, \
|
||||
{ __reg, GENMASK(9, 8) }, \
|
||||
{ __reg, GENMASK(11, 10) }, \
|
||||
{ __reg, GENMASK(13, 12) }, \
|
||||
{ __reg, GENMASK(15, 14) }, \
|
||||
{ __reg, GENMASK(17, 16) }, \
|
||||
{ __reg, GENMASK(19, 18) }, \
|
||||
{ __reg, GENMASK(21, 20) }, \
|
||||
{ __reg, GENMASK(23, 22) }, \
|
||||
{ __reg, GENMASK(25, 24) }, \
|
||||
{ __reg, GENMASK(27, 26) }, \
|
||||
{ __reg, GENMASK(29, 28) }, \
|
||||
{ __reg, GENMASK(31, 30) }
|
||||
|
||||
#define VPU_HHI_MEMPD(__reg) \
|
||||
{ __reg, BIT(8) }, \
|
||||
{ __reg, BIT(9) }, \
|
||||
{ __reg, BIT(10) }, \
|
||||
{ __reg, BIT(11) }, \
|
||||
{ __reg, BIT(12) }, \
|
||||
{ __reg, BIT(13) }, \
|
||||
{ __reg, BIT(14) }, \
|
||||
{ __reg, BIT(15) }
|
||||
|
||||
static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
|
||||
VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
|
||||
VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
|
||||
VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
|
||||
VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
|
||||
{ HHI_MEM_PD_REG0, GENMASK(3, 2) },
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
|
||||
VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
|
||||
VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
|
||||
VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
|
||||
VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
|
||||
{ HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
|
||||
{ HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
|
||||
{ HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
|
||||
{ HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
|
||||
VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
|
||||
{ HHI_NANOQ_MEM_PD_REG0, 0xff },
|
||||
{ HHI_NANOQ_MEM_PD_REG1, 0xff },
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
|
||||
{ HHI_MEM_PD_REG0, GENMASK(31, 30) },
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
|
||||
{ HHI_MEM_PD_REG0, GENMASK(29, 26) },
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
|
||||
{ HHI_MEM_PD_REG0, GENMASK(25, 18) },
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
|
||||
{ HHI_MEM_PD_REG0, GENMASK(5, 4) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
|
||||
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
|
||||
};
|
||||
|
||||
#define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks) \
|
||||
{ \
|
||||
.name = __name, \
|
||||
.reset_names_count = __resets, \
|
||||
.clk_names_count = __clks, \
|
||||
.top_pd = __top_pd, \
|
||||
.mem_pd_count = ARRAY_SIZE(__mem), \
|
||||
.mem_pd = __mem, \
|
||||
.get_power = __get_power, \
|
||||
}
|
||||
|
||||
#define TOP_PD(__name, __top_pd, __mem, __get_power) \
|
||||
{ \
|
||||
.name = __name, \
|
||||
.top_pd = __top_pd, \
|
||||
.mem_pd_count = ARRAY_SIZE(__mem), \
|
||||
.mem_pd = __mem, \
|
||||
.get_power = __get_power, \
|
||||
}
|
||||
|
||||
#define MEM_PD(__name, __mem) \
|
||||
TOP_PD(__name, NULL, __mem, NULL)
|
||||
|
||||
static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain);
|
||||
|
||||
static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
|
||||
[PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
|
||||
pwrc_ee_get_power, 11, 2),
|
||||
[PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
|
||||
[PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
|
||||
pwrc_ee_get_power, 11, 2),
|
||||
[PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
|
||||
pwrc_ee_get_power),
|
||||
[PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
|
||||
pwrc_ee_get_power),
|
||||
[PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
|
||||
pwrc_ee_get_power),
|
||||
[PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
|
||||
pwrc_ee_get_power),
|
||||
[PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
|
||||
[PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
|
||||
};
|
||||
|
||||
struct meson_ee_pwrc_domain {
|
||||
struct generic_pm_domain base;
|
||||
bool enabled;
|
||||
struct meson_ee_pwrc *pwrc;
|
||||
struct meson_ee_pwrc_domain_desc desc;
|
||||
struct clk_bulk_data *clks;
|
||||
int num_clks;
|
||||
struct reset_control *rstc;
|
||||
int num_rstc;
|
||||
};
|
||||
|
||||
struct meson_ee_pwrc {
|
||||
struct regmap *regmap_ao;
|
||||
struct regmap *regmap_hhi;
|
||||
struct meson_ee_pwrc_domain *domains;
|
||||
struct genpd_onecell_data xlate;
|
||||
};
|
||||
|
||||
static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
regmap_read(pwrc_domain->pwrc->regmap_ao,
|
||||
pwrc_domain->desc.top_pd->sleep_reg, ®);
|
||||
|
||||
return (reg & pwrc_domain->desc.top_pd->sleep_mask);
|
||||
}
|
||||
|
||||
static int meson_ee_pwrc_off(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct meson_ee_pwrc_domain *pwrc_domain =
|
||||
container_of(domain, struct meson_ee_pwrc_domain, base);
|
||||
int i;
|
||||
|
||||
if (pwrc_domain->desc.top_pd)
|
||||
regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
|
||||
pwrc_domain->desc.top_pd->sleep_reg,
|
||||
pwrc_domain->desc.top_pd->sleep_mask,
|
||||
pwrc_domain->desc.top_pd->sleep_mask);
|
||||
udelay(20);
|
||||
|
||||
for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
|
||||
regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
|
||||
pwrc_domain->desc.mem_pd[i].reg,
|
||||
pwrc_domain->desc.mem_pd[i].mask,
|
||||
pwrc_domain->desc.mem_pd[i].mask);
|
||||
|
||||
udelay(20);
|
||||
|
||||
if (pwrc_domain->desc.top_pd)
|
||||
regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
|
||||
pwrc_domain->desc.top_pd->iso_reg,
|
||||
pwrc_domain->desc.top_pd->iso_mask,
|
||||
pwrc_domain->desc.top_pd->iso_mask);
|
||||
|
||||
if (pwrc_domain->num_clks) {
|
||||
msleep(20);
|
||||
clk_bulk_disable_unprepare(pwrc_domain->num_clks,
|
||||
pwrc_domain->clks);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_ee_pwrc_on(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct meson_ee_pwrc_domain *pwrc_domain =
|
||||
container_of(domain, struct meson_ee_pwrc_domain, base);
|
||||
int i, ret;
|
||||
|
||||
if (pwrc_domain->desc.top_pd)
|
||||
regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
|
||||
pwrc_domain->desc.top_pd->sleep_reg,
|
||||
pwrc_domain->desc.top_pd->sleep_mask, 0);
|
||||
udelay(20);
|
||||
|
||||
for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
|
||||
regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
|
||||
pwrc_domain->desc.mem_pd[i].reg,
|
||||
pwrc_domain->desc.mem_pd[i].mask, 0);
|
||||
|
||||
udelay(20);
|
||||
|
||||
ret = reset_control_assert(pwrc_domain->rstc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (pwrc_domain->desc.top_pd)
|
||||
regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
|
||||
pwrc_domain->desc.top_pd->iso_reg,
|
||||
pwrc_domain->desc.top_pd->iso_mask, 0);
|
||||
|
||||
ret = reset_control_deassert(pwrc_domain->rstc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return clk_bulk_prepare_enable(pwrc_domain->num_clks,
|
||||
pwrc_domain->clks);
|
||||
}
|
||||
|
||||
static int meson_ee_pwrc_init_domain(struct platform_device *pdev,
|
||||
struct meson_ee_pwrc *pwrc,
|
||||
struct meson_ee_pwrc_domain *dom)
|
||||
{
|
||||
dom->pwrc = pwrc;
|
||||
dom->num_rstc = dom->desc.reset_names_count;
|
||||
dom->num_clks = dom->desc.clk_names_count;
|
||||
|
||||
if (dom->num_rstc) {
|
||||
int count = reset_control_get_count(&pdev->dev);
|
||||
|
||||
if (count != dom->num_rstc)
|
||||
dev_warn(&pdev->dev, "Invalid resets count %d for domain %s\n",
|
||||
count, dom->desc.name);
|
||||
|
||||
dom->rstc = devm_reset_control_array_get(&pdev->dev, false,
|
||||
false);
|
||||
if (IS_ERR(dom->rstc))
|
||||
return PTR_ERR(dom->rstc);
|
||||
}
|
||||
|
||||
if (dom->num_clks) {
|
||||
int ret = devm_clk_bulk_get_all(&pdev->dev, &dom->clks);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (dom->num_clks != ret) {
|
||||
dev_warn(&pdev->dev, "Invalid clocks count %d for domain %s\n",
|
||||
ret, dom->desc.name);
|
||||
dom->num_clks = ret;
|
||||
}
|
||||
}
|
||||
|
||||
dom->base.name = dom->desc.name;
|
||||
dom->base.power_on = meson_ee_pwrc_on;
|
||||
dom->base.power_off = meson_ee_pwrc_off;
|
||||
|
||||
/*
|
||||
* TOFIX: This is a special case for the VPU power domain, which can
|
||||
* be enabled previously by the bootloader. In this case the VPU
|
||||
* pipeline may be functional but no driver maybe never attach
|
||||
* to this power domain, and if the domain is disabled it could
|
||||
* cause system errors. This is why the pm_domain_always_on_gov
|
||||
* is used here.
|
||||
* For the same reason, the clocks should be enabled in case
|
||||
* we need to power the domain off, otherwise the internal clocks
|
||||
* prepare/enable counters won't be in sync.
|
||||
*/
|
||||
if (dom->num_clks && dom->desc.get_power && !dom->desc.get_power(dom)) {
|
||||
int ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pm_genpd_init(&dom->base, &pm_domain_always_on_gov, false);
|
||||
} else
|
||||
pm_genpd_init(&dom->base, NULL,
|
||||
(dom->desc.get_power ?
|
||||
dom->desc.get_power(dom) : true));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_ee_pwrc_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct meson_ee_pwrc_domain_data *match;
|
||||
struct regmap *regmap_ao, *regmap_hhi;
|
||||
struct meson_ee_pwrc *pwrc;
|
||||
int i, ret;
|
||||
|
||||
match = of_device_get_match_data(&pdev->dev);
|
||||
if (!match) {
|
||||
dev_err(&pdev->dev, "failed to get match data\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL);
|
||||
if (!pwrc)
|
||||
return -ENOMEM;
|
||||
|
||||
pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count,
|
||||
sizeof(*pwrc->xlate.domains),
|
||||
GFP_KERNEL);
|
||||
if (!pwrc->xlate.domains)
|
||||
return -ENOMEM;
|
||||
|
||||
pwrc->domains = devm_kcalloc(&pdev->dev, match->count,
|
||||
sizeof(*pwrc->domains), GFP_KERNEL);
|
||||
if (!pwrc->domains)
|
||||
return -ENOMEM;
|
||||
|
||||
pwrc->xlate.num_domains = match->count;
|
||||
|
||||
regmap_hhi = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
|
||||
if (IS_ERR(regmap_hhi)) {
|
||||
dev_err(&pdev->dev, "failed to get HHI regmap\n");
|
||||
return PTR_ERR(regmap_hhi);
|
||||
}
|
||||
|
||||
regmap_ao = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
||||
"amlogic,ao-sysctrl");
|
||||
if (IS_ERR(regmap_ao)) {
|
||||
dev_err(&pdev->dev, "failed to get AO regmap\n");
|
||||
return PTR_ERR(regmap_ao);
|
||||
}
|
||||
|
||||
pwrc->regmap_ao = regmap_ao;
|
||||
pwrc->regmap_hhi = regmap_hhi;
|
||||
|
||||
platform_set_drvdata(pdev, pwrc);
|
||||
|
||||
for (i = 0 ; i < match->count ; ++i) {
|
||||
struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
|
||||
|
||||
memcpy(&dom->desc, &match->domains[i], sizeof(dom->desc));
|
||||
|
||||
ret = meson_ee_pwrc_init_domain(pdev, pwrc, dom);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pwrc->xlate.domains[i] = &dom->base;
|
||||
}
|
||||
|
||||
of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void meson_ee_pwrc_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct meson_ee_pwrc *pwrc = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
||||
for (i = 0 ; i < pwrc->xlate.num_domains ; ++i) {
|
||||
struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
|
||||
|
||||
if (dom->desc.get_power && !dom->desc.get_power(dom))
|
||||
meson_ee_pwrc_off(&dom->base);
|
||||
}
|
||||
}
|
||||
|
||||
static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
|
||||
.count = ARRAY_SIZE(g12a_pwrc_domains),
|
||||
.domains = g12a_pwrc_domains,
|
||||
};
|
||||
|
||||
static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
|
||||
.count = ARRAY_SIZE(sm1_pwrc_domains),
|
||||
.domains = sm1_pwrc_domains,
|
||||
};
|
||||
|
||||
static const struct of_device_id meson_ee_pwrc_match_table[] = {
|
||||
{
|
||||
.compatible = "amlogic,meson-g12a-pwrc",
|
||||
.data = &meson_ee_g12a_pwrc_data,
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-sm1-pwrc",
|
||||
.data = &meson_ee_sm1_pwrc_data,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver meson_ee_pwrc_driver = {
|
||||
.probe = meson_ee_pwrc_probe,
|
||||
.shutdown = meson_ee_pwrc_shutdown,
|
||||
.driver = {
|
||||
.name = "meson_ee_pwrc",
|
||||
.of_match_table = meson_ee_pwrc_match_table,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(meson_ee_pwrc_driver);
|
|
@ -39,6 +39,7 @@ static const struct meson_gx_soc_id {
|
|||
{ "TXHD", 0x27 },
|
||||
{ "G12A", 0x28 },
|
||||
{ "G12B", 0x29 },
|
||||
{ "SM1", 0x2b },
|
||||
};
|
||||
|
||||
static const struct meson_gx_package_id {
|
||||
|
@ -65,6 +66,8 @@ static const struct meson_gx_package_id {
|
|||
{ "S905D2", 0x28, 0x10, 0xf0 },
|
||||
{ "S905X2", 0x28, 0x40, 0xf0 },
|
||||
{ "S922X", 0x29, 0x40, 0xf0 },
|
||||
{ "A311D", 0x29, 0x10, 0xf0 },
|
||||
{ "S905X3", 0x2b, 0x5, 0xf },
|
||||
};
|
||||
|
||||
static inline unsigned int socinfo_to_major(u32 socinfo)
|
||||
|
@ -138,8 +141,10 @@ static int __init meson_gx_socinfo_init(void)
|
|||
}
|
||||
|
||||
/* check if chip-id is available */
|
||||
if (!of_property_read_bool(np, "amlogic,has-chip-id"))
|
||||
if (!of_property_read_bool(np, "amlogic,has-chip-id")) {
|
||||
of_node_put(np);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* node should be a syscon */
|
||||
regmap = syscon_node_to_regmap(np);
|
||||
|
|
|
@ -138,5 +138,10 @@
|
|||
#define CLKID_VDEC_HEVCF 210
|
||||
#define CLKID_TS 212
|
||||
#define CLKID_CPUB_CLK 224
|
||||
#define CLKID_GP1_PLL 243
|
||||
#define CLKID_DSU_CLK 252
|
||||
#define CLKID_CPU1_CLK 253
|
||||
#define CLKID_CPU2_CLK 254
|
||||
#define CLKID_CPU3_CLK 255
|
||||
|
||||
#endif /* __G12A_CLKC_H */
|
||||
|
|
13
include/dt-bindings/power/meson-g12a-power.h
Normal file
13
include/dt-bindings/power/meson-g12a-power.h
Normal file
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON_G12A_POWER_H
|
||||
#define _DT_BINDINGS_MESON_G12A_POWER_H
|
||||
|
||||
#define PWRC_G12A_VPU_ID 0
|
||||
#define PWRC_G12A_ETH_ID 1
|
||||
|
||||
#endif
|
18
include/dt-bindings/power/meson-sm1-power.h
Normal file
18
include/dt-bindings/power/meson-sm1-power.h
Normal file
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON_SM1_POWER_H
|
||||
#define _DT_BINDINGS_MESON_SM1_POWER_H
|
||||
|
||||
#define PWRC_SM1_VPU_ID 0
|
||||
#define PWRC_SM1_NNA_ID 1
|
||||
#define PWRC_SM1_USB_ID 2
|
||||
#define PWRC_SM1_PCIE_ID 3
|
||||
#define PWRC_SM1_GE2D_ID 4
|
||||
#define PWRC_SM1_AUDIO_ID 5
|
||||
#define PWRC_SM1_ETH_ID 6
|
||||
|
||||
#endif
|
38
include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
Normal file
38
include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
Normal file
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
|
||||
|
||||
#define AUD_RESET_PDM 0
|
||||
#define AUD_RESET_TDMIN_A 1
|
||||
#define AUD_RESET_TDMIN_B 2
|
||||
#define AUD_RESET_TDMIN_C 3
|
||||
#define AUD_RESET_TDMIN_LB 4
|
||||
#define AUD_RESET_LOOPBACK 5
|
||||
#define AUD_RESET_TODDR_A 6
|
||||
#define AUD_RESET_TODDR_B 7
|
||||
#define AUD_RESET_TODDR_C 8
|
||||
#define AUD_RESET_FRDDR_A 9
|
||||
#define AUD_RESET_FRDDR_B 10
|
||||
#define AUD_RESET_FRDDR_C 11
|
||||
#define AUD_RESET_TDMOUT_A 12
|
||||
#define AUD_RESET_TDMOUT_B 13
|
||||
#define AUD_RESET_TDMOUT_C 14
|
||||
#define AUD_RESET_SPDIFOUT 15
|
||||
#define AUD_RESET_SPDIFOUT_B 16
|
||||
#define AUD_RESET_SPDIFIN 17
|
||||
#define AUD_RESET_EQDRC 18
|
||||
#define AUD_RESET_RESAMPLE 19
|
||||
#define AUD_RESET_DDRARB 20
|
||||
#define AUD_RESET_POWDET 21
|
||||
#define AUD_RESET_TORAM 22
|
||||
#define AUD_RESET_TOACODEC 23
|
||||
#define AUD_RESET_TOHDMITX 24
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||||
#define AUD_RESET_CLKTREE 25
|
||||
|
||||
#endif
|
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Reference in a new issue