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drm/amdgpu: switch to golden tsc registers for raven/raven2
Due to raven/raven2 maybe enable sclk slow down, they cannot get clock count by the RLC at the auto level of dpm performance. So switch to golden tsc register. Suggested-by: shanshengwang <shansheng.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 40 additions and 0 deletions
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@ -149,6 +149,16 @@ MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin");
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#define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026
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#define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_UPPER_Raven 0x007a
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#define mmGOLDEN_TSC_COUNT_UPPER_Raven_BASE_IDX 0
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#define mmGOLDEN_TSC_COUNT_LOWER_Raven 0x007b
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#define mmGOLDEN_TSC_COUNT_LOWER_Raven_BASE_IDX 0
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#define mmGOLDEN_TSC_COUNT_UPPER_Raven2 0x0068
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#define mmGOLDEN_TSC_COUNT_UPPER_Raven2_BASE_IDX 0
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#define mmGOLDEN_TSC_COUNT_LOWER_Raven2 0x0069
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#define mmGOLDEN_TSC_COUNT_LOWER_Raven2_BASE_IDX 0
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enum ta_ras_gfx_subblock {
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/*CPC*/
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TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
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@ -3988,6 +3998,36 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
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preempt_enable();
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clock = clock_lo | (clock_hi << 32ULL);
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break;
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case IP_VERSION(9, 1, 0):
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preempt_disable();
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clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
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clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
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hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
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/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
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* roughly every 42 seconds.
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*/
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if (hi_check != clock_hi) {
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clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
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clock_hi = hi_check;
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}
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preempt_enable();
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clock = clock_lo | (clock_hi << 32ULL);
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break;
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case IP_VERSION(9, 2, 2):
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preempt_disable();
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clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
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clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
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hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
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/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
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* roughly every 42 seconds.
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*/
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if (hi_check != clock_hi) {
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clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
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clock_hi = hi_check;
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}
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preempt_enable();
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clock = clock_lo | (clock_hi << 32ULL);
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break;
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default:
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amdgpu_gfx_off_ctrl(adev, false);
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mutex_lock(&adev->gfx.gpu_clock_mutex);
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