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clk: meson: migrate dividers to clk_regmap
Move meson8b, gxbb and axg clocks using clk_divider to clk_regmap Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
parent
7f9768a540
commit
f06ddd2852
3 changed files with 142 additions and 159 deletions
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@ -433,14 +433,15 @@ static struct clk_mux axg_mpeg_clk_sel = {
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},
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};
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static struct clk_divider axg_mpeg_clk_div = {
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.reg = (void *)HHI_MPEG_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &meson_clk_lock,
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static struct clk_regmap axg_mpeg_clk_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_MPEG_CLK_CNTL,
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.shift = 0,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpeg_clk_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "mpeg_clk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -487,15 +488,16 @@ static struct clk_mux axg_sd_emmc_b_clk0_sel = {
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},
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};
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static struct clk_divider axg_sd_emmc_b_clk0_div = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.lock = &meson_clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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static struct clk_regmap axg_sd_emmc_b_clk0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SD_EMMC_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_b_clk0_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -531,15 +533,16 @@ static struct clk_mux axg_sd_emmc_c_clk0_sel = {
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},
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};
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static struct clk_divider axg_sd_emmc_c_clk0_div = {
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.reg = (void *)HHI_NAND_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &meson_clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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static struct clk_regmap axg_sd_emmc_c_clk0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_NAND_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_c_clk0_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -706,12 +709,6 @@ static struct clk_mux *const axg_clk_muxes[] = {
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&axg_sd_emmc_c_clk0_sel,
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};
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static struct clk_divider *const axg_clk_dividers[] = {
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&axg_mpeg_clk_div,
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&axg_sd_emmc_b_clk0_div,
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&axg_sd_emmc_c_clk0_div,
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};
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static struct clk_regmap *const axg_clk_regmaps[] = {
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&axg_clk81,
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&axg_ddr,
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@ -760,6 +757,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
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&axg_ao_i2c,
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&axg_sd_emmc_b_clk0,
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&axg_sd_emmc_c_clk0,
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&axg_mpeg_clk_div,
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&axg_sd_emmc_b_clk0_div,
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&axg_sd_emmc_c_clk0_div,
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};
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struct clkc_data {
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@ -769,8 +769,6 @@ struct clkc_data {
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unsigned int clk_plls_count;
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struct clk_mux *const *clk_muxes;
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unsigned int clk_muxes_count;
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struct clk_divider *const *clk_dividers;
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unsigned int clk_dividers_count;
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struct clk_hw_onecell_data *hw_onecell_data;
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};
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@ -781,8 +779,6 @@ static const struct clkc_data axg_clkc_data = {
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.clk_plls_count = ARRAY_SIZE(axg_clk_plls),
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.clk_muxes = axg_clk_muxes,
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.clk_muxes_count = ARRAY_SIZE(axg_clk_muxes),
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.clk_dividers = axg_clk_dividers,
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.clk_dividers_count = ARRAY_SIZE(axg_clk_dividers),
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.hw_onecell_data = &axg_hw_onecell_data,
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};
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@ -838,11 +834,6 @@ static int axg_clkc_probe(struct platform_device *pdev)
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clkc_data->clk_muxes[i]->reg = clk_base +
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(u64)clkc_data->clk_muxes[i]->reg;
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/* Populate base address for dividers */
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for (i = 0; i < clkc_data->clk_dividers_count; i++)
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clkc_data->clk_dividers[i]->reg = clk_base +
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(u64)clkc_data->clk_dividers[i]->reg;
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/* Populate regmap for the regmap backed clocks */
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for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
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axg_clk_regmaps[i]->map = map;
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@ -604,14 +604,15 @@ static struct clk_mux gxbb_mpeg_clk_sel = {
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},
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};
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static struct clk_divider gxbb_mpeg_clk_div = {
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.reg = (void *)HHI_MPEG_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &meson_clk_lock,
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static struct clk_regmap gxbb_mpeg_clk_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_MPEG_CLK_CNTL,
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.shift = 0,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "mpeg_clk_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "mpeg_clk_sel" },
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.num_parents = 1,
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
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@ -647,14 +648,15 @@ static struct clk_mux gxbb_sar_adc_clk_sel = {
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},
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};
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static struct clk_divider gxbb_sar_adc_clk_div = {
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.reg = (void *)HHI_SAR_CLK_CNTL,
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.shift = 0,
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.width = 8,
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.lock = &meson_clk_lock,
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static struct clk_regmap gxbb_sar_adc_clk_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SAR_CLK_CNTL,
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.shift = 0,
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.width = 8,
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},
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.hw.init = &(struct clk_init_data){
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.name = "sar_adc_clk_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "sar_adc_clk_sel" },
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.num_parents = 1,
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},
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@ -705,14 +707,15 @@ static struct clk_mux gxbb_mali_0_sel = {
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},
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};
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static struct clk_divider gxbb_mali_0_div = {
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.reg = (void *)HHI_MALI_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &meson_clk_lock,
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static struct clk_regmap gxbb_mali_0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_MALI_CLK_CNTL,
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.shift = 0,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "mali_0_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "mali_0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_NO_REPARENT,
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@ -753,14 +756,15 @@ static struct clk_mux gxbb_mali_1_sel = {
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},
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};
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static struct clk_divider gxbb_mali_1_div = {
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.reg = (void *)HHI_MALI_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.lock = &meson_clk_lock,
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static struct clk_regmap gxbb_mali_1_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_MALI_CLK_CNTL,
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.shift = 16,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "mali_1_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "mali_1_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_NO_REPARENT,
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@ -864,15 +868,16 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = {
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},
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};
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static struct clk_divider gxbb_cts_mclk_i958_div = {
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.reg = (void *)HHI_AUD_CLK_CNTL2,
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.shift = 16,
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.width = 8,
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.lock = &meson_clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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static struct clk_regmap gxbb_cts_mclk_i958_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_AUD_CLK_CNTL2,
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.shift = 16,
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.width = 8,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "cts_mclk_i958_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -911,14 +916,15 @@ static struct clk_mux gxbb_cts_i958 = {
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},
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};
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static struct clk_divider gxbb_32k_clk_div = {
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.reg = (void *)HHI_32K_CLK_CNTL,
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.shift = 0,
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.width = 14,
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.lock = &meson_clk_lock,
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static struct clk_regmap gxbb_32k_clk_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_32K_CLK_CNTL,
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.shift = 0,
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.width = 14,
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},
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.hw.init = &(struct clk_init_data){
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.name = "32k_clk_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "32k_clk_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
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@ -983,15 +989,16 @@ static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
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},
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};
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static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &meson_clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SD_EMMC_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_a_clk0_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1027,15 +1034,16 @@ static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
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},
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};
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static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
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.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.lock = &meson_clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SD_EMMC_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_b_clk0_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1071,15 +1079,16 @@ static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
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},
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};
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static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
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.reg = (void *)HHI_NAND_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &meson_clk_lock,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_NAND_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "sd_emmc_c_clk0_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1126,14 +1135,15 @@ static struct clk_mux gxbb_vpu_0_sel = {
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},
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};
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static struct clk_divider gxbb_vpu_0_div = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &meson_clk_lock,
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static struct clk_regmap gxbb_vpu_0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VPU_CLK_CNTL,
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.shift = 0,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu_0_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vpu_0_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1173,14 +1183,15 @@ static struct clk_mux gxbb_vpu_1_sel = {
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},
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};
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static struct clk_divider gxbb_vpu_1_div = {
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.reg = (void *)HHI_VPU_CLK_CNTL,
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.shift = 16,
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.width = 7,
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.lock = &meson_clk_lock,
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static struct clk_regmap gxbb_vpu_1_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VPU_CLK_CNTL,
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.shift = 16,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vpu_1_div",
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.ops = &clk_divider_ops,
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.ops = &clk_regmap_divider_ops,
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.parent_names = (const char *[]){ "vpu_1_sel" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1245,14 +1256,15 @@ static struct clk_mux gxbb_vapb_0_sel = {
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},
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};
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static struct clk_divider gxbb_vapb_0_div = {
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.reg = (void *)HHI_VAPBCLK_CNTL,
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.shift = 0,
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.width = 7,
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.lock = &meson_clk_lock,
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static struct clk_regmap gxbb_vapb_0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VAPBCLK_CNTL,
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.shift = 0,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vapb_0_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vapb_0_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
@ -1292,14 +1304,15 @@ static struct clk_mux gxbb_vapb_1_sel = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_divider gxbb_vapb_1_div = {
|
||||
.reg = (void *)HHI_VAPBCLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.lock = &meson_clk_lock,
|
||||
static struct clk_regmap gxbb_vapb_1_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VAPBCLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vapb_1_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vapb_1_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
@ -1781,22 +1794,6 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
|
|||
&gxbb_vapb_sel,
|
||||
};
|
||||
|
||||
static struct clk_divider *const gxbb_clk_dividers[] = {
|
||||
&gxbb_mpeg_clk_div,
|
||||
&gxbb_sar_adc_clk_div,
|
||||
&gxbb_mali_0_div,
|
||||
&gxbb_mali_1_div,
|
||||
&gxbb_cts_mclk_i958_div,
|
||||
&gxbb_32k_clk_div,
|
||||
&gxbb_sd_emmc_a_clk0_div,
|
||||
&gxbb_sd_emmc_b_clk0_div,
|
||||
&gxbb_sd_emmc_c_clk0_div,
|
||||
&gxbb_vpu_0_div,
|
||||
&gxbb_vpu_1_div,
|
||||
&gxbb_vapb_0_div,
|
||||
&gxbb_vapb_1_div,
|
||||
};
|
||||
|
||||
static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
|
||||
&gxbb_cts_amclk_div,
|
||||
};
|
||||
|
@ -1898,6 +1895,19 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
|
|||
&gxbb_vapb_0,
|
||||
&gxbb_vapb_1,
|
||||
&gxbb_vapb,
|
||||
&gxbb_mpeg_clk_div,
|
||||
&gxbb_sar_adc_clk_div,
|
||||
&gxbb_mali_0_div,
|
||||
&gxbb_mali_1_div,
|
||||
&gxbb_cts_mclk_i958_div,
|
||||
&gxbb_32k_clk_div,
|
||||
&gxbb_sd_emmc_a_clk0_div,
|
||||
&gxbb_sd_emmc_b_clk0_div,
|
||||
&gxbb_sd_emmc_c_clk0_div,
|
||||
&gxbb_vpu_0_div,
|
||||
&gxbb_vpu_1_div,
|
||||
&gxbb_vapb_0_div,
|
||||
&gxbb_vapb_1_div,
|
||||
};
|
||||
|
||||
struct clkc_data {
|
||||
|
@ -1907,8 +1917,6 @@ struct clkc_data {
|
|||
unsigned int clk_plls_count;
|
||||
struct clk_mux *const *clk_muxes;
|
||||
unsigned int clk_muxes_count;
|
||||
struct clk_divider *const *clk_dividers;
|
||||
unsigned int clk_dividers_count;
|
||||
struct meson_clk_audio_divider *const *clk_audio_dividers;
|
||||
unsigned int clk_audio_dividers_count;
|
||||
struct clk_hw_onecell_data *hw_onecell_data;
|
||||
|
@ -1921,8 +1929,6 @@ static const struct clkc_data gxbb_clkc_data = {
|
|||
.clk_plls_count = ARRAY_SIZE(gxbb_clk_plls),
|
||||
.clk_muxes = gxbb_clk_muxes,
|
||||
.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
|
||||
.clk_dividers = gxbb_clk_dividers,
|
||||
.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
|
||||
.clk_audio_dividers = gxbb_audio_dividers,
|
||||
.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
|
||||
.hw_onecell_data = &gxbb_hw_onecell_data,
|
||||
|
@ -1935,8 +1941,6 @@ static const struct clkc_data gxl_clkc_data = {
|
|||
.clk_plls_count = ARRAY_SIZE(gxl_clk_plls),
|
||||
.clk_muxes = gxbb_clk_muxes,
|
||||
.clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
|
||||
.clk_dividers = gxbb_clk_dividers,
|
||||
.clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
|
||||
.clk_audio_dividers = gxbb_audio_dividers,
|
||||
.clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
|
||||
.hw_onecell_data = &gxl_hw_onecell_data,
|
||||
|
@ -1994,11 +1998,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
|
|||
clkc_data->clk_muxes[i]->reg = clk_base +
|
||||
(u64)clkc_data->clk_muxes[i]->reg;
|
||||
|
||||
/* Populate base address for dividers */
|
||||
for (i = 0; i < clkc_data->clk_dividers_count; i++)
|
||||
clkc_data->clk_dividers[i]->reg = clk_base +
|
||||
(u64)clkc_data->clk_dividers[i]->reg;
|
||||
|
||||
/* Populate base address for the audio dividers */
|
||||
for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
|
||||
clkc_data->clk_audio_dividers[i]->base = clk_base;
|
||||
|
|
|
@ -393,14 +393,15 @@ struct clk_mux meson8b_mpeg_clk_sel = {
|
|||
},
|
||||
};
|
||||
|
||||
struct clk_divider meson8b_mpeg_clk_div = {
|
||||
.reg = (void *)HHI_MPEG_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.lock = &meson_clk_lock,
|
||||
struct clk_regmap meson8b_mpeg_clk_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_MPEG_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpeg_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "mpeg_clk_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
|
||||
|
@ -623,10 +624,6 @@ static struct clk_mux *const meson8b_clk_muxes[] = {
|
|||
&meson8b_mpeg_clk_sel,
|
||||
};
|
||||
|
||||
static struct clk_divider *const meson8b_clk_dividers[] = {
|
||||
&meson8b_mpeg_clk_div,
|
||||
};
|
||||
|
||||
static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
||||
&meson8b_clk81,
|
||||
&meson8b_ddr,
|
||||
|
@ -706,6 +703,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
|||
&meson8b_ao_ahb_sram,
|
||||
&meson8b_ao_ahb_bus,
|
||||
&meson8b_ao_iface,
|
||||
&meson8b_mpeg_clk_div,
|
||||
};
|
||||
|
||||
static const struct meson8b_clk_reset_line {
|
||||
|
@ -844,11 +842,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
|
|||
meson8b_clk_muxes[i]->reg = clk_base +
|
||||
(u32)meson8b_clk_muxes[i]->reg;
|
||||
|
||||
/* Populate base address for dividers */
|
||||
for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++)
|
||||
meson8b_clk_dividers[i]->reg = clk_base +
|
||||
(u32)meson8b_clk_dividers[i]->reg;
|
||||
|
||||
/* Populate regmap for the regmap backed clocks */
|
||||
for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
|
||||
meson8b_clk_regmaps[i]->map = map;
|
||||
|
|
Loading…
Reference in a new issue