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gpio: remove zte zx driver
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
Arnd Bergmann
Bartosz Golaszewski
parent
f61d3f0c69
commit
f0a2c77eb8
4 changed files with 0 additions and 321 deletions
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@ -1,24 +0,0 @@
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ZTE ZX296702 GPIO controller
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Required properties:
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- compatible : "zte,zx296702-gpio"
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters:
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- bit 0 specifies polarity (0 for normal, 1 for inverted)
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- gpio-controller : Marks the device node as a GPIO controller.
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- interrupts : Interrupt mapping for GPIO IRQ.
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- gpio-ranges : Interaction with the PINCTRL subsystem.
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gpio1: gpio@b008040 {
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compatible = "zte,zx296702-gpio";
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reg = <0xb008040 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clock-names = "gpio_pclk";
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clocks = <&lsp0clk ZX296702_GPIO_CLK>;
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};
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@ -741,13 +741,6 @@ config GPIO_ZYNQ
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help
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Say yes here to support Xilinx Zynq GPIO controller.
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config GPIO_ZX
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bool "ZTE ZX GPIO support"
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depends on ARCH_ZX || COMPILE_TEST
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select GPIOLIB_IRQCHIP
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help
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Say yes here to support the GPIO device on ZTE ZX SoCs.
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config GPIO_LOONGSON1
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tristate "Loongson1 GPIO support"
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depends on MACH_LOONGSON32
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@ -181,5 +181,4 @@ obj-$(CONFIG_GPIO_XLP) += gpio-xlp.o
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obj-$(CONFIG_GPIO_XRA1403) += gpio-xra1403.o
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obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
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obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
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obj-$(CONFIG_GPIO_ZX) += gpio-zx.o
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obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
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@ -1,289 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* ZTE ZX296702 GPIO driver
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*
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* Author: Jun Nie <jun.nie@linaro.org>
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*
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* Copyright (C) 2015 Linaro Ltd.
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define ZX_GPIO_DIR 0x00
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#define ZX_GPIO_IVE 0x04
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#define ZX_GPIO_IV 0x08
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#define ZX_GPIO_IEP 0x0C
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#define ZX_GPIO_IEN 0x10
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#define ZX_GPIO_DI 0x14
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#define ZX_GPIO_DO1 0x18
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#define ZX_GPIO_DO0 0x1C
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#define ZX_GPIO_DO 0x20
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#define ZX_GPIO_IM 0x28
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#define ZX_GPIO_IE 0x2C
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#define ZX_GPIO_MIS 0x30
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#define ZX_GPIO_IC 0x34
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#define ZX_GPIO_NR 16
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struct zx_gpio {
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raw_spinlock_t lock;
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void __iomem *base;
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struct gpio_chip gc;
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};
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static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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struct zx_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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u16 gpiodir;
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if (offset >= gc->ngpio)
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return -EINVAL;
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raw_spin_lock_irqsave(&chip->lock, flags);
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gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
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gpiodir &= ~BIT(offset);
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writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
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int value)
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{
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struct zx_gpio *chip = gpiochip_get_data(gc);
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unsigned long flags;
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u16 gpiodir;
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if (offset >= gc->ngpio)
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return -EINVAL;
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raw_spin_lock_irqsave(&chip->lock, flags);
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gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
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gpiodir |= BIT(offset);
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writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
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if (value)
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writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
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else
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writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int zx_get_value(struct gpio_chip *gc, unsigned offset)
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{
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struct zx_gpio *chip = gpiochip_get_data(gc);
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return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
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}
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static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct zx_gpio *chip = gpiochip_get_data(gc);
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if (value)
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writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
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else
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writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
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}
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static int zx_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct zx_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d);
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unsigned long flags;
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u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
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u16 bit = BIT(offset);
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if (offset < 0 || offset >= ZX_GPIO_NR)
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return -EINVAL;
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raw_spin_lock_irqsave(&chip->lock, flags);
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gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
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gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
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gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
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gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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gpiois |= bit;
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if (trigger & IRQ_TYPE_LEVEL_HIGH)
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gpioiev |= bit;
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else
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gpioiev &= ~bit;
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} else
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gpiois &= ~bit;
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if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
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gpioi_epos |= bit;
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gpioi_eneg |= bit;
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} else {
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if (trigger & IRQ_TYPE_EDGE_RISING) {
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gpioi_epos |= bit;
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gpioi_eneg &= ~bit;
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} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
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gpioi_eneg |= bit;
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gpioi_epos &= ~bit;
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}
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}
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writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
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writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
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writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
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writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
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raw_spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static void zx_irq_handler(struct irq_desc *desc)
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{
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unsigned long pending;
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int offset;
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct zx_gpio *chip = gpiochip_get_data(gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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chained_irq_enter(irqchip, desc);
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pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
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writew_relaxed(pending, chip->base + ZX_GPIO_IC);
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if (pending) {
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for_each_set_bit(offset, &pending, ZX_GPIO_NR)
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generic_handle_irq(irq_find_mapping(gc->irq.domain,
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offset));
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}
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chained_irq_exit(irqchip, desc);
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}
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static void zx_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct zx_gpio *chip = gpiochip_get_data(gc);
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u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
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u16 gpioie;
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raw_spin_lock(&chip->lock);
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gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
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writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
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gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
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writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
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raw_spin_unlock(&chip->lock);
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}
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static void zx_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct zx_gpio *chip = gpiochip_get_data(gc);
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u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
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u16 gpioie;
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raw_spin_lock(&chip->lock);
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gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
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writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
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gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
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writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
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raw_spin_unlock(&chip->lock);
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}
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static struct irq_chip zx_irqchip = {
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.name = "zx-gpio",
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.irq_mask = zx_irq_mask,
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.irq_unmask = zx_irq_unmask,
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.irq_set_type = zx_irq_type,
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};
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static int zx_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct zx_gpio *chip;
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struct gpio_irq_chip *girq;
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int irq, id, ret;
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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chip->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(chip->base))
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return PTR_ERR(chip->base);
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id = of_alias_get_id(dev->of_node, "gpio");
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raw_spin_lock_init(&chip->lock);
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chip->gc.request = gpiochip_generic_request;
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chip->gc.free = gpiochip_generic_free;
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chip->gc.direction_input = zx_direction_input;
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chip->gc.direction_output = zx_direction_output;
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chip->gc.get = zx_get_value;
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chip->gc.set = zx_set_value;
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chip->gc.base = ZX_GPIO_NR * id;
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chip->gc.ngpio = ZX_GPIO_NR;
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chip->gc.label = dev_name(dev);
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chip->gc.parent = dev;
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chip->gc.owner = THIS_MODULE;
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/*
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* irq_chip support
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*/
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writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
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writew_relaxed(0, chip->base + ZX_GPIO_IE);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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girq = &chip->gc.irq;
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girq->chip = &zx_irqchip;
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girq->parent_handler = zx_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(&pdev->dev, 1,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = irq;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_simple_irq;
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ret = gpiochip_add_data(&chip->gc, chip);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, chip);
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dev_info(dev, "ZX GPIO chip registered\n");
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return 0;
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}
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static const struct of_device_id zx_gpio_match[] = {
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{
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.compatible = "zte,zx296702-gpio",
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},
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{ },
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};
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static struct platform_driver zx_gpio_driver = {
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.probe = zx_gpio_probe,
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.driver = {
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.name = "zx_gpio",
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.of_match_table = of_match_ptr(zx_gpio_match),
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},
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};
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builtin_platform_driver(zx_gpio_driver)
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