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RDMA/hns: Use new interface to modify QP context 

Fill all QPC fileds with hr_reg_*() instead of roce_set_*(). SQPN is used
for HIP08 ES only, it should be removed.

Link: https://lore.kernel.org/r/1624262443-24528-6-git-send-email-liweihang@huawei.com
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Lang Cheng 2021-06-21 16:00:39 +08:00 committed by Jason Gunthorpe
parent f6fcd28d49
commit f0cb411aad
2 changed files with 432 additions and 864 deletions
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746
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
View File

File diff suppressed because it is too large Load Diff

550
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
View File

@ -589,372 +589,192 @@ struct hns_roce_v2_qp_context {
#define QPC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context, h, l)
#define QPC_TST QPC_FIELD_LOC(2, 0)
#define QPC_SGE_SHIFT QPC_FIELD_LOC(7, 3)
#define QPC_CNP_TIMER QPC_FIELD_LOC(31, 8)
#define QPC_WQE_SGE_BA_L QPC_FIELD_LOC(63, 32)
#define QPC_WQE_SGE_BA_H QPC_FIELD_LOC(92, 64)
#define QPC_SQ_HOP_NUM QPC_FIELD_LOC(94, 93)
#define QPC_CIRE_EN QPC_FIELD_LOC(95, 95)
#define QPC_WQE_SGE_BA_PG_SZ QPC_FIELD_LOC(99, 96)
#define QPC_WQE_SGE_BUF_PG_SZ QPC_FIELD_LOC(103, 100)
#define QPC_PD QPC_FIELD_LOC(127, 104)
#define QPC_RQ_HOP_NUM QPC_FIELD_LOC(129, 128)
#define QPC_SGE_HOP_NUM QPC_FIELD_LOC(131, 130)
#define QPC_RQWS QPC_FIELD_LOC(135, 132)
#define QPC_SQ_SHIFT QPC_FIELD_LOC(139, 136)
#define QPC_RQ_SHIFT QPC_FIELD_LOC(143, 140)
#define QPC_GMV_IDX QPC_FIELD_LOC(159, 144)
#define QPC_HOPLIMIT QPC_FIELD_LOC(167, 160)
#define QPC_TC QPC_FIELD_LOC(175, 168)
#define QPC_VLAN_ID QPC_FIELD_LOC(187, 176)
#define QPC_MTU QPC_FIELD_LOC(191, 188)
#define QPC_FL QPC_FIELD_LOC(211, 192)
#define QPC_SL QPC_FIELD_LOC(215, 212)
#define QPC_CNP_TX_FLAG QPC_FIELD_LOC(216, 216)
#define QPC_CE_FLAG QPC_FIELD_LOC(217, 217)
#define QPC_LBI QPC_FIELD_LOC(218, 218)
#define QPC_AT QPC_FIELD_LOC(223, 219)
#define QPC_DGID QPC_FIELD_LOC(351, 224)
#define QPC_DMAC_L QPC_FIELD_LOC(383, 352)
#define QPC_DMAC_H QPC_FIELD_LOC(399, 384)
#define QPC_UDPSPN QPC_FIELD_LOC(415, 400)
#define QPC_DQPN QPC_FIELD_LOC(439, 416)
#define QPC_SQ_TX_ERR QPC_FIELD_LOC(440, 440)
#define QPC_SQ_RX_ERR QPC_FIELD_LOC(441, 441)
#define QPC_RQ_TX_ERR QPC_FIELD_LOC(442, 442)
#define QPC_RQ_RX_ERR QPC_FIELD_LOC(443, 443)
#define QPC_LP_PKTN_INI QPC_FIELD_LOC(447, 444)
#define QPC_CONG_ALGO_TMPL_ID QPC_FIELD_LOC(455, 448)
#define V2_QPC_BYTE_4_TST_S 0
#define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
#define V2_QPC_BYTE_4_SGE_SHIFT_S 3
#define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
#define V2_QPC_BYTE_4_SQPN_S 8
#define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
#define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
#define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
#define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
#define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
#define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
#define V2_QPC_BYTE_16_PD_S 8
#define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
#define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
#define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
#define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
#define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
#define V2_QPC_BYTE_20_RQWS_S 4
#define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
#define V2_QPC_BYTE_20_SQ_SHIFT_S 8
#define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
#define V2_QPC_BYTE_20_RQ_SHIFT_S 12
#define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
#define V2_QPC_BYTE_20_SGID_IDX_S 16
#define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
#define V2_QPC_BYTE_20_SMAC_IDX_S 24
#define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
#define V2_QPC_BYTE_24_HOP_LIMIT_S 0
#define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
#define V2_QPC_BYTE_24_TC_S 8
#define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
#define V2_QPC_BYTE_24_VLAN_ID_S 16
#define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
#define V2_QPC_BYTE_24_MTU_S 28
#define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
#define V2_QPC_BYTE_28_FL_S 0
#define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
#define V2_QPC_BYTE_28_SL_S 20
#define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
#define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
#define V2_QPC_BYTE_28_CE_FLAG_S 25
#define V2_QPC_BYTE_28_LBI_S 26
#define V2_QPC_BYTE_28_AT_S 27
#define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
#define V2_QPC_BYTE_52_DMAC_S 0
#define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
#define V2_QPC_BYTE_52_UDPSPN_S 16
#define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
#define V2_QPC_BYTE_56_DQPN_S 0
#define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
#define V2_QPC_BYTE_56_SQ_TX_ERR_S 24
#define V2_QPC_BYTE_56_SQ_RX_ERR_S 25
#define V2_QPC_BYTE_56_RQ_TX_ERR_S 26
#define V2_QPC_BYTE_56_RQ_RX_ERR_S 27
#define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
#define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
#define V2_QPC_BYTE_60_SCC_TOKEN_S 8
#define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
#define V2_QPC_BYTE_60_SQ_DB_DOING_S 27
#define V2_QPC_BYTE_60_RQ_DB_DOING_S 28
#define V2_QPC_BYTE_60_QP_ST_S 29
#define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
#define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
#define V2_QPC_BYTE_76_SRQN_S 0
#define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
#define V2_QPC_BYTE_76_SRQ_EN_S 24
#define V2_QPC_BYTE_76_RRE_S 25
#define V2_QPC_BYTE_76_RWE_S 26
#define V2_QPC_BYTE_76_ATE_S 27
#define V2_QPC_BYTE_76_RQIE_S 28
#define V2_QPC_BYTE_76_EXT_ATE_S 29
#define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
#define V2_QPC_BYTE_80_RX_CQN_S 0
#define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
#define V2_QPC_BYTE_80_XRC_QP_TYPE_S 24
#define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
#define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
#define V2_QPC_BYTE_92_SRQ_INFO_S 20
#define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
#define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
#define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
#define V2_QPC_BYTE_108_INV_CREDIT_S 0
#define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
#define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
#define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
#define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
#define V2_QPC_BYTE_132_TRRL_BA_S 16
#define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
#define V2_QPC_BYTE_140_TRRL_BA_S 0
#define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
#define V2_QPC_BYTE_140_RR_MAX_S 12
#define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
#define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
#define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
#define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
#define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
#define V2_QPC_BYTE_148_RQ_MSN_S 0
#define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
#define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
#define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
#define V2_QPC_BYTE_152_RAQ_PSN_S 0
#define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
#define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
#define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
#define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
#define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
#define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
#define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
#define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
#define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
#define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
#define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
#define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
#define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
#define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
#define V2_QPC_BYTE_172_FRE_S 7
#define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
#define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
#define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
#define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
#define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
#define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
#define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
#define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
#define V2_QPC_BYTE_196_IRRL_HEAD_S 0
#define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
#define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
#define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
#define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
#define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
#define V2_QPC_BYTE_208_IRRL_BA_S 0
#define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
#define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
#define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
#define V2_QPC_BYTE_208_RMT_E2E_S 28
#define V2_QPC_BYTE_208_SR_MAX_S 29
#define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
#define V2_QPC_BYTE_212_LSN_S 0
#define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
#define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
#define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
#define V2_QPC_BYTE_212_CHECK_FLG_S 27
#define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
#define V2_QPC_BYTE_212_RETRY_CNT_S 29
#define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
#define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
#define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
#define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
#define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
#define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
#define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
#define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
#define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
#define V2_QPC_BYTE_232_SO_LP_VLD_S 29
#define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
#define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
#define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
#define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
#define V2_QPC_BYTE_240_RX_ACK_MSN_S 16
#define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
#define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
#define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
#define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
#define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
#define V2_QPC_BYTE_244_RNR_CNT_S 27
#define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
#define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
#define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
#define V2_QPC_BYTE_248_IRRL_PSN_S 0
#define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
#define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
#define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
#define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
#define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
#define V2_QPC_BYTE_252_TX_CQN_S 0
#define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
#define V2_QPC_BYTE_252_SIG_TYPE_S 24
#define V2_QPC_BYTE_252_ERR_TYPE_S 25
#define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
#define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
#define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
#define QPC_SCC_TOKEN QPC_FIELD_LOC(474, 456)
#define QPC_SQ_DB_DOING QPC_FIELD_LOC(475, 475)
#define QPC_RQ_DB_DOING QPC_FIELD_LOC(476, 476)
#define QPC_QP_ST QPC_FIELD_LOC(479, 477)
#define QPC_QKEY_XRCD QPC_FIELD_LOC(511, 480)
#define QPC_RQ_RECORD_EN QPC_FIELD_LOC(512, 512)
#define QPC_RQ_DB_RECORD_ADDR_L QPC_FIELD_LOC(543, 513)
#define QPC_RQ_DB_RECORD_ADDR_H QPC_FIELD_LOC(575, 544)
#define QPC_SRQN QPC_FIELD_LOC(599, 576)
#define QPC_SRQ_EN QPC_FIELD_LOC(600, 600)
#define QPC_RRE QPC_FIELD_LOC(601, 601)
#define QPC_RWE QPC_FIELD_LOC(602, 602)
#define QPC_ATE QPC_FIELD_LOC(603, 603)
#define QPC_RQIE QPC_FIELD_LOC(604, 604)
#define QPC_EXT_ATE QPC_FIELD_LOC(605, 605)
#define QPC_RQ_VLAN_EN QPC_FIELD_LOC(606, 606)
#define QPC_RQ_RTY_TX_ERR QPC_FIELD_LOC(607, 607)
#define QPC_RX_CQN QPC_FIELD_LOC(631, 608)
#define QPC_XRC_QP_TYPE QPC_FIELD_LOC(632, 632)
#define QPC_RSV3 QPC_FIELD_LOC(634, 633)
#define QPC_MIN_RNR_TIME QPC_FIELD_LOC(639, 635)
#define QPC_RQ_PRODUCER_IDX QPC_FIELD_LOC(655, 640)
#define QPC_RQ_CONSUMER_IDX QPC_FIELD_LOC(671, 656)
#define QPC_RQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(703, 672)
#define QPC_RQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(723, 704)
#define QPC_SRQ_INFO QPC_FIELD_LOC(735, 724)
#define QPC_RX_REQ_MSN QPC_FIELD_LOC(759, 736)
#define QPC_REDUCE_CODE QPC_FIELD_LOC(766, 760)
#define QPC_RX_XRC_PKT_CQE_FLG QPC_FIELD_LOC(767, 767)
#define QPC_RQ_NXT_BLK_ADDR_L QPC_FIELD_LOC(799, 768)
#define QPC_RQ_NXT_BLK_ADDR_H QPC_FIELD_LOC(819, 800)
#define QPC_REDUCE_EN QPC_FIELD_LOC(820, 820)
#define QPC_FLUSH_EN QPC_FIELD_LOC(821, 821)
#define QPC_AW_EN QPC_FIELD_LOC(822, 822)
#define QPC_WN_EN QPC_FIELD_LOC(823, 823)
#define QPC_RQ_CUR_WQE_SGE_NUM QPC_FIELD_LOC(831, 824)
#define QPC_INV_CREDIT QPC_FIELD_LOC(832, 832)
#define QPC_LAST_WRITE_TYPE QPC_FIELD_LOC(834, 833)
#define QPC_RX_REQ_PSN_ERR QPC_FIELD_LOC(835, 835)
#define QPC_RX_REQ_LAST_OPTYPE QPC_FIELD_LOC(838, 836)
#define QPC_RX_REQ_RNR QPC_FIELD_LOC(839, 839)
#define QPC_RX_REQ_EPSN QPC_FIELD_LOC(863, 840)
#define QPC_RQ_RNR_TIMER QPC_FIELD_LOC(895, 864)
#define QPC_RX_MSG_LEN QPC_FIELD_LOC(927, 896)
#define QPC_RX_RKEY_PKT_INFO QPC_FIELD_LOC(959, 928)
#define QPC_RX_VA QPC_FIELD_LOC(1023, 960)
#define QPC_TRRL_HEAD_MAX QPC_FIELD_LOC(1031, 1024)
#define QPC_TRRL_TAIL_MAX QPC_FIELD_LOC(1039, 1032)
#define QPC_TRRL_BA_L QPC_FIELD_LOC(1055, 1040)
#define QPC_TRRL_BA_M QPC_FIELD_LOC(1087, 1056)
#define QPC_TRRL_BA_H QPC_FIELD_LOC(1099, 1088)
#define QPC_RR_MAX QPC_FIELD_LOC(1102, 1100)
#define QPC_RQ_RTY_WAIT_DO QPC_FIELD_LOC(1103, 1103)
#define QPC_RAQ_TRRL_HEAD QPC_FIELD_LOC(1111, 1104)
#define QPC_RAQ_TRRL_TAIL QPC_FIELD_LOC(1119, 1112)
#define QPC_RAQ_RTY_INI_PSN QPC_FIELD_LOC(1143, 1120)
#define QPC_CIRE_SLV_RQ_EN QPC_FIELD_LOC(1144, 1144)
#define QPC_RAQ_CREDIT QPC_FIELD_LOC(1149, 1145)
#define QPC_RQ_DB_IN_EXT QPC_FIELD_LOC(1150, 1150)
#define QPC_RESP_RTY_FLG QPC_FIELD_LOC(1151, 1151)
#define QPC_RAQ_MSN QPC_FIELD_LOC(1175, 1152)
#define QPC_RAQ_SYNDROME QPC_FIELD_LOC(1183, 1176)
#define QPC_RAQ_PSN QPC_FIELD_LOC(1207, 1184)
#define QPC_RAQ_TRRL_RTY_HEAD QPC_FIELD_LOC(1215, 1208)
#define QPC_RAQ_USE_PKTN QPC_FIELD_LOC(1239, 1216)
#define QPC_RQ_SCC_TOKEN QPC_FIELD_LOC(1245, 1240)
#define QPC_RVD10 QPC_FIELD_LOC(1247, 1246)
#define QPC_SQ_PRODUCER_IDX QPC_FIELD_LOC(1263, 1248)
#define QPC_SQ_CONSUMER_IDX QPC_FIELD_LOC(1279, 1264)
#define QPC_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1311, 1280)
#define QPC_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1331, 1312)
#define QPC_MSG_RTY_LP_FLG QPC_FIELD_LOC(1332, 1332)
#define QPC_SQ_INVLD_FLG QPC_FIELD_LOC(1333, 1333)
#define QPC_LP_SGEN_INI QPC_FIELD_LOC(1335, 1334)
#define QPC_SQ_VLAN_EN QPC_FIELD_LOC(1336, 1336)
#define QPC_POLL_DB_WAIT_DO QPC_FIELD_LOC(1337, 1337)
#define QPC_SCC_TOKEN_FORBID_SQ_DEQ QPC_FIELD_LOC(1338, 1338)
#define QPC_WAIT_ACK_TIMEOUT QPC_FIELD_LOC(1339, 1339)
#define QPC_IRRL_IDX_LSB QPC_FIELD_LOC(1343, 1340)
#define QPC_ACK_REQ_FREQ QPC_FIELD_LOC(1349, 1344)
#define QPC_MSG_RNR_FLG QPC_FIELD_LOC(1350, 1350)
#define QPC_FRE QPC_FIELD_LOC(1351, 1351)
#define QPC_SQ_CUR_PSN QPC_FIELD_LOC(1375, 1352)
#define QPC_MSG_USE_PKTN QPC_FIELD_LOC(1399, 1376)
#define QPC_IRRL_HEAD_PRE QPC_FIELD_LOC(1407, 1400)
#define QPC_SQ_CUR_SGE_BLK_ADDR_L QPC_FIELD_LOC(1439, 1408)
#define QPC_SQ_CUR_SGE_BLK_ADDR_H QPC_FIELD_LOC(1459, 1440)
#define QPC_IRRL_IDX_MSB QPC_FIELD_LOC(1471, 1460)
#define QPC_CUR_SGE_OFFSET QPC_FIELD_LOC(1503, 1472)
#define QPC_CUR_SGE_IDX QPC_FIELD_LOC(1527, 1504)
#define QPC_EXT_SGE_NUM_LEFT QPC_FIELD_LOC(1535, 1528)
#define QPC_OWNER_MODE QPC_FIELD_LOC(1536, 1536)
#define QPC_CIRE_SLV_SQ_EN QPC_FIELD_LOC(1537, 1537)
#define QPC_CIRE_DOING QPC_FIELD_LOC(1538, 1538)
#define QPC_CIRE_RESULT QPC_FIELD_LOC(1539, 1539)
#define QPC_OWNER_DB_WAIT_DO QPC_FIELD_LOC(1540, 1540)
#define QPC_SQ_WQE_INVLD QPC_FIELD_LOC(1541, 1541)
#define QPC_DCA_MODE QPC_FIELD_LOC(1542, 1542)
#define QPC_RTY_OWNER_NOCHK QPC_FIELD_LOC(1543, 1543)
#define QPC_V2_IRRL_HEAD QPC_FIELD_LOC(1543, 1536)
#define QPC_SQ_MAX_PSN QPC_FIELD_LOC(1567, 1544)
#define QPC_SQ_MAX_IDX QPC_FIELD_LOC(1583, 1568)
#define QPC_LCL_OPERATED_CNT QPC_FIELD_LOC(1599, 1584)
#define QPC_IRRL_BA_L QPC_FIELD_LOC(1631, 1600)
#define QPC_IRRL_BA_H QPC_FIELD_LOC(1657, 1632)
#define QPC_PKT_RNR_FLG QPC_FIELD_LOC(1658, 1658)
#define QPC_PKT_RTY_FLG QPC_FIELD_LOC(1659, 1659)
#define QPC_RMT_E2E QPC_FIELD_LOC(1660, 1660)
#define QPC_SR_MAX QPC_FIELD_LOC(1663, 1661)
#define QPC_LSN QPC_FIELD_LOC(1687, 1664)
#define QPC_RETRY_NUM_INIT QPC_FIELD_LOC(1690, 1688)
#define QPC_CHECK_FLG QPC_FIELD_LOC(1692, 1691)
#define QPC_RETRY_CNT QPC_FIELD_LOC(1695, 1693)
#define QPC_SQ_TIMER QPC_FIELD_LOC(1727, 1696)
#define QPC_RETRY_MSG_MSN QPC_FIELD_LOC(1743, 1728)
#define QPC_RETRY_MSG_PSN_L QPC_FIELD_LOC(1759, 1744)
#define QPC_RETRY_MSG_PSN_H QPC_FIELD_LOC(1767, 1760)
#define QPC_RETRY_MSG_FPKT_PSN QPC_FIELD_LOC(1791, 1768)
#define QPC_RX_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1823, 1792)
#define QPC_RX_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1843, 1824)
#define QPC_IRRL_SGE_IDX QPC_FIELD_LOC(1851, 1844)
#define QPC_LSAN_EN QPC_FIELD_LOC(1852, 1852)
#define QPC_SO_LP_VLD QPC_FIELD_LOC(1853, 1853)
#define QPC_FENCE_LP_VLD QPC_FIELD_LOC(1854, 1854)
#define QPC_IRRL_LP_VLD QPC_FIELD_LOC(1855, 1855)
#define QPC_IRRL_CUR_SGE_OFFSET QPC_FIELD_LOC(1887, 1856)
#define QPC_IRRL_TAIL_REAL QPC_FIELD_LOC(1895, 1888)
#define QPC_IRRL_TAIL_RD QPC_FIELD_LOC(1903, 1896)
#define QPC_RX_ACK_MSN QPC_FIELD_LOC(1919, 1904)
#define QPC_RX_ACK_EPSN QPC_FIELD_LOC(1943, 1920)
#define QPC_RNR_NUM_INIT QPC_FIELD_LOC(1946, 1944)
#define QPC_RNR_CNT QPC_FIELD_LOC(1949, 1947)
#define QPC_LCL_OP_FLG QPC_FIELD_LOC(1950, 1950)
#define QPC_IRRL_RD_FLG QPC_FIELD_LOC(1951, 1951)
#define QPC_IRRL_PSN QPC_FIELD_LOC(1975, 1952)
#define QPC_ACK_PSN_ERR QPC_FIELD_LOC(1976, 1976)
#define QPC_ACK_LAST_OPTYPE QPC_FIELD_LOC(1978, 1977)
#define QPC_IRRL_PSN_VLD QPC_FIELD_LOC(1979, 1979)
#define QPC_RNR_RETRY_FLAG QPC_FIELD_LOC(1980, 1980)
#define QPC_SQ_RTY_TX_ERR QPC_FIELD_LOC(1981, 1981)
#define QPC_LAST_IND QPC_FIELD_LOC(1982, 1982)
#define QPC_CQ_ERR_IND QPC_FIELD_LOC(1983, 1983)
#define QPC_TX_CQN QPC_FIELD_LOC(2007, 1984)
#define QPC_SIG_TYPE QPC_FIELD_LOC(2008, 2008)
#define QPC_ERR_TYPE QPC_FIELD_LOC(2015, 2009)
#define QPC_RQ_CQE_IDX QPC_FIELD_LOC(2031, 2016)
#define QPC_SQ_FLUSH_IDX QPC_FIELD_LOC(2047, 2032)
#define RETRY_MSG_PSN_SHIFT 16
#define QPCEX_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context_ex, h, l)