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ARM: 7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes
The linker script assumes a cacheline size of 32 bytes when aligning the .data..cacheline_aligned and .data..percpu sections. This patch updates the script to use L1_CACHE_BYTES, which should be set to 64 on platforms that require it. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1 changed files with 4 additions and 3 deletions
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@ -4,6 +4,7 @@
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*/
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*/
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#include <asm-generic/vmlinux.lds.h>
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#include <asm-generic/vmlinux.lds.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/thread_info.h>
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#include <asm/memory.h>
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#include <asm/memory.h>
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#include <asm/page.h>
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#include <asm/page.h>
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@ -181,7 +182,7 @@ SECTIONS
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}
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}
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#endif
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#endif
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PERCPU_SECTION(32)
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PERCPU_SECTION(L1_CACHE_BYTES)
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#ifdef CONFIG_XIP_KERNEL
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#ifdef CONFIG_XIP_KERNEL
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__data_loc = ALIGN(4); /* location in binary */
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__data_loc = ALIGN(4); /* location in binary */
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@ -212,8 +213,8 @@ SECTIONS
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#endif
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#endif
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NOSAVE_DATA
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NOSAVE_DATA
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CACHELINE_ALIGNED_DATA(32)
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CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
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READ_MOSTLY_DATA(32)
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READ_MOSTLY_DATA(L1_CACHE_BYTES)
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/*
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/*
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* The exception fixup table (might need resorting at runtime)
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* The exception fixup table (might need resorting at runtime)
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