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[ARM] pxa: add clock definition for graphics controller
Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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parent
d2c3706842
commit
f0f04f0840
3 changed files with 6 additions and 2 deletions
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@ -208,7 +208,7 @@
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#define CKEN_MVED 43 /* < MVED clock enable */
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#define CKEN_MVED 43 /* < MVED clock enable */
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/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
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/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
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#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
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#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */
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#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
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#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */
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#endif /* __ASM_ARCH_PXA3XX_REGS_H */
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#endif /* __ASM_ARCH_PXA3XX_REGS_H */
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@ -84,9 +84,11 @@ static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
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};
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};
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static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
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static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
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static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
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static struct clk_lookup common_clkregs[] = {
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static struct clk_lookup common_clkregs[] = {
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INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
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};
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};
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static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
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static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
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@ -78,9 +78,11 @@ static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
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};
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};
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static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
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static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
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static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
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static struct clk_lookup pxa320_clkregs[] = {
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static struct clk_lookup pxa320_clkregs[] = {
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INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
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};
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};
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static int __init pxa320_init(void)
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static int __init pxa320_init(void)
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