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Revert "drm/amd/display: disable SubVP + DRR to prevent underflow"
[ Upstream commitf38129bb08
] This reverts commit80c6d6804f
. The orignal commit was intended as a workaround to prevent underflow and flickering when using one normal monitor and the other high refresh rate monitor (> 120Hz). This patch is being reverted in favour of a software solution to enable SubVP+DRR Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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3 changed files with 0 additions and 10 deletions
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@ -1653,11 +1653,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
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if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
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init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
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init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
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/* Disable SubVP + DRR config by default */
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init_data.flags.disable_subvp_drr = true;
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if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
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init_data.flags.disable_subvp_drr = false;
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init_data.flags.seamless_boot_edp_requested = false;
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init_data.flags.seamless_boot_edp_requested = false;
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if (check_seamless_boot_capability(adev)) {
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if (check_seamless_boot_capability(adev)) {
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@ -880,10 +880,6 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struc
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int16_t stretched_drr_us = 0;
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int16_t stretched_drr_us = 0;
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int16_t drr_stretched_vblank_us = 0;
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int16_t drr_stretched_vblank_us = 0;
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int16_t max_vblank_mallregion = 0;
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int16_t max_vblank_mallregion = 0;
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const struct dc_config *config = &dc->config;
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if (config->disable_subvp_drr)
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return false;
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// Find SubVP pipe
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// Find SubVP pipe
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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@ -240,7 +240,6 @@ enum DC_FEATURE_MASK {
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DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
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DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
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DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
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DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
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DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
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DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
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DC_ENABLE_SUBVP_DRR = (1 << 9), // 0x200, disabled by default
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};
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};
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enum DC_DEBUG_MASK {
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enum DC_DEBUG_MASK {
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