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sparc: Make sparc64 use scalable lib/iommu-common.c functions
In iperf experiments running linux as the Tx side (TCP client) with 10 threads results in a severe performance drop when TSO is disabled, indicating a weakness in the software that can be avoided by using the scalable IOMMU arena DMA allocation. Baseline numbers before this patch: with default settings (TSO enabled) : 9-9.5 Gbps Disable TSO using ethtool- drops badly: 2-3 Gbps. After this patch, iperf client with 10 threads, can give a throughput of at least 8.5 Gbps, even when TSO is disabled. Signed-off-by: Sowmini Varadhan <sowmini.varadhan@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
10b88a4b17
commit
f1600e549b
4 changed files with 159 additions and 235 deletions
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@ -16,6 +16,7 @@
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#define IOPTE_WRITE 0x0000000000000002UL
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#define IOMMU_NUM_CTXS 4096
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#include <linux/iommu-common.h>
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struct iommu_arena {
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unsigned long *map;
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@ -24,11 +25,10 @@ struct iommu_arena {
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};
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struct iommu {
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struct iommu_table tbl;
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spinlock_t lock;
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struct iommu_arena arena;
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void (*flush_all)(struct iommu *);
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u32 dma_addr_mask;
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iopte_t *page_table;
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u32 page_table_map_base;
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unsigned long iommu_control;
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unsigned long iommu_tsbbase;
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unsigned long iommu_flush;
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@ -40,7 +40,6 @@ struct iommu {
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unsigned long dummy_page_pa;
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unsigned long ctx_lowest_free;
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DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
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u32 dma_addr_mask;
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};
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struct strbuf {
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@ -13,11 +13,15 @@
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#include <linux/errno.h>
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#include <linux/iommu-helper.h>
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#include <linux/bitmap.h>
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#include <linux/hash.h>
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#include <linux/iommu-common.h>
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#ifdef CONFIG_PCI
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#include <linux/pci.h>
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#endif
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static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
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#include <asm/iommu.h>
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#include "iommu_common.h"
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@ -45,8 +49,9 @@
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"i" (ASI_PHYS_BYPASS_EC_E))
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/* Must be invoked under the IOMMU lock. */
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static void iommu_flushall(struct iommu *iommu)
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static void iommu_flushall(struct iommu_table *iommu_table)
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{
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struct iommu *iommu = container_of(iommu_table, struct iommu, tbl);
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if (iommu->iommu_flushinv) {
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iommu_write(iommu->iommu_flushinv, ~(u64)0);
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} else {
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@ -87,93 +92,22 @@ static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
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iopte_val(*iopte) = val;
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}
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/* Based almost entirely upon the ppc64 iommu allocator. If you use the 'handle'
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* facility it must all be done in one pass while under the iommu lock.
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*
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* On sun4u platforms, we only flush the IOMMU once every time we've passed
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* over the entire page table doing allocations. Therefore we only ever advance
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* the hint and cannot backtrack it.
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*/
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unsigned long iommu_range_alloc(struct device *dev,
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struct iommu *iommu,
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unsigned long npages,
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unsigned long *handle)
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static struct iommu_tbl_ops iommu_sparc_ops = {
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.reset = iommu_flushall
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};
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static void setup_iommu_pool_hash(void)
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{
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unsigned long n, end, start, limit, boundary_size;
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struct iommu_arena *arena = &iommu->arena;
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int pass = 0;
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unsigned int i;
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static bool do_once;
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/* This allocator was derived from x86_64's bit string search */
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/* Sanity check */
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if (unlikely(npages == 0)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return DMA_ERROR_CODE;
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if (do_once)
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return;
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do_once = true;
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for_each_possible_cpu(i)
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per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
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}
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if (handle && *handle)
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start = *handle;
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else
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start = arena->hint;
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limit = arena->limit;
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/* The case below can happen if we have a small segment appended
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* to a large, or when the previous alloc was at the very end of
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* the available space. If so, go back to the beginning and flush.
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*/
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if (start >= limit) {
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start = 0;
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if (iommu->flush_all)
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iommu->flush_all(iommu);
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}
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again:
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if (dev)
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boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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1 << IO_PAGE_SHIFT);
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else
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boundary_size = ALIGN(1UL << 32, 1 << IO_PAGE_SHIFT);
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n = iommu_area_alloc(arena->map, limit, start, npages,
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iommu->page_table_map_base >> IO_PAGE_SHIFT,
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boundary_size >> IO_PAGE_SHIFT, 0);
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if (n == -1) {
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if (likely(pass < 1)) {
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/* First failure, rescan from the beginning. */
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start = 0;
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if (iommu->flush_all)
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iommu->flush_all(iommu);
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pass++;
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goto again;
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} else {
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/* Second failure, give up */
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return DMA_ERROR_CODE;
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}
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}
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end = n + npages;
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arena->hint = end;
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/* Update handle for SG allocations */
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if (handle)
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*handle = end;
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return n;
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}
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void iommu_range_free(struct iommu *iommu, dma_addr_t dma_addr, unsigned long npages)
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{
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struct iommu_arena *arena = &iommu->arena;
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unsigned long entry;
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entry = (dma_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
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bitmap_clear(arena->map, entry, npages);
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}
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int iommu_table_init(struct iommu *iommu, int tsbsize,
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u32 dma_offset, u32 dma_addr_mask,
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/* Setup initial software IOMMU state. */
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spin_lock_init(&iommu->lock);
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iommu->ctx_lowest_free = 1;
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iommu->page_table_map_base = dma_offset;
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iommu->tbl.page_table_map_base = dma_offset;
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iommu->dma_addr_mask = dma_addr_mask;
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/* Allocate and initialize the free area map. */
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sz = num_tsb_entries / 8;
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sz = (sz + 7UL) & ~7UL;
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iommu->arena.map = kmalloc_node(sz, GFP_KERNEL, numa_node);
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if (!iommu->arena.map) {
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printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n");
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iommu->tbl.map = kmalloc_node(sz, GFP_KERNEL, numa_node);
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if (!iommu->tbl.map)
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return -ENOMEM;
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}
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memset(iommu->arena.map, 0, sz);
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iommu->arena.limit = num_tsb_entries;
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memset(iommu->tbl.map, 0, sz);
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if (tlb_type != hypervisor)
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iommu->flush_all = iommu_flushall;
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iommu_sparc_ops.reset = NULL; /* not needed on on sun4v */
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setup_iommu_pool_hash();
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iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
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&iommu_sparc_ops, false, 1);
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/* Allocate and initialize the dummy page which we
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* set inactive IO PTEs to point to.
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iommu->dummy_page = 0UL;
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out_free_map:
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kfree(iommu->arena.map);
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iommu->arena.map = NULL;
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kfree(iommu->tbl.map);
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iommu->tbl.map = NULL;
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return -ENOMEM;
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}
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static inline iopte_t *alloc_npages(struct device *dev, struct iommu *iommu,
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static inline iopte_t *alloc_npages(struct device *dev,
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struct iommu *iommu,
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unsigned long npages)
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{
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unsigned long entry;
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entry = iommu_range_alloc(dev, iommu, npages, NULL);
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
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__this_cpu_read(iommu_pool_hash));
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if (unlikely(entry == DMA_ERROR_CODE))
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return NULL;
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@ -284,7 +220,7 @@ static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addrp, gfp_t gfp,
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struct dma_attrs *attrs)
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{
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unsigned long flags, order, first_page;
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unsigned long order, first_page;
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struct iommu *iommu;
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struct page *page;
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int npages, nid;
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@ -306,16 +242,14 @@ static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
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iommu = dev->archdata.iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(iopte == NULL)) {
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free_pages(first_page, order);
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return NULL;
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}
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*dma_addrp = (iommu->page_table_map_base +
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*dma_addrp = (iommu->tbl.page_table_map_base +
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((iopte - iommu->page_table) << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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npages = size >> IO_PAGE_SHIFT;
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struct dma_attrs *attrs)
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{
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struct iommu *iommu;
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unsigned long flags, order, npages;
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unsigned long order, npages;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = dev->archdata.iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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iommu_range_free(iommu, dvma, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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iommu_tbl_range_free(&iommu->tbl, dvma, npages, false, NULL);
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order = get_order(size);
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if (order < 10)
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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base = alloc_npages(dev, iommu, npages);
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spin_lock_irqsave(&iommu->lock, flags);
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu_alloc_ctx(iommu);
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if (unlikely(!base))
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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bus_addr = (iommu->tbl.page_table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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@ -496,7 +426,7 @@ static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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base = iommu->page_table +
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((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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((bus_addr - iommu->tbl.page_table_map_base) >> IO_PAGE_SHIFT);
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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@ -515,11 +445,11 @@ static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
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for (i = 0; i < npages; i++)
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iopte_make_dummy(iommu, base + i);
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iommu_range_free(iommu, bus_addr, npages);
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iommu_free_ctx(iommu, ctx);
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spin_unlock_irqrestore(&iommu->lock, flags);
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages,
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false, NULL);
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}
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static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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@ -567,7 +497,7 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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max_seg_size = dma_get_max_seg_size(dev);
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seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
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base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
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base_shift = iommu->tbl.page_table_map_base >> IO_PAGE_SHIFT;
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for_each_sg(sglist, s, nelems, i) {
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unsigned long paddr, npages, entry, out_entry = 0, slen;
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iopte_t *base;
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@ -581,7 +511,8 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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/* Allocate iommu entries for that segment */
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paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
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npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
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entry = iommu_range_alloc(dev, iommu, npages, &handle);
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, &handle,
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__this_cpu_read(iommu_pool_hash));
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/* Handle failure */
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if (unlikely(entry == DMA_ERROR_CODE)) {
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@ -594,7 +525,7 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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base = iommu->page_table + entry;
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/* Convert entry to a dma_addr_t */
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dma_addr = iommu->page_table_map_base +
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dma_addr = iommu->tbl.page_table_map_base +
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(entry << IO_PAGE_SHIFT);
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dma_addr |= (s->offset & ~IO_PAGE_MASK);
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@ -654,15 +585,17 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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vaddr = s->dma_address & IO_PAGE_MASK;
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npages = iommu_num_pages(s->dma_address, s->dma_length,
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IO_PAGE_SIZE);
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iommu_range_free(iommu, vaddr, npages);
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entry = (vaddr - iommu->page_table_map_base)
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entry = (vaddr - iommu->tbl.page_table_map_base)
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>> IO_PAGE_SHIFT;
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base = iommu->page_table + entry;
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for (j = 0; j < npages; j++)
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iopte_make_dummy(iommu, base + j);
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iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
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false, NULL);
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s->dma_address = DMA_ERROR_CODE;
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s->dma_length = 0;
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}
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@ -677,17 +610,19 @@ static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
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/* If contexts are being used, they are the same in all of the mappings
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* we make for a particular SG.
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*/
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static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
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static unsigned long fetch_sg_ctx(struct iommu *iommu,
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struct scatterlist *sg)
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{
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unsigned long ctx = 0;
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if (iommu->iommu_ctxflush) {
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iopte_t *base;
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u32 bus_addr;
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struct iommu_table *tbl = &iommu->tbl;
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bus_addr = sg->dma_address & IO_PAGE_MASK;
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base = iommu->page_table +
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((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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((bus_addr - tbl->page_table_map_base) >> IO_PAGE_SHIFT);
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ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
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}
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@ -723,9 +658,8 @@ static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
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if (!len)
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break;
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npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
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iommu_range_free(iommu, dma_handle, npages);
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entry = ((dma_handle - iommu->page_table_map_base)
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entry = ((dma_handle - iommu->tbl.page_table_map_base)
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>> IO_PAGE_SHIFT);
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base = iommu->page_table + entry;
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@ -737,6 +671,8 @@ static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
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for (i = 0; i < npages; i++)
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iopte_make_dummy(iommu, base + i);
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iommu_tbl_range_free(&iommu->tbl, dma_handle, npages, false,
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NULL);
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sg = sg_next(sg);
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}
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@ -770,9 +706,10 @@ static void dma_4u_sync_single_for_cpu(struct device *dev,
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if (iommu->iommu_ctxflush &&
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strbuf->strbuf_ctxflush) {
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iopte_t *iopte;
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struct iommu_table *tbl = &iommu->tbl;
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iopte = iommu->page_table +
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((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
|
||||
((bus_addr - tbl->page_table_map_base)>>IO_PAGE_SHIFT);
|
||||
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
||||
}
|
||||
|
||||
|
@ -805,9 +742,10 @@ static void dma_4u_sync_sg_for_cpu(struct device *dev,
|
|||
if (iommu->iommu_ctxflush &&
|
||||
strbuf->strbuf_ctxflush) {
|
||||
iopte_t *iopte;
|
||||
struct iommu_table *tbl = &iommu->tbl;
|
||||
|
||||
iopte = iommu->page_table +
|
||||
((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
||||
iopte = iommu->page_table + ((sglist[0].dma_address -
|
||||
tbl->page_table_map_base) >> IO_PAGE_SHIFT);
|
||||
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
||||
}
|
||||
|
||||
|
|
|
@ -48,12 +48,4 @@ static inline int is_span_boundary(unsigned long entry,
|
|||
return iommu_is_span_boundary(entry, nr, shift, boundary_size);
|
||||
}
|
||||
|
||||
unsigned long iommu_range_alloc(struct device *dev,
|
||||
struct iommu *iommu,
|
||||
unsigned long npages,
|
||||
unsigned long *handle);
|
||||
void iommu_range_free(struct iommu *iommu,
|
||||
dma_addr_t dma_addr,
|
||||
unsigned long npages);
|
||||
|
||||
#endif /* _IOMMU_COMMON_H */
|
||||
|
|
|
@ -15,6 +15,8 @@
|
|||
#include <linux/export.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/hash.h>
|
||||
#include <linux/iommu-common.h>
|
||||
|
||||
#include <asm/iommu.h>
|
||||
#include <asm/irq.h>
|
||||
|
@ -28,6 +30,7 @@
|
|||
|
||||
#define DRIVER_NAME "pci_sun4v"
|
||||
#define PFX DRIVER_NAME ": "
|
||||
static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
|
||||
|
||||
static unsigned long vpci_major = 1;
|
||||
static unsigned long vpci_minor = 1;
|
||||
|
@ -155,14 +158,13 @@ static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
|
|||
|
||||
iommu = dev->archdata.iommu;
|
||||
|
||||
spin_lock_irqsave(&iommu->lock, flags);
|
||||
entry = iommu_range_alloc(dev, iommu, npages, NULL);
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
|
||||
__this_cpu_read(iommu_pool_hash));
|
||||
|
||||
if (unlikely(entry == DMA_ERROR_CODE))
|
||||
goto range_alloc_fail;
|
||||
|
||||
*dma_addrp = (iommu->page_table_map_base +
|
||||
*dma_addrp = (iommu->tbl.page_table_map_base +
|
||||
(entry << IO_PAGE_SHIFT));
|
||||
ret = (void *) first_page;
|
||||
first_page = __pa(first_page);
|
||||
|
@ -188,45 +190,46 @@ static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
|
|||
return ret;
|
||||
|
||||
iommu_map_fail:
|
||||
/* Interrupts are disabled. */
|
||||
spin_lock(&iommu->lock);
|
||||
iommu_range_free(iommu, *dma_addrp, npages);
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
iommu_tbl_range_free(&iommu->tbl, *dma_addrp, npages, false, NULL);
|
||||
|
||||
range_alloc_fail:
|
||||
free_pages(first_page, order);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void dma_4v_iommu_demap(void *demap_arg, unsigned long entry,
|
||||
unsigned long npages)
|
||||
{
|
||||
u32 devhandle = *(u32 *)demap_arg;
|
||||
unsigned long num, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
do {
|
||||
num = pci_sun4v_iommu_demap(devhandle,
|
||||
HV_PCI_TSBID(0, entry),
|
||||
npages);
|
||||
|
||||
entry += num;
|
||||
npages -= num;
|
||||
} while (npages != 0);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
|
||||
dma_addr_t dvma, struct dma_attrs *attrs)
|
||||
{
|
||||
struct pci_pbm_info *pbm;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags, order, npages, entry;
|
||||
unsigned long order, npages, entry;
|
||||
u32 devhandle;
|
||||
|
||||
npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
|
||||
iommu = dev->archdata.iommu;
|
||||
pbm = dev->archdata.host_controller;
|
||||
devhandle = pbm->devhandle;
|
||||
entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
||||
|
||||
spin_lock_irqsave(&iommu->lock, flags);
|
||||
|
||||
iommu_range_free(iommu, dvma, npages);
|
||||
|
||||
do {
|
||||
unsigned long num;
|
||||
|
||||
num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
|
||||
npages);
|
||||
entry += num;
|
||||
npages -= num;
|
||||
} while (npages != 0);
|
||||
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
|
||||
entry = ((dvma - iommu->tbl.page_table_map_base) >> IO_PAGE_SHIFT);
|
||||
dma_4v_iommu_demap(&devhandle, entry, npages);
|
||||
iommu_tbl_range_free(&iommu->tbl, dvma, npages, false, NULL);
|
||||
order = get_order(size);
|
||||
if (order < 10)
|
||||
free_pages((unsigned long)cpu, order);
|
||||
|
@ -253,14 +256,13 @@ static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
|
|||
npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
|
||||
npages >>= IO_PAGE_SHIFT;
|
||||
|
||||
spin_lock_irqsave(&iommu->lock, flags);
|
||||
entry = iommu_range_alloc(dev, iommu, npages, NULL);
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
|
||||
__this_cpu_read(iommu_pool_hash));
|
||||
|
||||
if (unlikely(entry == DMA_ERROR_CODE))
|
||||
goto bad;
|
||||
|
||||
bus_addr = (iommu->page_table_map_base +
|
||||
bus_addr = (iommu->tbl.page_table_map_base +
|
||||
(entry << IO_PAGE_SHIFT));
|
||||
ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
|
||||
base_paddr = __pa(oaddr & IO_PAGE_MASK);
|
||||
|
@ -290,11 +292,7 @@ static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
|
|||
return DMA_ERROR_CODE;
|
||||
|
||||
iommu_map_fail:
|
||||
/* Interrupts are disabled. */
|
||||
spin_lock(&iommu->lock);
|
||||
iommu_range_free(iommu, bus_addr, npages);
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
|
||||
iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, false, NULL);
|
||||
return DMA_ERROR_CODE;
|
||||
}
|
||||
|
||||
|
@ -304,7 +302,7 @@ static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
|
|||
{
|
||||
struct pci_pbm_info *pbm;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags, npages;
|
||||
unsigned long npages;
|
||||
long entry;
|
||||
u32 devhandle;
|
||||
|
||||
|
@ -321,22 +319,9 @@ static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
|
|||
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
||||
npages >>= IO_PAGE_SHIFT;
|
||||
bus_addr &= IO_PAGE_MASK;
|
||||
|
||||
spin_lock_irqsave(&iommu->lock, flags);
|
||||
|
||||
iommu_range_free(iommu, bus_addr, npages);
|
||||
|
||||
entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
|
||||
do {
|
||||
unsigned long num;
|
||||
|
||||
num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
|
||||
npages);
|
||||
entry += num;
|
||||
npages -= num;
|
||||
} while (npages != 0);
|
||||
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
entry = (bus_addr - iommu->tbl.page_table_map_base) >> IO_PAGE_SHIFT;
|
||||
dma_4v_iommu_demap(&devhandle, entry, npages);
|
||||
iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, false, NULL);
|
||||
}
|
||||
|
||||
static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
||||
|
@ -371,14 +356,14 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
/* Init first segment length for backout at failure */
|
||||
outs->dma_length = 0;
|
||||
|
||||
spin_lock_irqsave(&iommu->lock, flags);
|
||||
local_irq_save(flags);
|
||||
|
||||
iommu_batch_start(dev, prot, ~0UL);
|
||||
|
||||
max_seg_size = dma_get_max_seg_size(dev);
|
||||
seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
|
||||
IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
|
||||
base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
|
||||
base_shift = iommu->tbl.page_table_map_base >> IO_PAGE_SHIFT;
|
||||
for_each_sg(sglist, s, nelems, i) {
|
||||
unsigned long paddr, npages, entry, out_entry = 0, slen;
|
||||
|
||||
|
@ -391,7 +376,8 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
/* Allocate iommu entries for that segment */
|
||||
paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
|
||||
npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
|
||||
entry = iommu_range_alloc(dev, iommu, npages, &handle);
|
||||
entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, &handle,
|
||||
__this_cpu_read(iommu_pool_hash));
|
||||
|
||||
/* Handle failure */
|
||||
if (unlikely(entry == DMA_ERROR_CODE)) {
|
||||
|
@ -404,7 +390,7 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
iommu_batch_new_entry(entry);
|
||||
|
||||
/* Convert entry to a dma_addr_t */
|
||||
dma_addr = iommu->page_table_map_base +
|
||||
dma_addr = iommu->tbl.page_table_map_base +
|
||||
(entry << IO_PAGE_SHIFT);
|
||||
dma_addr |= (s->offset & ~IO_PAGE_MASK);
|
||||
|
||||
|
@ -451,7 +437,7 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
if (unlikely(err < 0L))
|
||||
goto iommu_map_failed;
|
||||
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
local_irq_restore(flags);
|
||||
|
||||
if (outcount < incount) {
|
||||
outs = sg_next(outs);
|
||||
|
@ -469,7 +455,8 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
vaddr = s->dma_address & IO_PAGE_MASK;
|
||||
npages = iommu_num_pages(s->dma_address, s->dma_length,
|
||||
IO_PAGE_SIZE);
|
||||
iommu_range_free(iommu, vaddr, npages);
|
||||
iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
|
||||
false, NULL);
|
||||
/* XXX demap? XXX */
|
||||
s->dma_address = DMA_ERROR_CODE;
|
||||
s->dma_length = 0;
|
||||
|
@ -477,7 +464,7 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
if (s == outs)
|
||||
break;
|
||||
}
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
local_irq_restore(flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -489,7 +476,7 @@ static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|||
struct pci_pbm_info *pbm;
|
||||
struct scatterlist *sg;
|
||||
struct iommu *iommu;
|
||||
unsigned long flags;
|
||||
unsigned long flags, entry;
|
||||
u32 devhandle;
|
||||
|
||||
BUG_ON(direction == DMA_NONE);
|
||||
|
@ -498,33 +485,27 @@ static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|||
pbm = dev->archdata.host_controller;
|
||||
devhandle = pbm->devhandle;
|
||||
|
||||
spin_lock_irqsave(&iommu->lock, flags);
|
||||
local_irq_save(flags);
|
||||
|
||||
sg = sglist;
|
||||
while (nelems--) {
|
||||
dma_addr_t dma_handle = sg->dma_address;
|
||||
unsigned int len = sg->dma_length;
|
||||
unsigned long npages, entry;
|
||||
unsigned long npages;
|
||||
struct iommu_table *tbl = &iommu->tbl;
|
||||
unsigned long shift = IO_PAGE_SHIFT;
|
||||
|
||||
if (!len)
|
||||
break;
|
||||
npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
|
||||
iommu_range_free(iommu, dma_handle, npages);
|
||||
|
||||
entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
||||
while (npages) {
|
||||
unsigned long num;
|
||||
|
||||
num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
|
||||
npages);
|
||||
entry += num;
|
||||
npages -= num;
|
||||
}
|
||||
|
||||
entry = ((dma_handle - tbl->page_table_map_base) >> shift);
|
||||
dma_4v_iommu_demap(&devhandle, entry, npages);
|
||||
iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
|
||||
false, NULL);
|
||||
sg = sg_next(sg);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&iommu->lock, flags);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static struct dma_map_ops sun4v_dma_ops = {
|
||||
|
@ -536,6 +517,8 @@ static struct dma_map_ops sun4v_dma_ops = {
|
|||
.unmap_sg = dma_4v_unmap_sg,
|
||||
};
|
||||
|
||||
static struct iommu_tbl_ops dma_4v_iommu_ops;
|
||||
|
||||
static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
|
||||
{
|
||||
struct property *prop;
|
||||
|
@ -550,14 +533,16 @@ static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
|
|||
}
|
||||
|
||||
static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
|
||||
struct iommu *iommu)
|
||||
struct iommu_table *iommu)
|
||||
{
|
||||
struct iommu_arena *arena = &iommu->arena;
|
||||
unsigned long i, cnt = 0;
|
||||
struct iommu_pool *pool;
|
||||
unsigned long i, pool_nr, cnt = 0;
|
||||
u32 devhandle;
|
||||
|
||||
devhandle = pbm->devhandle;
|
||||
for (i = 0; i < arena->limit; i++) {
|
||||
for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
|
||||
pool = &(iommu->arena_pool[pool_nr]);
|
||||
for (i = pool->start; i <= pool->end; i++) {
|
||||
unsigned long ret, io_attrs, ra;
|
||||
|
||||
ret = pci_sun4v_iommu_getmap(devhandle,
|
||||
|
@ -566,14 +551,15 @@ static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
|
|||
if (ret == HV_EOK) {
|
||||
if (page_in_phys_avail(ra)) {
|
||||
pci_sun4v_iommu_demap(devhandle,
|
||||
HV_PCI_TSBID(0, i), 1);
|
||||
HV_PCI_TSBID(0,
|
||||
i), 1);
|
||||
} else {
|
||||
cnt++;
|
||||
__set_bit(i, arena->map);
|
||||
__set_bit(i, iommu->map);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return cnt;
|
||||
}
|
||||
|
||||
|
@ -601,22 +587,22 @@ static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
|
|||
dma_offset = vdma[0];
|
||||
|
||||
/* Setup initial software IOMMU state. */
|
||||
spin_lock_init(&iommu->lock);
|
||||
iommu->ctx_lowest_free = 1;
|
||||
iommu->page_table_map_base = dma_offset;
|
||||
iommu->tbl.page_table_map_base = dma_offset;
|
||||
iommu->dma_addr_mask = dma_mask;
|
||||
|
||||
/* Allocate and initialize the free area map. */
|
||||
sz = (num_tsb_entries + 7) / 8;
|
||||
sz = (sz + 7UL) & ~7UL;
|
||||
iommu->arena.map = kzalloc(sz, GFP_KERNEL);
|
||||
if (!iommu->arena.map) {
|
||||
iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
|
||||
if (!iommu->tbl.map) {
|
||||
printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
iommu->arena.limit = num_tsb_entries;
|
||||
|
||||
sz = probe_existing_entries(pbm, iommu);
|
||||
iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
|
||||
&dma_4v_iommu_ops, false /* no large_pool */,
|
||||
0 /* default npools */);
|
||||
sz = probe_existing_entries(pbm, &iommu->tbl);
|
||||
if (sz)
|
||||
printk("%s: Imported %lu TSB entries from OBP\n",
|
||||
pbm->name, sz);
|
||||
|
@ -1015,8 +1001,17 @@ static struct platform_driver pci_sun4v_driver = {
|
|||
.probe = pci_sun4v_probe,
|
||||
};
|
||||
|
||||
static void setup_iommu_pool_hash(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for_each_possible_cpu(i)
|
||||
per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
|
||||
}
|
||||
|
||||
static int __init pci_sun4v_init(void)
|
||||
{
|
||||
setup_iommu_pool_hash();
|
||||
return platform_driver_register(&pci_sun4v_driver);
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue