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drm/i915/dp: Add a standalone function to obtain shared dpll for HSW/BDW/SKL/BXT
Add the PLL selection code for HSW/BDW/BXT/SKL into a stand-alone function in order to allow for the implementation of a platform neutral upfront link training function. v4: * Removed dereferencing NULL pointer in case of failure (Dhinakaran Pandiyan) v3: * Add Hooks for all DDI platforms into this standalone function v2: * Change the macro to use dev_priv instead of dev (David Weinehall) Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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4 changed files with 81 additions and 1 deletions
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@ -2393,6 +2393,45 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
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return connector;
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}
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struct intel_shared_dpll *
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intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
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{
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struct intel_connector *connector = intel_dp->attached_connector;
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struct intel_encoder *encoder = connector->encoder;
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct intel_shared_dpll *pll = NULL;
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struct intel_shared_dpll_config tmp_pll_config;
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enum intel_dpll_id dpll_id;
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if (IS_BROXTON(dev_priv)) {
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dpll_id = (enum intel_dpll_id)dig_port->port;
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/*
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* Select the required PLL. This works for platforms where
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* there is no shared DPLL.
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*/
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pll = &dev_priv->shared_dplls[dpll_id];
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if (WARN_ON(pll->active_mask)) {
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DRM_ERROR("Shared DPLL in use. active_mask:%x\n",
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pll->active_mask);
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return NULL;
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}
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tmp_pll_config = pll->config;
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if (!bxt_ddi_dp_set_dpll_hw_state(clock,
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&pll->config.hw_state)) {
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DRM_ERROR("Could not setup DPLL\n");
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pll->config = tmp_pll_config;
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return NULL;
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}
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} else if (IS_SKYLAKE(dev_priv)) {
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pll = skl_find_link_pll(dev_priv, clock);
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} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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pll = hsw_ddi_dp_get_dpll(encoder, clock);
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}
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return pll;
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}
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void intel_ddi_init(struct drm_device *dev, enum port port)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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@ -23,6 +23,44 @@
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#include "intel_drv.h"
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struct intel_shared_dpll *
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skl_find_link_pll(struct drm_i915_private *dev_priv, int clock)
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{
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struct intel_shared_dpll *pll = NULL;
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struct intel_dpll_hw_state dpll_hw_state;
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enum intel_dpll_id i;
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bool found = false;
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if (!skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
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return pll;
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for (i = DPLL_ID_SKL_DPLL1; i <= DPLL_ID_SKL_DPLL3; i++) {
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pll = &dev_priv->shared_dplls[i];
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/* Only want to check enabled timings first */
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if (pll->config.crtc_mask == 0)
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continue;
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if (memcmp(&dpll_hw_state, &pll->config.hw_state,
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sizeof(pll->config.hw_state)) == 0) {
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found = true;
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break;
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}
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}
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/* Ok no matching timings, maybe there's a free one? */
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for (i = DPLL_ID_SKL_DPLL1;
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((found == false) && (i <= DPLL_ID_SKL_DPLL3)); i++) {
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pll = &dev_priv->shared_dplls[i];
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if (pll->config.crtc_mask == 0) {
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pll->config.hw_state = dpll_hw_state;
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break;
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}
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}
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return pll;
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}
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struct intel_shared_dpll *
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intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
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enum intel_dpll_id id)
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@ -168,6 +168,8 @@ bool bxt_ddi_dp_set_dpll_hw_state(int clock,
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/* SKL dpll related functions */
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bool skl_ddi_dp_set_dpll_hw_state(int clock,
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struct intel_dpll_hw_state *dpll_hw_state);
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struct intel_shared_dpll *skl_find_link_pll(struct drm_i915_private *dev_priv,
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int clock);
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/* HSW dpll related functions */
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@ -1159,7 +1159,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config);
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void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
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uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
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struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
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int clock);
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unsigned int intel_fb_align_height(struct drm_device *dev,
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unsigned int height,
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uint32_t pixel_format,
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