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mtd: spi-nor: always use bounce buffer for register read/writes
spi-mem layer expects all buffers passed to it to be DMA'able. But spi-nor layer mostly allocates buffers on stack for reading/writing to registers and therefore are not DMA'able. Introduce bounce buffer to be used to read/write to registers. This ensures that buffer passed to spi-mem layer during register read/writes is DMA'able. With this change nor->cmd-buf is no longer used, so drop it. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This commit is contained in:
parent
5f9e832c13
commit
f173f26a4d
2 changed files with 49 additions and 38 deletions
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@ -296,15 +296,14 @@ struct flash_info {
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static int read_sr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
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ret = nor->read_reg(nor, SPINOR_OP_RDSR, nor->bouncebuf, 1);
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if (ret < 0) {
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pr_err("error %d reading SR\n", (int) ret);
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return ret;
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}
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return val;
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return nor->bouncebuf[0];
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}
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/*
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@ -315,15 +314,14 @@ static int read_sr(struct spi_nor *nor)
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static int read_fsr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
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ret = nor->read_reg(nor, SPINOR_OP_RDFSR, nor->bouncebuf, 1);
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if (ret < 0) {
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pr_err("error %d reading FSR\n", ret);
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return ret;
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}
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return val;
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return nor->bouncebuf[0];
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}
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/*
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@ -334,15 +332,14 @@ static int read_fsr(struct spi_nor *nor)
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static int read_cr(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
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ret = nor->read_reg(nor, SPINOR_OP_RDCR, nor->bouncebuf, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading CR\n", ret);
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return ret;
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}
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return val;
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return nor->bouncebuf[0];
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}
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/*
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@ -351,8 +348,8 @@ static int read_cr(struct spi_nor *nor)
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*/
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static int write_sr(struct spi_nor *nor, u8 val)
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{
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nor->cmd_buf[0] = val;
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return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
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nor->bouncebuf[0] = val;
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return nor->write_reg(nor, SPINOR_OP_WRSR, nor->bouncebuf, 1);
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}
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/*
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@ -500,31 +497,31 @@ static int set_4byte(struct spi_nor *nor, bool enable)
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* We must clear the register to enable normal behavior.
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*/
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write_enable(nor);
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nor->cmd_buf[0] = 0;
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nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
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nor->bouncebuf[0] = 0;
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nor->write_reg(nor, SPINOR_OP_WREAR,
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nor->bouncebuf, 1);
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write_disable(nor);
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}
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return status;
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default:
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/* Spansion style */
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nor->cmd_buf[0] = enable << 7;
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return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
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nor->bouncebuf[0] = enable << 7;
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return nor->write_reg(nor, SPINOR_OP_BRWR, nor->bouncebuf, 1);
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}
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}
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static int s3an_sr_ready(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
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ret = nor->read_reg(nor, SPINOR_OP_XRDSR, nor->bouncebuf, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
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return ret;
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}
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return !!(val & XSR_RDY);
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return !!(nor->bouncebuf[0] & XSR_RDY);
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}
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static int spi_nor_sr_ready(struct spi_nor *nor)
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@ -683,7 +680,6 @@ static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr)
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*/
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static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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{
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u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
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int i;
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if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
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@ -697,11 +693,12 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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* control
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*/
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for (i = nor->addr_width - 1; i >= 0; i--) {
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buf[i] = addr & 0xff;
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nor->bouncebuf[i] = addr & 0xff;
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addr >>= 8;
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}
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return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
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return nor->write_reg(nor, nor->erase_opcode, nor->bouncebuf,
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nor->addr_width);
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}
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/**
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@ -1485,9 +1482,11 @@ static int macronix_quad_enable(struct spi_nor *nor)
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*/
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static int spansion_quad_enable(struct spi_nor *nor)
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{
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u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
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u8 *sr_cr = nor->bouncebuf;
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int ret;
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sr_cr[0] = 0;
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sr_cr[1] = CR_QUAD_EN_SPAN;
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ret = write_sr_cr(nor, sr_cr);
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if (ret)
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return ret;
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@ -1517,7 +1516,7 @@ static int spansion_quad_enable(struct spi_nor *nor)
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*/
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static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
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{
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u8 sr_cr[2];
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u8 *sr_cr = nor->bouncebuf;
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int ret;
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/* Keep the current value of the Status Register. */
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@ -1548,7 +1547,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
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static int spansion_read_cr_quad_enable(struct spi_nor *nor)
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{
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struct device *dev = nor->dev;
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u8 sr_cr[2];
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u8 *sr_cr = nor->bouncebuf;
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int ret;
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/* Check current Quad Enable bit value. */
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@ -1599,22 +1598,22 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
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*/
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static int sr2_bit7_quad_enable(struct spi_nor *nor)
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{
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u8 sr2;
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u8 *sr2 = nor->bouncebuf;
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int ret;
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/* Check current Quad Enable bit value. */
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ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
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ret = nor->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
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if (ret)
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return ret;
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if (sr2 & SR2_QUAD_EN_BIT7)
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if (*sr2 & SR2_QUAD_EN_BIT7)
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return 0;
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/* Update the Quad Enable bit. */
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sr2 |= SR2_QUAD_EN_BIT7;
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*sr2 |= SR2_QUAD_EN_BIT7;
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write_enable(nor);
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ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
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ret = nor->write_reg(nor, SPINOR_OP_WRSR2, sr2, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error while writing status register 2\n");
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return -EINVAL;
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@ -1627,8 +1626,8 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
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}
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/* Read back and check it. */
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ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
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if (!(ret > 0 && (sr2 & SR2_QUAD_EN_BIT7))) {
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ret = nor->read_reg(nor, SPINOR_OP_RDSR2, sr2, 1);
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if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) {
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dev_err(nor->dev, "SR2 Quad bit not set\n");
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return -EINVAL;
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}
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@ -1687,7 +1686,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
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{
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int ret;
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u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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u8 sr_cr[2] = {0};
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u8 *sr_cr = nor->bouncebuf;
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/* Check current Quad Enable bit value. */
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ret = read_cr(nor);
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@ -2177,7 +2176,7 @@ static const struct flash_info spi_nor_ids[] = {
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static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
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{
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int tmp;
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u8 id[SPI_NOR_MAX_ID_LEN];
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u8 *id = nor->bouncebuf;
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const struct flash_info *info;
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tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
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@ -2393,9 +2392,8 @@ static int spi_nor_check(struct spi_nor *nor)
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static int s3an_nor_scan(struct spi_nor *nor)
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{
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int ret;
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u8 val;
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ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
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ret = nor->read_reg(nor, SPINOR_OP_XRDSR, nor->bouncebuf, 1);
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if (ret < 0) {
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dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);
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return ret;
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@ -2417,7 +2415,7 @@ static int s3an_nor_scan(struct spi_nor *nor)
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* The current addressing mode can be read from the XRDSR register
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* and should not be changed, because is a destructive operation.
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*/
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if (val & XSR_PAGESIZE) {
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if (nor->bouncebuf[0] & XSR_PAGESIZE) {
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/* Flash in Power of 2 mode */
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nor->page_size = (nor->page_size == 264) ? 256 : 512;
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nor->mtd.writebufsize = nor->page_size;
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@ -4121,6 +4119,16 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
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nor->read_proto = SNOR_PROTO_1_1_1;
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nor->write_proto = SNOR_PROTO_1_1_1;
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/*
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* We need the bounce buffer early to read/write registers when going
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* through the spi-mem layer (buffers have to be DMA-able).
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*/
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nor->bouncebuf_size = PAGE_SIZE;
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nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
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GFP_KERNEL);
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if (!nor->bouncebuf)
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return -ENOMEM;
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if (name)
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info = spi_nor_match_id(name);
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/* Try to auto-detect if chip name wasn't specified or not found */
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@ -344,6 +344,9 @@ struct flash_info;
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* @mtd: point to a mtd_info structure
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* @lock: the lock for the read/write/erase/lock/unlock operations
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* @dev: point to a spi device, or a spi nor controller device.
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* @bouncebuf: bounce buffer used when the buffer passed by the MTD
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* layer is not DMA-able
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* @bouncebuf_size: size of the bounce buffer
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* @info: spi-nor part JDEC MFR id and other info
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* @page_size: the page size of the SPI NOR
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* @addr_width: number of address bytes
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@ -356,7 +359,6 @@ struct flash_info;
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* @read_proto: the SPI protocol for read operations
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* @write_proto: the SPI protocol for write operations
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* @reg_proto the SPI protocol for read_reg/write_reg/erase operations
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* @cmd_buf: used by the write_reg
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* @erase_map: the erase map of the SPI NOR
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* @prepare: [OPTIONAL] do some preparations for the
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* read/write/erase/lock/unlock operations
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@ -382,6 +384,8 @@ struct spi_nor {
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struct mtd_info mtd;
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struct mutex lock;
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struct device *dev;
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u8 *bouncebuf;
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size_t bouncebuf_size;
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const struct flash_info *info;
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u32 page_size;
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u8 addr_width;
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@ -394,7 +398,6 @@ struct spi_nor {
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enum spi_nor_protocol reg_proto;
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bool sst_write_second;
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u32 flags;
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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struct spi_nor_erase_map erase_map;
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int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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