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drm/amdgpu: add thm v13_0_2 ip headers (v3)
v1: Add thm v13_0_2 register offset and shift masks in header files (Hawking) v2: Clean up thm v13_0_2 registers (Alex) v3: update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
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2 changed files with 1643 additions and 0 deletions
346
drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h
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346
drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#ifndef _thm_13_0_2_OFFSET_HEADER
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#define _thm_13_0_2_OFFSET_HEADER
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// addressBlock: thm_thm_SmuThmDec
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// base address: 0x59800
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#define regTHM_TCON_CUR_TMP 0x0000
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#define regTHM_TCON_CUR_TMP_BASE_IDX 0
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#define regTHM_TCON_HTC 0x0001
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#define regTHM_TCON_HTC_BASE_IDX 0
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#define regTHM_TCON_THERM_TRIP 0x0002
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#define regTHM_TCON_THERM_TRIP_BASE_IDX 0
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#define regTHM_CTF_DELAY 0x0003
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#define regTHM_CTF_DELAY_BASE_IDX 0
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#define regTHM_GPIO_PROCHOT_CTRL 0x0004
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#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0
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#define regTHM_GPIO_THERMTRIP_CTRL 0x0005
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#define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0
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#define regTHM_GPIO_PWM_CTRL 0x0006
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#define regTHM_GPIO_PWM_CTRL_BASE_IDX 0
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#define regTHM_GPIO_TACHIN_CTRL 0x0007
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#define regTHM_GPIO_TACHIN_CTRL_BASE_IDX 0
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#define regTHM_GPIO_PUMPOUT_CTRL 0x0008
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#define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0
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#define regTHM_GPIO_PUMPIN_CTRL 0x0009
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#define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0
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#define regTHM_THERMAL_INT_ENA 0x000a
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#define regTHM_THERMAL_INT_ENA_BASE_IDX 0
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#define regTHM_THERMAL_INT_CTRL 0x000b
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#define regTHM_THERMAL_INT_CTRL_BASE_IDX 0
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#define regTHM_THERMAL_INT_STATUS 0x000c
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#define regTHM_THERMAL_INT_STATUS_BASE_IDX 0
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#define regTHM_TMON0_RDIL0_DATA 0x000d
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#define regTHM_TMON0_RDIL0_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL1_DATA 0x000e
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#define regTHM_TMON0_RDIL1_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL2_DATA 0x000f
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#define regTHM_TMON0_RDIL2_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL3_DATA 0x0010
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#define regTHM_TMON0_RDIL3_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL4_DATA 0x0011
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#define regTHM_TMON0_RDIL4_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL5_DATA 0x0012
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#define regTHM_TMON0_RDIL5_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL6_DATA 0x0013
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#define regTHM_TMON0_RDIL6_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL7_DATA 0x0014
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#define regTHM_TMON0_RDIL7_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL8_DATA 0x0015
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#define regTHM_TMON0_RDIL8_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL9_DATA 0x0016
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#define regTHM_TMON0_RDIL9_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL10_DATA 0x0017
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#define regTHM_TMON0_RDIL10_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL11_DATA 0x0018
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#define regTHM_TMON0_RDIL11_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL12_DATA 0x0019
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#define regTHM_TMON0_RDIL12_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL13_DATA 0x001a
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#define regTHM_TMON0_RDIL13_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL14_DATA 0x001b
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#define regTHM_TMON0_RDIL14_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIL15_DATA 0x001c
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#define regTHM_TMON0_RDIL15_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR0_DATA 0x001d
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#define regTHM_TMON0_RDIR0_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR1_DATA 0x001e
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#define regTHM_TMON0_RDIR1_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR2_DATA 0x001f
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#define regTHM_TMON0_RDIR2_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR3_DATA 0x0020
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#define regTHM_TMON0_RDIR3_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR4_DATA 0x0021
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#define regTHM_TMON0_RDIR4_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR5_DATA 0x0022
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#define regTHM_TMON0_RDIR5_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR6_DATA 0x0023
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#define regTHM_TMON0_RDIR6_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR7_DATA 0x0024
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#define regTHM_TMON0_RDIR7_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR8_DATA 0x0025
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#define regTHM_TMON0_RDIR8_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR9_DATA 0x0026
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#define regTHM_TMON0_RDIR9_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR10_DATA 0x0027
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#define regTHM_TMON0_RDIR10_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR11_DATA 0x0028
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#define regTHM_TMON0_RDIR11_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR12_DATA 0x0029
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#define regTHM_TMON0_RDIR12_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR13_DATA 0x002a
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#define regTHM_TMON0_RDIR13_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR14_DATA 0x002b
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#define regTHM_TMON0_RDIR14_DATA_BASE_IDX 0
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#define regTHM_TMON0_RDIR15_DATA 0x002c
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#define regTHM_TMON0_RDIR15_DATA_BASE_IDX 0
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#define regTHM_TMON0_INT_DATA 0x002d
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#define regTHM_TMON0_INT_DATA_BASE_IDX 0
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#define regTHM_TMON0_CTRL 0x002e
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#define regTHM_TMON0_CTRL_BASE_IDX 0
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#define regTHM_TMON0_CTRL2 0x002f
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#define regTHM_TMON0_CTRL2_BASE_IDX 0
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#define regTHM_TMON1_RDIL0_DATA 0x0031
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#define regTHM_TMON1_RDIL0_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL1_DATA 0x0032
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#define regTHM_TMON1_RDIL1_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL2_DATA 0x0033
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#define regTHM_TMON1_RDIL2_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL3_DATA 0x0034
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#define regTHM_TMON1_RDIL3_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL4_DATA 0x0035
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#define regTHM_TMON1_RDIL4_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL5_DATA 0x0036
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#define regTHM_TMON1_RDIL5_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL6_DATA 0x0037
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#define regTHM_TMON1_RDIL6_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL7_DATA 0x0038
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#define regTHM_TMON1_RDIL7_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL8_DATA 0x0039
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#define regTHM_TMON1_RDIL8_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL9_DATA 0x003a
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#define regTHM_TMON1_RDIL9_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL10_DATA 0x003b
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#define regTHM_TMON1_RDIL10_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL11_DATA 0x003c
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#define regTHM_TMON1_RDIL11_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL12_DATA 0x003d
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#define regTHM_TMON1_RDIL12_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL13_DATA 0x003e
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#define regTHM_TMON1_RDIL13_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL14_DATA 0x003f
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#define regTHM_TMON1_RDIL14_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIL15_DATA 0x0040
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#define regTHM_TMON1_RDIL15_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR0_DATA 0x0041
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#define regTHM_TMON1_RDIR0_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR1_DATA 0x0042
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#define regTHM_TMON1_RDIR1_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR2_DATA 0x0043
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#define regTHM_TMON1_RDIR2_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR3_DATA 0x0044
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#define regTHM_TMON1_RDIR3_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR4_DATA 0x0045
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#define regTHM_TMON1_RDIR4_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR5_DATA 0x0046
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#define regTHM_TMON1_RDIR5_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR6_DATA 0x0047
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#define regTHM_TMON1_RDIR6_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR7_DATA 0x0048
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#define regTHM_TMON1_RDIR7_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR8_DATA 0x0049
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#define regTHM_TMON1_RDIR8_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR9_DATA 0x004a
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#define regTHM_TMON1_RDIR9_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR10_DATA 0x004b
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#define regTHM_TMON1_RDIR10_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR11_DATA 0x004c
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#define regTHM_TMON1_RDIR11_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR12_DATA 0x004d
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#define regTHM_TMON1_RDIR12_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR13_DATA 0x004e
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#define regTHM_TMON1_RDIR13_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR14_DATA 0x004f
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#define regTHM_TMON1_RDIR14_DATA_BASE_IDX 0
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#define regTHM_TMON1_RDIR15_DATA 0x0050
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#define regTHM_TMON1_RDIR15_DATA_BASE_IDX 0
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#define regTHM_TMON1_INT_DATA 0x0051
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#define regTHM_TMON1_INT_DATA_BASE_IDX 0
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#define regTHM_DIE1_TEMP 0x0079
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#define regTHM_DIE1_TEMP_BASE_IDX 0
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#define regTHM_DIE2_TEMP 0x007a
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#define regTHM_DIE2_TEMP_BASE_IDX 0
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#define regTHM_DIE3_TEMP 0x007b
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#define regTHM_DIE3_TEMP_BASE_IDX 0
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#define regTHM_SW_TEMP 0x0081
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#define regTHM_SW_TEMP_BASE_IDX 0
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#define regCG_MULT_THERMAL_CTRL 0x0082
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#define regCG_MULT_THERMAL_CTRL_BASE_IDX 0
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#define regCG_MULT_THERMAL_STATUS 0x0083
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#define regCG_MULT_THERMAL_STATUS_BASE_IDX 0
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#define regCG_THERMAL_RANGE 0x0084
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#define regCG_THERMAL_RANGE_BASE_IDX 0
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#define regTHM_TMON_CONFIG 0x0085
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#define regTHM_TMON_CONFIG_BASE_IDX 0
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#define regTHM_TMON_CONFIG2 0x0086
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#define regTHM_TMON_CONFIG2_BASE_IDX 0
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#define regTHM_TMON0_COEFF 0x0087
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#define regTHM_TMON0_COEFF_BASE_IDX 0
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#define regTHM_TMON1_COEFF 0x0088
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#define regTHM_TMON1_COEFF_BASE_IDX 0
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#define regCG_FDO_CTRL0 0x008b
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#define regCG_FDO_CTRL0_BASE_IDX 0
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#define regCG_FDO_CTRL1 0x008c
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#define regCG_FDO_CTRL1_BASE_IDX 0
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#define regCG_FDO_CTRL2 0x008d
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#define regCG_FDO_CTRL2_BASE_IDX 0
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#define regCG_TACH_CTRL 0x008e
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#define regCG_TACH_CTRL_BASE_IDX 0
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#define regCG_TACH_STATUS 0x008f
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#define regCG_TACH_STATUS_BASE_IDX 0
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#define regCG_THERMAL_STATUS 0x0090
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#define regCG_THERMAL_STATUS_BASE_IDX 0
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#define regCG_PUMP_CTRL0 0x0091
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#define regCG_PUMP_CTRL0_BASE_IDX 0
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#define regCG_PUMP_CTRL1 0x0092
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#define regCG_PUMP_CTRL1_BASE_IDX 0
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#define regCG_PUMP_CTRL2 0x0093
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#define regCG_PUMP_CTRL2_BASE_IDX 0
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#define regCG_PUMP_TACH_CTRL 0x0094
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#define regCG_PUMP_TACH_CTRL_BASE_IDX 0
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#define regCG_PUMP_TACH_STATUS 0x0095
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#define regCG_PUMP_TACH_STATUS_BASE_IDX 0
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#define regCG_PUMP_STATUS 0x0096
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#define regCG_PUMP_STATUS_BASE_IDX 0
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#define regTHM_TCON_LOCAL0 0x0097
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#define regTHM_TCON_LOCAL0_BASE_IDX 0
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#define regTHM_TCON_LOCAL1 0x0098
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#define regTHM_TCON_LOCAL1_BASE_IDX 0
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#define regTHM_TCON_LOCAL2 0x0099
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#define regTHM_TCON_LOCAL2_BASE_IDX 0
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#define regTHM_TCON_LOCAL3 0x009a
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#define regTHM_TCON_LOCAL3_BASE_IDX 0
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#define regTHM_TCON_LOCAL4 0x009b
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#define regTHM_TCON_LOCAL4_BASE_IDX 0
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#define regTHM_TCON_LOCAL5 0x009c
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#define regTHM_TCON_LOCAL5_BASE_IDX 0
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#define regTHM_TCON_LOCAL6 0x009d
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#define regTHM_TCON_LOCAL6_BASE_IDX 0
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#define regTHM_TCON_LOCAL7 0x009e
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#define regTHM_TCON_LOCAL7_BASE_IDX 0
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#define regTHM_TCON_LOCAL8 0x009f
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#define regTHM_TCON_LOCAL8_BASE_IDX 0
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#define regTHM_TCON_LOCAL9 0x00a0
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#define regTHM_TCON_LOCAL9_BASE_IDX 0
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#define regTHM_TCON_LOCAL10 0x00a1
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#define regTHM_TCON_LOCAL10_BASE_IDX 0
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#define regTHM_TCON_LOCAL11 0x00a2
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#define regTHM_TCON_LOCAL11_BASE_IDX 0
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#define regTHM_TCON_LOCAL12 0x00a3
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#define regTHM_TCON_LOCAL12_BASE_IDX 0
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#define regTHM_TCON_LOCAL14 0x00a4
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#define regTHM_TCON_LOCAL14_BASE_IDX 0
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#define regTHM_TCON_LOCAL15 0x00a5
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#define regTHM_TCON_LOCAL15_BASE_IDX 0
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#define regTHM_TCON_LOCAL13 0x00a6
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#define regTHM_TCON_LOCAL13_BASE_IDX 0
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#define regXTAL_CNTL 0x00ac
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#define regXTAL_CNTL_BASE_IDX 0
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#define regTHM_PWRMGT 0x00ad
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#define regTHM_PWRMGT_BASE_IDX 0
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#define regTHM_GPIO_MACO_EN_CTRL 0x00ae
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#define regTHM_GPIO_MACO_EN_CTRL_BASE_IDX 0
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#define regSBTSI_REMOTE_TEMP 0x00ca
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#define regSBTSI_REMOTE_TEMP_BASE_IDX 0
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#define regSBRMI_CONTROL 0x00cb
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#define regSBRMI_CONTROL_BASE_IDX 0
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#define regSBRMI_COMMAND 0x00cc
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#define regSBRMI_COMMAND_BASE_IDX 0
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#define regSBRMI_WRITE_DATA0 0x00cd
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#define regSBRMI_WRITE_DATA0_BASE_IDX 0
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#define regSBRMI_WRITE_DATA1 0x00ce
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#define regSBRMI_WRITE_DATA1_BASE_IDX 0
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#define regSBRMI_WRITE_DATA2 0x00cf
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#define regSBRMI_WRITE_DATA2_BASE_IDX 0
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#define regSBRMI_READ_DATA0 0x00d0
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#define regSBRMI_READ_DATA0_BASE_IDX 0
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#define regSBRMI_READ_DATA1 0x00d1
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#define regSBRMI_READ_DATA1_BASE_IDX 0
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#define regSBRMI_CORE_EN_NUMBER 0x00d2
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#define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0
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#define regSBRMI_CORE_EN_STATUS0 0x00d3
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#define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0
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#define regSBRMI_CORE_EN_STATUS1 0x00d4
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#define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0
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#define regSBRMI_APIC_STATUS0 0x00d5
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#define regSBRMI_APIC_STATUS0_BASE_IDX 0
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#define regSBRMI_APIC_STATUS1 0x00d6
|
||||
#define regSBRMI_APIC_STATUS1_BASE_IDX 0
|
||||
#define regSBRMI_MCE_STATUS0 0x00db
|
||||
#define regSBRMI_MCE_STATUS0_BASE_IDX 0
|
||||
#define regSBRMI_MCE_STATUS1 0x00dc
|
||||
#define regSBRMI_MCE_STATUS1_BASE_IDX 0
|
||||
#define regSMBUS_CNTL0 0x00df
|
||||
#define regSMBUS_CNTL0_BASE_IDX 0
|
||||
#define regSMBUS_CNTL1 0x00e0
|
||||
#define regSMBUS_CNTL1_BASE_IDX 0
|
||||
#define regSMBUS_BLKWR_CMD_CTRL0 0x00e1
|
||||
#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0
|
||||
#define regSMBUS_BLKWR_CMD_CTRL1 0x00e2
|
||||
#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0
|
||||
#define regSMBUS_BLKRD_CMD_CTRL0 0x00e3
|
||||
#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0
|
||||
#define regSMBUS_BLKRD_CMD_CTRL1 0x00e4
|
||||
#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0
|
||||
#define regSMBUS_TIMING_CNTL0 0x00e5
|
||||
#define regSMBUS_TIMING_CNTL0_BASE_IDX 0
|
||||
#define regSMBUS_TIMING_CNTL1 0x00e6
|
||||
#define regSMBUS_TIMING_CNTL1_BASE_IDX 0
|
||||
#define regSMBUS_TIMING_CNTL2 0x00e7
|
||||
#define regSMBUS_TIMING_CNTL2_BASE_IDX 0
|
||||
#define regSMBUS_TRIGGER_CNTL 0x00e8
|
||||
#define regSMBUS_TRIGGER_CNTL_BASE_IDX 0
|
||||
#define regSMBUS_UDID_CNTL0 0x00e9
|
||||
#define regSMBUS_UDID_CNTL0_BASE_IDX 0
|
||||
#define regSMBUS_UDID_CNTL1 0x00ea
|
||||
#define regSMBUS_UDID_CNTL1_BASE_IDX 0
|
||||
#define regSMBUS_UDID_CNTL2 0x00eb
|
||||
#define regSMBUS_UDID_CNTL2_BASE_IDX 0
|
||||
#define regTHM_TMON0_REMOTE_START 0x0100
|
||||
#define regTHM_TMON0_REMOTE_START_BASE_IDX 0
|
||||
#define regTHM_TMON0_REMOTE_END 0x013f
|
||||
#define regTHM_TMON0_REMOTE_END_BASE_IDX 0
|
||||
#define regTHM_TMON1_REMOTE_START 0x0140
|
||||
#define regTHM_TMON1_REMOTE_START_BASE_IDX 0
|
||||
#define regTHM_TMON1_REMOTE_END 0x017f
|
||||
#define regTHM_TMON1_REMOTE_END_BASE_IDX 0
|
||||
#define regTHM_TMON2_REMOTE_START 0x0180
|
||||
#define regTHM_TMON2_REMOTE_START_BASE_IDX 0
|
||||
#define regTHM_TMON2_REMOTE_END 0x01bf
|
||||
#define regTHM_TMON2_REMOTE_END_BASE_IDX 0
|
||||
|
||||
#endif
|
1297
drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h
Normal file
1297
drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h
Normal file
File diff suppressed because it is too large
Load diff
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Reference in a new issue