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drm-fixes for -rc7
- two fbcon regressions - amdgpu: dp mst, smu13 - i915: dual link dsi for tgl+ - armada, nouveau, drm/sched, fbmem -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEb4nG6jLu8Y5XI+PfTA9ye/CYqnEFAmQ4XEYACgkQTA9ye/CY qnFDIA/9FZJx4rW3rNl1fSN9UufQuDBq86kOECbG53VM9QcZVdDaV35cWBEyqG4p Ue8M3aZwltZ0+x6qeZ0rV+qZKlD3KYidq/MgW0YGPdVvSdrdVk0OOc4N6uQU1P1v Phr0hFHVao0+bWQE5gdK9S7DW23m/ys0y0C+LXVRNWWf4kVh5DFSjaqEo+SU8Gj1 6GOUWf+rH44r4cHqx4sgZ8r79jWdc3Bjb6OLSE3YVhyU2cffVJ8+AgIA6JyStOR0 tw0NKfAMI0BBlEewvvNWqKcLvZ7qz5bG+byy6amzX8bLmdyyz2BarM5MKSf7F0NY BC2GiQKUEh+hLsvUhLdqYV2iLKRI2Qjd0ESYF9WO2UElsTEf/2tuGKD5WTMmdJLG 1BjEC1lQL/uSHWy+9qpppEKkmQHo+6MLlvbbbNVxgz8n/ysxnJGTe5ntGRWc88nR 7yrHILf5Ry7/4D+PBctZqalf/JfklrY3hIuTl6XTgLE6eKM5Wgc2xn0ItmUXQD9i B18TCUiElr/FlMyw/oTWcstrI9rjrAv9FBZ0qoEqkXCfu7TPT+tJ+6oLq2rCJKUh 4GuzOm7PYFBu0lof8Cmthz/Z8GDKJrdgdfDfp8yJp7jmIz2q8Xm3yqG66xSQKuAE dOJpHIrQgQAxgTvsSAALXmlPN2XAp5dHBaS4vXPgbFNKWkWi3H0= =aI2h -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2023-04-13' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Daniel Vetter: - two fbcon regressions - amdgpu: dp mst, smu13 - i915: dual link dsi for tgl+ - armada, nouveau, drm/sched, fbmem * tag 'drm-fixes-2023-04-13' of git://anongit.freedesktop.org/drm/drm: fbcon: set_con2fb_map needs to set con2fb_map! fbcon: Fix error paths in set_con2fb_map drm/amd/pm: correct the pcie link state check for SMU13 drm/amd/pm: correct SMU13.0.7 max shader clock reporting drm/amd/pm: correct SMU13.0.7 pstate profiling clock settings drm/amd/display: Pass the right info to drm_dp_remove_payload drm/armada: Fix a potential double free in an error handling path fbmem: Reject FB_ACTIVATE_KD_TEXT from userspace drm/nouveau/fb: add missing sysmen flush callbacks drm/i915/dsi: fix DSS CTL register offsets for TGL+ drm/scheduler: Fix UAF race in drm_sched_entity_push_job()
This commit is contained in:
commit
f1be7b6c16
13 changed files with 175 additions and 35 deletions
|
@ -177,6 +177,40 @@ void dm_helpers_dp_update_branch_info(
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const struct dc_link *link)
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{}
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static void dm_helpers_construct_old_payload(
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struct dc_link *link,
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int pbn_per_slot,
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struct drm_dp_mst_atomic_payload *new_payload,
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struct drm_dp_mst_atomic_payload *old_payload)
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{
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struct link_mst_stream_allocation_table current_link_table =
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link->mst_stream_alloc_table;
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struct link_mst_stream_allocation *dc_alloc;
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int i;
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*old_payload = *new_payload;
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/* Set correct time_slots/PBN of old payload.
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* other fields (delete & dsc_enabled) in
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* struct drm_dp_mst_atomic_payload are don't care fields
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* while calling drm_dp_remove_payload()
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*/
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for (i = 0; i < current_link_table.stream_count; i++) {
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dc_alloc =
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¤t_link_table.stream_allocations[i];
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if (dc_alloc->vcp_id == new_payload->vcpi) {
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old_payload->time_slots = dc_alloc->slot_count;
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old_payload->pbn = dc_alloc->slot_count * pbn_per_slot;
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break;
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}
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}
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/* make sure there is an old payload*/
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ASSERT(i != current_link_table.stream_count);
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}
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/*
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* Writes payload allocation table in immediate downstream device.
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*/
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@ -188,7 +222,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
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{
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struct amdgpu_dm_connector *aconnector;
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struct drm_dp_mst_topology_state *mst_state;
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struct drm_dp_mst_atomic_payload *payload;
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struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
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struct drm_dp_mst_topology_mgr *mst_mgr;
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aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
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@ -204,17 +238,26 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
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mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
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/* It's OK for this to fail */
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payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
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if (enable)
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drm_dp_add_payload_part1(mst_mgr, mst_state, payload);
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else
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drm_dp_remove_payload(mst_mgr, mst_state, payload, payload);
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new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
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if (enable) {
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target_payload = new_payload;
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drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
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} else {
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/* construct old payload by VCPI*/
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dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div,
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new_payload, &old_payload);
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target_payload = &old_payload;
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drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload);
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}
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/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
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* AUX message. The sequence is slot 1-63 allocated sequence for each
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* stream. AMD ASIC stream slot allocation should follow the same
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* sequence. copy DRM MST allocation to dc */
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fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table);
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fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
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return true;
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}
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@ -61,6 +61,12 @@
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#define CTF_OFFSET_HOTSPOT 5
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#define CTF_OFFSET_MEM 5
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static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
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static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
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#define DECODE_GEN_SPEED(gen_speed_idx) (pmfw_decoded_link_speed[gen_speed_idx])
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#define DECODE_LANE_WIDTH(lane_width_idx) (pmfw_decoded_link_width[lane_width_idx])
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struct smu_13_0_max_sustainable_clocks {
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uint32_t display_clock;
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uint32_t phy_clock;
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@ -1144,8 +1144,8 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
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(pcie_table->pcie_lane[i] == 5) ? "x12" :
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(pcie_table->pcie_lane[i] == 6) ? "x16" : "",
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pcie_table->clk_freq[i],
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((gen_speed - 1) == pcie_table->pcie_gen[i]) &&
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(lane_width == link_width[pcie_table->pcie_lane[i]]) ?
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(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
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(lane_width == DECODE_LANE_WIDTH(link_width[pcie_table->pcie_lane[i]])) ?
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"*" : "");
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break;
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@ -575,6 +575,14 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
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dpm_table);
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if (ret)
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return ret;
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if (skutable->DriverReportedClocks.GameClockAc &&
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(dpm_table->dpm_levels[dpm_table->count - 1].value >
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skutable->DriverReportedClocks.GameClockAc)) {
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dpm_table->dpm_levels[dpm_table->count - 1].value =
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skutable->DriverReportedClocks.GameClockAc;
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dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
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}
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} else {
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dpm_table->count = 1;
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dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
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@ -828,6 +836,57 @@ static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
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return ret;
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}
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static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t *min,
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uint32_t *max)
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{
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struct smu_13_0_dpm_context *dpm_context =
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smu->smu_dpm.dpm_context;
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struct smu_13_0_dpm_table *dpm_table;
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switch (clk_type) {
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case SMU_MCLK:
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case SMU_UCLK:
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/* uclk dpm table */
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dpm_table = &dpm_context->dpm_tables.uclk_table;
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break;
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case SMU_GFXCLK:
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case SMU_SCLK:
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/* gfxclk dpm table */
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dpm_table = &dpm_context->dpm_tables.gfx_table;
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break;
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case SMU_SOCCLK:
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/* socclk dpm table */
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dpm_table = &dpm_context->dpm_tables.soc_table;
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break;
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case SMU_FCLK:
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/* fclk dpm table */
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dpm_table = &dpm_context->dpm_tables.fclk_table;
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break;
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case SMU_VCLK:
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case SMU_VCLK1:
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/* vclk dpm table */
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dpm_table = &dpm_context->dpm_tables.vclk_table;
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break;
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case SMU_DCLK:
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case SMU_DCLK1:
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/* dclk dpm table */
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dpm_table = &dpm_context->dpm_tables.dclk_table;
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break;
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default:
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dev_err(smu->adev->dev, "Unsupported clock type!\n");
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return -EINVAL;
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}
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if (min)
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*min = dpm_table->min;
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if (max)
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*max = dpm_table->max;
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return 0;
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}
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static int smu_v13_0_7_read_sensor(struct smu_context *smu,
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enum amd_pp_sensors sensor,
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void *data,
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@ -1074,8 +1133,8 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
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(pcie_table->pcie_lane[i] == 5) ? "x12" :
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(pcie_table->pcie_lane[i] == 6) ? "x16" : "",
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pcie_table->clk_freq[i],
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(gen_speed == pcie_table->pcie_gen[i]) &&
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(lane_width == pcie_table->pcie_lane[i]) ?
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(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
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(lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
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"*" : "");
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break;
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@ -1329,9 +1388,17 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
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&dpm_context->dpm_tables.fclk_table;
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struct smu_umd_pstate_table *pstate_table =
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&smu->pstate_table;
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struct smu_table_context *table_context = &smu->smu_table;
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PPTable_t *pptable = table_context->driver_pptable;
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DriverReportedClocks_t driver_clocks =
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pptable->SkuTable.DriverReportedClocks;
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pstate_table->gfxclk_pstate.min = gfx_table->min;
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pstate_table->gfxclk_pstate.peak = gfx_table->max;
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if (driver_clocks.GameClockAc &&
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(driver_clocks.GameClockAc < gfx_table->max))
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pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
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else
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pstate_table->gfxclk_pstate.peak = gfx_table->max;
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pstate_table->uclk_pstate.min = mem_table->min;
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pstate_table->uclk_pstate.peak = mem_table->max;
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@ -1348,12 +1415,12 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
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pstate_table->fclk_pstate.min = fclk_table->min;
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pstate_table->fclk_pstate.peak = fclk_table->max;
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/*
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* For now, just use the mininum clock frequency.
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* TODO: update them when the real pstate settings available
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*/
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pstate_table->gfxclk_pstate.standard = gfx_table->min;
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pstate_table->uclk_pstate.standard = mem_table->min;
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if (driver_clocks.BaseClockAc &&
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driver_clocks.BaseClockAc < gfx_table->max)
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pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
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else
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pstate_table->gfxclk_pstate.standard = gfx_table->max;
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pstate_table->uclk_pstate.standard = mem_table->max;
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pstate_table->socclk_pstate.standard = soc_table->min;
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pstate_table->vclk_pstate.standard = vclk_table->min;
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pstate_table->dclk_pstate.standard = dclk_table->min;
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|
@ -1676,7 +1743,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
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.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
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.init_pptable_microcode = smu_v13_0_init_pptable_microcode,
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.populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
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.get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
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.get_dpm_ultimate_freq = smu_v13_0_7_get_dpm_ultimate_freq,
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.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
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.read_sensor = smu_v13_0_7_read_sensor,
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.feature_is_enabled = smu_cmn_feature_is_enabled,
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|
|
|
@ -99,7 +99,6 @@ static int armada_drm_bind(struct device *dev)
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if (ret) {
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dev_err(dev, "[" DRM_NAME ":%s] can't kick out simple-fb: %d\n",
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__func__, ret);
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kfree(priv);
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return ret;
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}
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|
|
|
@ -300,9 +300,21 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
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u32 dss_ctl1;
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|
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dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
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/* FIXME: Move all DSS handling to intel_vdsc.c */
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if (DISPLAY_VER(dev_priv) >= 12) {
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
|
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|
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dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
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dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
|
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} else {
|
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dss_ctl1_reg = DSS_CTL1;
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dss_ctl2_reg = DSS_CTL2;
|
||||
}
|
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|
||||
dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
|
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dss_ctl1 |= SPLITTER_ENABLE;
|
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dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
|
||||
dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
|
||||
|
@ -323,16 +335,16 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
|
|||
|
||||
dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
|
||||
dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
|
||||
dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
|
||||
dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg);
|
||||
dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
|
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dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
|
||||
intel_de_write(dev_priv, DSS_CTL2, dss_ctl2);
|
||||
intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2);
|
||||
} else {
|
||||
/* Interleave */
|
||||
dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
|
||||
}
|
||||
|
||||
intel_de_write(dev_priv, DSS_CTL1, dss_ctl1);
|
||||
intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
|
||||
}
|
||||
|
||||
/* aka DSI 8X clock */
|
||||
|
|
|
@ -31,6 +31,7 @@ gf108_fb = {
|
|||
.init = gf100_fb_init,
|
||||
.init_page = gf100_fb_init_page,
|
||||
.intr = gf100_fb_intr,
|
||||
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
|
||||
.ram_new = gf108_ram_new,
|
||||
.default_bigpage = 17,
|
||||
};
|
||||
|
|
|
@ -77,6 +77,7 @@ gk104_fb = {
|
|||
.init = gf100_fb_init,
|
||||
.init_page = gf100_fb_init_page,
|
||||
.intr = gf100_fb_intr,
|
||||
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
|
||||
.ram_new = gk104_ram_new,
|
||||
.default_bigpage = 17,
|
||||
.clkgate_pack = gk104_fb_clkgate_pack,
|
||||
|
|
|
@ -59,6 +59,7 @@ gk110_fb = {
|
|||
.init = gf100_fb_init,
|
||||
.init_page = gf100_fb_init_page,
|
||||
.intr = gf100_fb_intr,
|
||||
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
|
||||
.ram_new = gk104_ram_new,
|
||||
.default_bigpage = 17,
|
||||
.clkgate_pack = gk110_fb_clkgate_pack,
|
||||
|
|
|
@ -31,6 +31,7 @@ gm107_fb = {
|
|||
.init = gf100_fb_init,
|
||||
.init_page = gf100_fb_init_page,
|
||||
.intr = gf100_fb_intr,
|
||||
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
|
||||
.ram_new = gm107_ram_new,
|
||||
.default_bigpage = 17,
|
||||
};
|
||||
|
|
|
@ -507,12 +507,19 @@ void drm_sched_entity_push_job(struct drm_sched_job *sched_job)
|
|||
{
|
||||
struct drm_sched_entity *entity = sched_job->entity;
|
||||
bool first;
|
||||
ktime_t submit_ts;
|
||||
|
||||
trace_drm_sched_job(sched_job, entity);
|
||||
atomic_inc(entity->rq->sched->score);
|
||||
WRITE_ONCE(entity->last_user, current->group_leader);
|
||||
|
||||
/*
|
||||
* After the sched_job is pushed into the entity queue, it may be
|
||||
* completed and freed up at any time. We can no longer access it.
|
||||
* Make sure to set the submit_ts first, to avoid a race.
|
||||
*/
|
||||
sched_job->submit_ts = submit_ts = ktime_get();
|
||||
first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node);
|
||||
sched_job->submit_ts = ktime_get();
|
||||
|
||||
/* first job wakes up scheduler */
|
||||
if (first) {
|
||||
|
@ -529,7 +536,7 @@ void drm_sched_entity_push_job(struct drm_sched_job *sched_job)
|
|||
spin_unlock(&entity->rq_lock);
|
||||
|
||||
if (drm_sched_policy == DRM_SCHED_POLICY_FIFO)
|
||||
drm_sched_rq_update_fifo(entity, sched_job->submit_ts);
|
||||
drm_sched_rq_update_fifo(entity, submit_ts);
|
||||
|
||||
drm_sched_wakeup(entity->rq->sched);
|
||||
}
|
||||
|
|
|
@ -823,7 +823,7 @@ static int set_con2fb_map(int unit, int newidx, int user)
|
|||
int oldidx = con2fb_map[unit];
|
||||
struct fb_info *info = fbcon_registered_fb[newidx];
|
||||
struct fb_info *oldinfo = NULL;
|
||||
int found, err = 0, show_logo;
|
||||
int err = 0, show_logo;
|
||||
|
||||
WARN_CONSOLE_UNLOCKED();
|
||||
|
||||
|
@ -841,26 +841,26 @@ static int set_con2fb_map(int unit, int newidx, int user)
|
|||
if (oldidx != -1)
|
||||
oldinfo = fbcon_registered_fb[oldidx];
|
||||
|
||||
found = search_fb_in_map(newidx);
|
||||
|
||||
if (!err && !found) {
|
||||
if (!search_fb_in_map(newidx)) {
|
||||
err = con2fb_acquire_newinfo(vc, info, unit);
|
||||
if (!err)
|
||||
con2fb_map[unit] = newidx;
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
fbcon_add_cursor_work(info);
|
||||
}
|
||||
|
||||
con2fb_map[unit] = newidx;
|
||||
|
||||
/*
|
||||
* If old fb is not mapped to any of the consoles,
|
||||
* fbcon should release it.
|
||||
*/
|
||||
if (!err && oldinfo && !search_fb_in_map(oldidx))
|
||||
if (oldinfo && !search_fb_in_map(oldidx))
|
||||
con2fb_release_oldinfo(vc, oldinfo, info);
|
||||
|
||||
show_logo = (fg_console == 0 && !user &&
|
||||
logo_shown != FBCON_LOGO_DONTSHOW);
|
||||
|
||||
if (!found)
|
||||
fbcon_add_cursor_work(info);
|
||||
con2fb_map_boot[unit] = newidx;
|
||||
con2fb_init_display(vc, info, unit, show_logo);
|
||||
|
||||
|
|
|
@ -1116,6 +1116,8 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
|
|||
case FBIOPUT_VSCREENINFO:
|
||||
if (copy_from_user(&var, argp, sizeof(var)))
|
||||
return -EFAULT;
|
||||
/* only for kernel-internal use */
|
||||
var.activate &= ~FB_ACTIVATE_KD_TEXT;
|
||||
console_lock();
|
||||
lock_fb_info(info);
|
||||
ret = fbcon_modechange_possible(info, &var);
|
||||
|
|
Loading…
Reference in a new issue