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EDAC, amd64: Add AMD Fam17h family type and ops
Add a family type and associated ops for Fam17h. Define a struct to hold all the UMC registers that we need. Make this a part of struct amd64_pvt in order to maximize code reuse in the rest of the driver. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1479423463-8536-10-git-send-email-Yazen.Ghannam@amd.com Signed-off-by: Borislav Petkov <bp@suse.de>
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196b79fcc8
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f1cbbec9fc
2 changed files with 54 additions and 1 deletions
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@ -1210,6 +1210,19 @@ static int f1x_early_channel_count(struct amd64_pvt *pvt)
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return channels;
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return channels;
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}
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}
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static int f17_early_channel_count(struct amd64_pvt *pvt)
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{
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int i, channels = 0;
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/* SDP Control bit 31 (SdpInit) is clear for unused UMC channels */
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for (i = 0; i < NUM_UMCS; i++)
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channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);
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amd64_info("MCT channel count: %d\n", channels);
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return channels;
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}
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static int ddr3_cs_size(unsigned i, bool dct_width)
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static int ddr3_cs_size(unsigned i, bool dct_width)
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{
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{
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unsigned shift = 0;
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unsigned shift = 0;
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@ -1337,6 +1350,23 @@ static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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return ddr3_cs_size(cs_mode, false);
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return ddr3_cs_size(cs_mode, false);
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}
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}
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static int f17_base_addr_to_cs_size(struct amd64_pvt *pvt, u8 umc,
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unsigned int cs_mode, int csrow_nr)
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{
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u32 base_addr = pvt->csels[umc].csbases[csrow_nr];
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/* Each mask is used for every two base addresses. */
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u32 addr_mask = pvt->csels[umc].csmasks[csrow_nr >> 1];
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/* Register [31:1] = Address [39:9]. Size is in kBs here. */
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u32 size = ((addr_mask >> 1) - (base_addr >> 1) + 1) >> 1;
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edac_dbg(1, "BaseAddr: 0x%x, AddrMask: 0x%x\n", base_addr, addr_mask);
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/* Return size in MBs. */
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return size >> 10;
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}
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static void read_dram_ctl_register(struct amd64_pvt *pvt)
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static void read_dram_ctl_register(struct amd64_pvt *pvt)
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{
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{
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@ -1989,6 +2019,15 @@ static struct amd64_family_type family_types[] = {
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.dbam_to_cs = f16_dbam_to_chip_select,
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.dbam_to_cs = f16_dbam_to_chip_select,
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}
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}
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},
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},
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[F17_CPUS] = {
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.ctl_name = "F17h",
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.f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,
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.f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_base_addr_to_cs_size,
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}
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},
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};
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};
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/*
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/*
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@ -2790,6 +2829,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
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pvt->ops = &family_types[F16_CPUS].ops;
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pvt->ops = &family_types[F16_CPUS].ops;
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break;
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break;
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case 0x17:
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fam_type = &family_types[F17_CPUS];
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pvt->ops = &family_types[F17_CPUS].ops;
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break;
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default:
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default:
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amd64_err("Unsupported family!\n");
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amd64_err("Unsupported family!\n");
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return NULL;
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return NULL;
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@ -118,6 +118,8 @@
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#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
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#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
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#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
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#define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
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/*
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/*
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* Function 1 - Address Map
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* Function 1 - Address Map
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@ -266,6 +268,7 @@ enum amd_families {
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F15_M60H_CPUS,
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F15_M60H_CPUS,
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F16_CPUS,
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F16_CPUS,
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F16_M30H_CPUS,
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F16_M30H_CPUS,
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F17_CPUS,
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NUM_FAMILIES,
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NUM_FAMILIES,
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};
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};
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@ -298,6 +301,10 @@ struct chip_select {
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u8 m_cnt;
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u8 m_cnt;
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};
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};
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struct amd64_umc {
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u32 sdp_ctrl; /* SDP Control reg */
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};
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struct amd64_pvt {
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struct amd64_pvt {
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struct low_ops *ops;
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struct low_ops *ops;
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@ -345,6 +352,8 @@ struct amd64_pvt {
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/* cache the dram_type */
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/* cache the dram_type */
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enum mem_type dram_type;
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enum mem_type dram_type;
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struct amd64_umc *umc; /* UMC registers */
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};
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};
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enum err_codes {
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enum err_codes {
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@ -438,7 +447,7 @@ struct low_ops {
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struct amd64_family_type {
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struct amd64_family_type {
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const char *ctl_name;
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const char *ctl_name;
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u16 f1_id, f2_id;
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u16 f0_id, f1_id, f2_id, f6_id;
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struct low_ops ops;
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struct low_ops ops;
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};
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};
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