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net: phy: nxp-c45-tja11xx: add TJA1120 support
Add TJA1120 driver entry and its driver_data. Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20230731091619.77961-6-radu-nicolae.pirea@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Radu Pirea (NXP OSS)
Jakub Kicinski
parent
369da33356
commit
f1fe5dff2b
2 changed files with 160 additions and 1 deletions
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@ -306,7 +306,7 @@ config NXP_C45_TJA11XX_PHY
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depends on PTP_1588_CLOCK_OPTIONAL
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help
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Enable support for NXP C45 TJA11XX PHYs.
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Currently supports only the TJA1103 PHY.
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Currently supports the TJA1103 and TJA1120 PHYs.
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config NXP_TJA11XX_PHY
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tristate "NXP TJA11xx PHYs support"
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@ -18,12 +18,17 @@
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#include <linux/net_tstamp.h>
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#define PHY_ID_TJA_1103 0x001BB010
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#define PHY_ID_TJA_1120 0x001BB031
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#define VEND1_DEVICE_CONTROL 0x0040
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#define DEVICE_CONTROL_RESET BIT(15)
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#define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14)
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#define DEVICE_CONTROL_CONFIG_ALL_EN BIT(13)
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#define VEND1_DEVICE_CONFIG 0x0048
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#define TJA1120_VEND1_EXT_TS_MODE 0x1012
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#define VEND1_PHY_IRQ_ACK 0x80A0
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#define VEND1_PHY_IRQ_EN 0x80A1
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#define VEND1_PHY_IRQ_STATUS 0x80A2
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@ -76,6 +81,14 @@
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#define MII_BASIC_CONFIG_RMII 0x5
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#define MII_BASIC_CONFIG_MII 0x4
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#define VEND1_SYMBOL_ERROR_CNT_XTD 0x8351
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#define EXTENDED_CNT_EN BIT(15)
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#define VEND1_MONITOR_STATUS 0xAC80
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#define MONITOR_RESET BIT(15)
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#define VEND1_MONITOR_CONFIG 0xAC86
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#define LOST_FRAMES_CNT_EN BIT(9)
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#define ALL_FRAMES_CNT_EN BIT(8)
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#define VEND1_SYMBOL_ERROR_COUNTER 0x8350
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#define VEND1_LINK_DROP_COUNTER 0x8352
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#define VEND1_LINK_LOSSES_AND_FAILURES 0x8353
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@ -94,6 +107,10 @@
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#define VEND1_RX_TS_INSRT_CTRL 0x114D
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#define TJA1103_RX_TS_INSRT_MODE2 0x02
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#define TJA1120_RX_TS_INSRT_CTRL 0x9012
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#define TJA1120_RX_TS_INSRT_EN BIT(15)
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#define TJA1120_TS_INSRT_MODE BIT(4)
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#define VEND1_EGR_RING_DATA_0 0x114E
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#define VEND1_EGR_RING_CTRL 0x1154
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@ -110,6 +127,7 @@
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#define PORT_PTP_CONTROL_BYPASS BIT(11)
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#define PTP_CLK_PERIOD_100BT1 15ULL
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#define PTP_CLK_PERIOD_1000BT1 8ULL
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#define EVENT_MSG_FILT_ALL 0x0F
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#define EVENT_MSG_FILT_NONE 0x00
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@ -929,6 +947,27 @@ static const struct nxp_c45_phy_stats tja1103_hw_stats[] = {
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NXP_C45_REG_FIELD(0xAFD1, MDIO_MMD_VEND1, 0, 9), },
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};
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static const struct nxp_c45_phy_stats tja1120_hw_stats[] = {
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{ "phy_symbol_error_cnt_ext",
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NXP_C45_REG_FIELD(0x8351, MDIO_MMD_VEND1, 0, 14) },
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{ "tx_frames_xtd",
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NXP_C45_REG_FIELD(0xACA1, MDIO_MMD_VEND1, 0, 8), },
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{ "tx_frames",
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NXP_C45_REG_FIELD(0xACA0, MDIO_MMD_VEND1, 0, 16), },
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{ "rx_frames_xtd",
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NXP_C45_REG_FIELD(0xACA3, MDIO_MMD_VEND1, 0, 8), },
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{ "rx_frames",
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NXP_C45_REG_FIELD(0xACA2, MDIO_MMD_VEND1, 0, 16), },
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{ "tx_lost_frames_xtd",
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NXP_C45_REG_FIELD(0xACA5, MDIO_MMD_VEND1, 0, 8), },
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{ "tx_lost_frames",
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NXP_C45_REG_FIELD(0xACA4, MDIO_MMD_VEND1, 0, 16), },
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{ "rx_lost_frames_xtd",
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NXP_C45_REG_FIELD(0xACA7, MDIO_MMD_VEND1, 0, 8), },
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{ "rx_lost_frames",
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NXP_C45_REG_FIELD(0xACA6, MDIO_MMD_VEND1, 0, 16), },
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};
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static int nxp_c45_get_sset_count(struct phy_device *phydev)
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{
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const struct nxp_c45_phy_data *phy_data = nxp_c45_get_data(phydev);
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@ -1511,6 +1550,101 @@ static const struct nxp_c45_phy_data tja1103_phy_data = {
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.ptp_enable = tja1103_ptp_enable,
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};
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static void tja1120_counters_enable(struct phy_device *phydev)
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{
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD,
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EXTENDED_CNT_EN);
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS,
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MONITOR_RESET);
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG,
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ALL_FRAMES_CNT_EN | LOST_FRAMES_CNT_EN);
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}
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static void tja1120_ptp_init(struct phy_device *phydev)
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{
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phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_RX_TS_INSRT_CTRL,
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TJA1120_RX_TS_INSRT_EN | TJA1120_TS_INSRT_MODE);
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phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_VEND1_EXT_TS_MODE,
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TJA1120_TS_INSRT_MODE);
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG,
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PTP_ENABLE);
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}
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static void tja1120_ptp_enable(struct phy_device *phydev, bool enable)
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{
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if (enable)
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_PORT_FUNC_ENABLES,
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PTP_ENABLE);
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else
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phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_PORT_FUNC_ENABLES,
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PTP_ENABLE);
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}
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static const struct nxp_c45_regmap tja1120_regmap = {
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.vend1_ptp_clk_period = 0x1020,
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.vend1_event_msg_filt = 0x9010,
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.pps_enable =
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NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 4, 1),
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.pps_polarity =
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NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 5, 1),
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.ltc_lock_ctrl =
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NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 2, 1),
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.ltc_read =
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NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 1, 1),
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.ltc_write =
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NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 2, 1),
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.vend1_ltc_wr_nsec_0 = 0x1040,
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.vend1_ltc_wr_nsec_1 = 0x1041,
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.vend1_ltc_wr_sec_0 = 0x1042,
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.vend1_ltc_wr_sec_1 = 0x1043,
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.vend1_ltc_rd_nsec_0 = 0x1048,
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.vend1_ltc_rd_nsec_1 = 0x1049,
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.vend1_ltc_rd_sec_0 = 0x104A,
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.vend1_ltc_rd_sec_1 = 0x104B,
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.vend1_rate_adj_subns_0 = 0x1030,
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.vend1_rate_adj_subns_1 = 0x1031,
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.irq_egr_ts_en =
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NXP_C45_REG_FIELD(0x900A, MDIO_MMD_VEND1, 1, 1),
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.irq_egr_ts_status =
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NXP_C45_REG_FIELD(0x900C, MDIO_MMD_VEND1, 1, 1),
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.domain_number =
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NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 8, 8),
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.msg_type =
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NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 4, 4),
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.sequence_id =
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NXP_C45_REG_FIELD(0x9062, MDIO_MMD_VEND1, 0, 16),
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.sec_1_0 =
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NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 0, 2),
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.sec_4_2 =
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NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 2, 3),
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.nsec_15_0 =
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NXP_C45_REG_FIELD(0x9063, MDIO_MMD_VEND1, 0, 16),
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.nsec_29_16 =
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NXP_C45_REG_FIELD(0x9064, MDIO_MMD_VEND1, 0, 14),
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.vend1_ext_trg_data_0 = 0x1071,
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.vend1_ext_trg_data_1 = 0x1072,
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.vend1_ext_trg_data_2 = 0x1073,
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.vend1_ext_trg_data_3 = 0x1074,
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.vend1_ext_trg_ctrl = 0x1075,
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.cable_test = 0x8360,
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.cable_test_valid =
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NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 15, 1),
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.cable_test_result =
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NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 0, 3),
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};
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static const struct nxp_c45_phy_data tja1120_phy_data = {
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.regmap = &tja1120_regmap,
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.stats = tja1120_hw_stats,
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.n_stats = ARRAY_SIZE(tja1120_hw_stats),
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.ptp_clk_period = PTP_CLK_PERIOD_1000BT1,
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.counters_enable = tja1120_counters_enable,
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.ptp_init = tja1120_ptp_init,
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.ptp_enable = tja1120_ptp_enable,
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};
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static struct phy_driver nxp_c45_driver[] = {
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{
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PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103),
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@ -1536,12 +1670,37 @@ static struct phy_driver nxp_c45_driver[] = {
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.get_sqi_max = nxp_c45_get_sqi_max,
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.remove = nxp_c45_remove,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_TJA_1120),
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.name = "NXP C45 TJA1120",
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.get_features = nxp_c45_get_features,
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.driver_data = &tja1120_phy_data,
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.probe = nxp_c45_probe,
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.soft_reset = nxp_c45_soft_reset,
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.config_aneg = genphy_c45_config_aneg,
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.config_init = nxp_c45_config_init,
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.config_intr = nxp_c45_config_intr,
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.handle_interrupt = nxp_c45_handle_interrupt,
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.read_status = genphy_c45_read_status,
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.suspend = genphy_c45_pma_suspend,
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.resume = genphy_c45_pma_resume,
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.get_sset_count = nxp_c45_get_sset_count,
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.get_strings = nxp_c45_get_strings,
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.get_stats = nxp_c45_get_stats,
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.cable_test_start = nxp_c45_cable_test_start,
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.cable_test_get_status = nxp_c45_cable_test_get_status,
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.set_loopback = genphy_c45_loopback,
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.get_sqi = nxp_c45_get_sqi,
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.get_sqi_max = nxp_c45_get_sqi_max,
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.remove = nxp_c45_remove,
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},
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};
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module_phy_driver(nxp_c45_driver);
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static struct mdio_device_id __maybe_unused nxp_c45_tbl[] = {
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{ PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_TJA_1120) },
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{ /*sentinel*/ },
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};
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