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drm/i915: Stop using group access when progrmming icl combo phy TX
Program each TX lane individually so that we can start to use per-lane drive settings. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-8-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
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1 changed files with 16 additions and 12 deletions
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@ -1069,14 +1069,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
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intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
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/* Program PORT_TX_DW2 */
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val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
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val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
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RCOMP_SCALAR_MASK);
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val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
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val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
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/* Program Rcomp scalar for every table entry */
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val |= RCOMP_SCALAR(0x98);
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intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
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for (ln = 0; ln < 4; ln++) {
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val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
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val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
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RCOMP_SCALAR_MASK);
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val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
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val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
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/* Program Rcomp scalar for every table entry */
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val |= RCOMP_SCALAR(0x98);
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intel_de_write(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), val);
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}
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/* Program PORT_TX_DW4 */
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/* We cannot write to GRP. It would overwrite individual loadgen. */
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@ -1091,10 +1093,12 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
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}
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/* Program PORT_TX_DW7 */
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val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(0, phy));
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val &= ~N_SCALAR_MASK;
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val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
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intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
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for (ln = 0; ln < 4; ln++) {
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val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
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val &= ~N_SCALAR_MASK;
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val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
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intel_de_write(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), val);
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}
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}
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static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
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