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First round of amlogic DT binding clock update target for v5.5
Add the audio clock and reset bindings for the sm1 SoC family -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAl2cO+cACgkQ5vwPHDfy 2oXQug//cqVN9hhMgZv+an1DmZbJ2vt2lJvs9ddk2eNodlLC3wvz93YeNyqNn79p 11KNDBtgaorR5o41wfjHSlqZBqQQjhIPKdod/i5xzAJSi/0d6GzahrcUp6jXsE5o dzImQcGXzhhYpK21JXftq3OBqwEQrML5DgW+ab42IoV8CERCDSavpn/ZYP2RRqBY +5n1owpW+2f5xp2fkT5T/HGrDEdAbgM3lZEgM4w/2Tp9XpBxHDqbS7iDV7OLV+4/ Mb4zXwB9ra7u/bxEIPi4tpUaruZYfNFd5c3lWOd6nD+218UHo2pF0ZLlaNhw3Xdp 0M9Cyjy5hgqPDWTfmVKkKQKWXY7ys06rvLXowAfaob0SpHKV11QtPnmJYhsmDP60 vQTwi1ejfl/KsmNm6b6OTuRdflRCuDVueUuuX1xIFc30phnoqt99pvjz8GVSzqiX rx3QdYvhXbi0ioqSjdiu8KITBjdllsfPpO42qMsnU5wOWeOLQk9Ju42yK9IFwjSs C5aDeo9WEaUHYHJpI+KXdB38BFDEv2qvKz729t/tnenmgq0F+gy1CUPtwIe0rP8J GxK/KEEgCuwuwL/LcSb9iA7U2ycmDE0G6Kqoh0kTQd698CeIvPiLy9+yNP5HZeyT 2eUFGpKGSyZ25P5SAIHkQ2PSScjsQ5wemsf1jFuJgn/dngPEDkM= =XPSR -----END PGP SIGNATURE----- Merge tag 'clk-meson-dt-v5.5-1' of git://github.com/BayLibre/clk-meson into v5.5/dt64-redo First round of amlogic DT binding clock update target for v5.5 Add the audio clock and reset bindings for the sm1 SoC family * tag 'clk-meson-dt-v5.5-1' of git://github.com/BayLibre/clk-meson: dt-bindings: clock: meson: add sm1 resets to the axg-audio controller dt-bindings: clk: axg-audio: add sm1 bindings
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commit
f21ab7906d
3 changed files with 27 additions and 1 deletions
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@ -7,7 +7,8 @@ devices.
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Required Properties:
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
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"amlogic,g12a-audio-clkc" for G12A.
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"amlogic,g12a-audio-clkc" for G12A,
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"amlogic,sm1-audio-clkc" for S905X3.
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- reg : physical base address of the clock controller and length of
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memory mapped region.
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- clocks : a list of phandle + clock-specifier pairs for the clocks listed
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@ -80,5 +80,15 @@
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#define AUD_CLKID_TDM_SCLK_PAD0 160
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#define AUD_CLKID_TDM_SCLK_PAD1 161
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#define AUD_CLKID_TDM_SCLK_PAD2 162
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#define AUD_CLKID_TOP 163
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#define AUD_CLKID_TORAM 164
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#define AUD_CLKID_EQDRC 165
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#define AUD_CLKID_RESAMPLE_B 166
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#define AUD_CLKID_TOVAD 167
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#define AUD_CLKID_LOCKER 168
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#define AUD_CLKID_SPDIFIN_LB 169
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#define AUD_CLKID_FRDDR_D 170
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#define AUD_CLKID_TODDR_D 171
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#define AUD_CLKID_LOOPBACK_B 172
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#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
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@ -35,4 +35,19 @@
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#define AUD_RESET_TOHDMITX 24
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#define AUD_RESET_CLKTREE 25
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/* SM1 added resets */
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#define AUD_RESET_RESAMPLE_B 26
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#define AUD_RESET_TOVAD 27
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#define AUD_RESET_LOCKER 28
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#define AUD_RESET_SPDIFIN_LB 29
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#define AUD_RESET_FRATV 30
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#define AUD_RESET_FRHDMIRX 31
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#define AUD_RESET_FRDDR_D 32
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#define AUD_RESET_TODDR_D 33
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#define AUD_RESET_LOOPBACK_B 34
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#define AUD_RESET_EARCTX 35
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#define AUD_RESET_EARCRX 36
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#define AUD_RESET_FRDDR_E 37
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#define AUD_RESET_TODDR_E 38
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#endif
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