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clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
Various MSDC core clocks, used for multiple MSDC controller instances, share the same parent(s): in order to add parents selection in the mtk-sd driver to achieve an accurate clock rate for all modes, remove the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this will make sure that a clk_set_rate() call performed for a clock on a secondary controller will not change the rate of a common parent, which would result in an overclock or underclock of one of the controllers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20230516135205.372951-3-angelogioacchino.delregno@collabora.com Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
Stephen Boyd
parent
1775790eff
commit
f235f6ae59
11 changed files with 93 additions and 92 deletions
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@ -406,15 +406,15 @@ static const struct mtk_mux top_muxes[] = {
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CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
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CLK_CFG_UPDATE, 11),
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/* CLK_CFG_3 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
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msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
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CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
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CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
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msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
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CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
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CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
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msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
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CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),
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CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14, 0),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
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CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
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24, 2, 31, CLK_CFG_UPDATE, 15),
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@ -687,16 +687,16 @@ static const struct mtk_mux top_muxes[] = {
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0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
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0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
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msdc50_hclk_parents, 0x70, 0x74, 0x78,
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16, 2, 23, 0x004, 22),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
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msdc50_0_parents, 0x70, 0x74, 0x78,
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24, 3, 31, 0x004, 23),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
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msdc50_hclk_parents, 0x70, 0x74, 0x78,
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16, 2, 23, 0x004, 22, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel",
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msdc50_0_parents, 0x70, 0x74, 0x78,
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24, 3, 31, 0x004, 23, 0),
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/* CLK_CFG_6 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
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msdc30_1_parents, 0x80, 0x84, 0x88,
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0, 3, 7, 0x004, 24),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "msdc30_1_sel",
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msdc30_1_parents, 0x80, 0x84, 0x88,
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0, 3, 7, 0x004, 24, 0),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
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0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
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@ -310,12 +310,12 @@ static const struct mtk_mux top_muxes[] = {
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pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
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0x1C0, 7),
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/* CLK_CFG_2 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
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emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
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0x1C0, 8),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
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emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
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0x1C0, 9),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
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emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
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0x1C0, 8, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
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emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
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0x1C0, 9, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
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csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
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0x1C0, 10,
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@ -193,12 +193,12 @@ static const struct mtk_mux top_muxes[] = {
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pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
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31, 0x1C0, 7),
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/* CLK_CFG_2 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
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emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
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0x1C0, 8),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
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emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
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0x1C0, 9),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
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emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
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0x1C0, 8, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
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emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
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0x1C0, 9, 0),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
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f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
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0x1C0, 10),
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@ -547,17 +547,17 @@ static const struct mtk_composite top_muxes[] = {
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MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
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/* CLK_CFG_3 */
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MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
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MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
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0x0070, 8, 3, 15),
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MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,
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0x0070, 16, 4, 23),
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MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
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0x0070, 24, 3, 31),
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MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
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0x0070, 8, 3, 15, 0),
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MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,
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0x0070, 16, 4, 23, 0),
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MUX_GATE_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
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0x0070, 24, 3, 31, 0),
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/* CLK_CFG_4 */
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MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,
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0x0080, 0, 3, 7),
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MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
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0x0080, 8, 4, 15),
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MUX_GATE_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,
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0x0080, 0, 3, 7, 0),
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MUX_GATE_FLAGS(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
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0x0080, 8, 4, 15, 0),
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MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
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0x0080, 16, 2, 23),
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MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
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@ -595,8 +595,8 @@ static const struct mtk_composite top_muxes[] = {
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MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents,
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0x00c0, 24, 3, 31),
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/* CLK_CFG_13 */
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MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,
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0x00d0, 0, 3, 7),
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MUX_GATE_FLAGS(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,
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0x00d0, 0, 3, 7, 0),
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MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
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MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents,
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0x00d0, 16, 2, 23),
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@ -487,14 +487,14 @@ static const struct mtk_mux top_muxes[] = {
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
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spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15),
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/* CLK_CFG_4 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
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msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
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msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
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msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
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msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
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msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
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msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
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msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
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msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19, 0),
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/* CLK_CFG_5 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
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audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20),
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@ -531,12 +531,12 @@ static const struct mtk_mux top_mtk_muxes[] = {
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MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
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spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11),
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/* CLK_CFG_3 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
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msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
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msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
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msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
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msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
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msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
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msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14, 0),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO, "top_audio",
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audio_parents, 0x0070, 0x0074, 0x0078, 24, 2, 31, 0x0004, 15),
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/* CLK_CFG_4 */
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@ -1015,15 +1015,15 @@ static const struct mtk_mux top_mtk_muxes[] = {
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uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
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spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
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msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
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msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
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msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
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msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27, 0),
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/* CLK_CFG_7 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
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msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
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msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
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msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
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msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29, 0),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
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intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
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@ -601,15 +601,16 @@ static const struct mtk_mux top_mtk_muxes[] = {
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uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
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spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
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msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
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msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2,
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31, 0x004, 27, 0),
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/* CLK_CFG_7 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
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msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
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msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
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msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
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msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
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msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29, 0),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
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msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30, 0),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
|
||||
audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
|
||||
/* CLK_CFG_8 */
|
||||
|
|
|
|||
|
|
@ -930,15 +930,15 @@ static const struct mtk_mux top_mtk_muxes[] = {
|
|||
/* CLK_CFG_7 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
|
||||
spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
|
||||
msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
|
||||
msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
|
||||
msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
|
||||
msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
|
||||
msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
|
||||
msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31, 0),
|
||||
/* CLK_CFG_8 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
|
||||
msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
|
||||
msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0, 0),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
|
||||
intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
|
||||
|
|
|
|||
|
|
@ -431,22 +431,22 @@ static const struct mtk_mux top_muxes[] = {
|
|||
0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
|
||||
0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel",
|
||||
msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2,
|
||||
23, CLK_CFG_UPDATE, 10),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel",
|
||||
msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2,
|
||||
31, CLK_CFG_UPDATE, 11),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel",
|
||||
msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2,
|
||||
23, CLK_CFG_UPDATE, 10, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel",
|
||||
msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2,
|
||||
31, CLK_CFG_UPDATE, 11, 0),
|
||||
/* CLK_CFG_3 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
|
||||
msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7,
|
||||
CLK_CFG_UPDATE, 12),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel",
|
||||
msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15,
|
||||
CLK_CFG_UPDATE, 13),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
|
||||
msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23,
|
||||
CLK_CFG_UPDATE, 14),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
|
||||
msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7,
|
||||
CLK_CFG_UPDATE, 12, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel",
|
||||
msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15,
|
||||
CLK_CFG_UPDATE, 13, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
|
||||
msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23,
|
||||
CLK_CFG_UPDATE, 14, 0),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
|
||||
0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE,
|
||||
15),
|
||||
|
|
|
|||
Loading…
Reference in a new issue