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ARM: dts: ixp4xx: Add a devicetree for Freecom FSG-3
This adds a devicetree for the Freecom FSG-3, a combined router and NAS. Cc: Rod Whitby <rod@whitby.id.au> Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -242,6 +242,7 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \
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dtb-$(CONFIG_ARCH_IXP4XX) += \
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intel-ixp42x-linksys-nslu2.dtb \
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intel-ixp42x-linksys-wrv54g.dtb \
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intel-ixp42x-freecom-fsg-3.dtb \
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intel-ixp42x-welltech-epbx100.dtb \
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intel-ixp42x-ixdp425.dtb \
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intel-ixp43x-kixrp435.dtb \
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158
arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
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158
arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts
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@ -0,0 +1,158 @@
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for the Freecom FSG-3 router.
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* This machine is based on IXP425.
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* This device tree is inspired by the board file by Rod Whitby.
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*/
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/dts-v1/;
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#include "intel-ixp42x.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Freecom FSG-3";
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compatible = "freecom,fsg-3", "intel,ixp42x";
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#address-cells = <1>;
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#size-cells = <1>;
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memory@0 {
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/* 64 MB memory */
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device_type = "memory";
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reg = <0x00000000 0x4000000>;
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};
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chosen {
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/* Boot from the first partition on the hard drive */
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bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
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stdout-path = "uart0:115200n8";
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};
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aliases {
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serial0 = &uart0;
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};
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gpio_keys {
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compatible = "gpio-keys";
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button-sync {
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wakeup-source;
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/* Closest approximation of what the key should do */
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linux,code = <KEY_CONNECT>;
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label = "sync";
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gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
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};
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button-reset {
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wakeup-source;
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linux,code = <KEY_ESC>;
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label = "reset";
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gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
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};
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button-usb {
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wakeup-source;
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/* Unplug USB, closest approximation of what the key should do */
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linux,code = <KEY_EJECTCD>;
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label = "usb";
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gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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};
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};
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i2c {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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hwmon@28 {
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/*
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* Temperature sensor and fan control chip.
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*
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* TODO: create a proper device tree binding for
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* the sensor and temperature zone and create a
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* zone with fan control.
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*/
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compatible = "winbond,w83781d";
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reg = <0x28>;
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};
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rtc@6f {
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compatible = "isil,isl1208";
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reg = <0x6f>;
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};
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};
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/* Enable writes on the expansion bus */
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intel,ixp4xx-eb-write-enable = <1>;
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/* 4 MB of Flash mapped in at CS0 */
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reg = <0 0x00000000 0x400000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x3e0000 */
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fis-index-block = <0x1f>;
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};
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};
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};
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pci@c0000000 {
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status = "ok";
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/*
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* Written based on the FSG-3 PCI boardfile.
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* We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
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*/
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interrupt-map =
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/* IDSEL 12 */
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<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
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<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
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<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
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<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
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/* IDSEL 13 */
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<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
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<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
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<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
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<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
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/* IDSEL 14 */
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<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
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<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
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<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
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<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
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};
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/* EthB */
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ethernet@c8009000 {
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status = "ok";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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};
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};
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};
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/* EthC */
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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phy-mode = "rgmii";
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phy-handle = <&phy4>;
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};
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};
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};
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