mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 02:39:48 +00:00
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (28 commits) [MIPS] Rework cobalt_board_id [MIPS] Use RTC_CMOS for Cobalt [MIPS] Use platform_device for Cobalt UART [MIPS] Separate Alchemy processor based boards config [MIPS] Fix build error in atomic64_cmpxchg [MIPS] Run checksyscalls for N32 and O32 ABI [MIPS] tlbex: use __maybe_unused [MIPS] excite: use __maybe_unused [MIPS] Add extern cobalt_board_id [MIPS] Remove unused CONFIG_TOSHIBA_BOARDS [MIPS] Rename tb0229_defconfig to tb0219_defconfig [MIPS] Update tb0229_defconfig; add CONFIG_GPIO_TB0219. [MIPS] Add minimum defconfig for RBHMA4200 [MIPS] SB1: Build fix. [MIPS] Drop __devinit tag from allocate_irqno() and free_irqno() [MIPS] clocksource: use CLOCKSOURCE_MASK() macro [MIPS] Remove LIMITED_DMA support [MIPS] Remove Momenco Jaguar ATX support [MIPS] Remove Momenco Ocelot G support [MIPS] FPU hazard handling ...
This commit is contained in:
commit
f2c60ed038
71 changed files with 686 additions and 4082 deletions
|
@ -1,54 +0,0 @@
|
|||
|
||||
Pete Popov, ppopov@pacbell.net
|
||||
07/11/2001
|
||||
|
||||
This README briefly explains how to use the pci and pci_auto
|
||||
code in arch/mips/kernel. The code was ported from PowerPC and
|
||||
modified slightly. It has been tested pretty well on PPC on some
|
||||
rather complex systems with multiple bridges and devices behind
|
||||
each bridge. However, at the time this README was written, the
|
||||
mips port was tested only on boards with a single pci bus and
|
||||
no P2P bridges. It's very possible that on boards with P2P
|
||||
bridges some modifications have to be made. The code will
|
||||
evolve, no doubt, but currently every single mips board
|
||||
is doing its own pcibios thing and it has become a big
|
||||
mess. This generic pci code is meant to clean up the mips
|
||||
pci mess and make it easier to add pci support to new boards.
|
||||
|
||||
inside the define for your board in arch/mips/config.in.
|
||||
For example, the Galileo EV96100 board looks like this:
|
||||
|
||||
if [ "$CONFIG_MIPS_EV96100" = "y" ]; then
|
||||
define_bool CONFIG_PCI y
|
||||
define_bool CONFIG_MIPS_GT96100 y
|
||||
define_bool CONFIG_NEW_PCI y
|
||||
define_bool CONFIG_SWAP_IO_SPACE y
|
||||
fi
|
||||
|
||||
|
||||
Next, if you want to use the arch/mips/kernel/pci code, which has the
|
||||
pcibios_init() function, add
|
||||
|
||||
define_bool CONFIG_NEW_PCI y
|
||||
|
||||
inside the define for your board. Again, the EV96100 example above
|
||||
show NEW_PCI turned on.
|
||||
|
||||
|
||||
Now you need to add your files to hook in your pci configuration
|
||||
cycles. Usually you'll need only a couple of files named something
|
||||
like pci_fixups.c and pci_ops.c. You can copy the templates
|
||||
provided and fill in the code.
|
||||
|
||||
The file pci_ops.c should contain the pci configuration cycles routines.
|
||||
It also has the mips_pci_channels[] array which contains the descriptors
|
||||
of each pci controller.
|
||||
|
||||
The file pci_fixups.c contains a few routines to do interrupt fixups,
|
||||
resources fixups, and, if needed, pci bios fixups.
|
||||
|
||||
Usually you'll put your pci_fixups.c file in your board specific directory,
|
||||
since the functions in that file are board specific. The functions in
|
||||
pci_ops.c, on the other hand, are usually pci controller specific so that
|
||||
file could be shared among a few different boards using the same
|
||||
pci controller.
|
|
@ -15,121 +15,8 @@ choice
|
|||
prompt "System type"
|
||||
default SGI_IP22
|
||||
|
||||
config MIPS_MTX1
|
||||
bool "4G Systems MTX-1 board"
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SOC_AU1500
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_BOSPORUS
|
||||
bool "AMD Alchemy Bosporus board"
|
||||
select SOC_AU1500
|
||||
select DMA_NONCOHERENT
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1000
|
||||
bool "AMD Alchemy PB1000 board"
|
||||
select SOC_AU1000
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1100
|
||||
bool "AMD Alchemy PB1100 board"
|
||||
select SOC_AU1100
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1500
|
||||
bool "AMD Alchemy PB1500 board"
|
||||
select SOC_AU1500
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1550
|
||||
bool "AMD Alchemy PB1550 board"
|
||||
select SOC_AU1550
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1200
|
||||
bool "AMD Alchemy PB1200 board"
|
||||
select SOC_AU1200
|
||||
select DMA_NONCOHERENT
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1000
|
||||
bool "AMD Alchemy DB1000 board"
|
||||
select SOC_AU1000
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1100
|
||||
bool "AMD Alchemy DB1100 board"
|
||||
select SOC_AU1100
|
||||
select DMA_NONCOHERENT
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1500
|
||||
bool "AMD Alchemy DB1500 board"
|
||||
select SOC_AU1500
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1550
|
||||
bool "AMD Alchemy DB1550 board"
|
||||
select SOC_AU1550
|
||||
select HW_HAS_PCI
|
||||
select DMA_NONCOHERENT
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1200
|
||||
bool "AMD Alchemy DB1200 board"
|
||||
select SOC_AU1200
|
||||
select DMA_COHERENT
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_MIRAGE
|
||||
bool "AMD Alchemy Mirage board"
|
||||
select DMA_NONCOHERENT
|
||||
select SOC_AU1500
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
config MACH_ALCHEMY
|
||||
bool "Alchemy processor based machines"
|
||||
|
||||
config BASLER_EXCITE
|
||||
bool "Basler eXcite smart camera"
|
||||
|
@ -369,28 +256,6 @@ config MIPS_SIM
|
|||
This option enables support for MIPS Technologies MIPSsim software
|
||||
emulator.
|
||||
|
||||
config MOMENCO_JAGUAR_ATX
|
||||
bool "Momentum Jaguar board"
|
||||
select BOOT_ELF32
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select IRQ_CPU_RM7K
|
||||
select IRQ_MV64340
|
||||
select LIMITED_DMA
|
||||
select PCI_MARVELL
|
||||
select RM7000_CPU_SCACHE
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_HAS_CPU_RM9000
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_64BIT_KERNEL
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_KGDB
|
||||
help
|
||||
The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
|
||||
Momentum Computer <http://www.momenco.com/>.
|
||||
|
||||
config MOMENCO_OCELOT
|
||||
bool "Momentum Ocelot board"
|
||||
select DMA_NONCOHERENT
|
||||
|
@ -446,29 +311,6 @@ config MOMENCO_OCELOT_C
|
|||
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
|
||||
Momentum Computer <http://www.momenco.com/>.
|
||||
|
||||
config MOMENCO_OCELOT_G
|
||||
bool "Momentum Ocelot-G board"
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select IRQ_CPU_RM7K
|
||||
select PCI_MARVELL
|
||||
select RM7000_CPU_SCACHE
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_HAS_CPU_RM7000
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
help
|
||||
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
|
||||
Momentum Computer <http://www.momenco.com/>.
|
||||
|
||||
config MIPS_XXS1500
|
||||
bool "MyCable XXS1500 board"
|
||||
select DMA_NONCOHERENT
|
||||
select SOC_AU1500
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config PNX8550_JBS
|
||||
bool "Philips PNX8550 based JBS board"
|
||||
select PNX8550
|
||||
|
@ -775,7 +617,6 @@ config TOSHIBA_JMR3927
|
|||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select TOSHIBA_BOARDS
|
||||
select GENERIC_HARDIRQS_NO__DO_IRQ
|
||||
|
||||
config TOSHIBA_RBTX4927
|
||||
|
@ -791,7 +632,6 @@ config TOSHIBA_RBTX4927
|
|||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_KGDB
|
||||
select TOSHIBA_BOARDS
|
||||
select GENERIC_HARDIRQS_NO__DO_IRQ
|
||||
help
|
||||
This Toshiba board is based on the TX4927 processor. Say Y here to
|
||||
|
@ -811,7 +651,6 @@ config TOSHIBA_RBTX4938
|
|||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_KGDB
|
||||
select TOSHIBA_BOARDS
|
||||
select GENERIC_HARDIRQS_NO__DO_IRQ
|
||||
help
|
||||
This Toshiba board is based on the TX4938 processor. Say Y here to
|
||||
|
@ -819,11 +658,11 @@ config TOSHIBA_RBTX4938
|
|||
|
||||
endchoice
|
||||
|
||||
source "arch/mips/au1000/Kconfig"
|
||||
source "arch/mips/ddb5xxx/Kconfig"
|
||||
source "arch/mips/gt64120/ev64120/Kconfig"
|
||||
source "arch/mips/jazz/Kconfig"
|
||||
source "arch/mips/lasat/Kconfig"
|
||||
source "arch/mips/momentum/Kconfig"
|
||||
source "arch/mips/pmc-sierra/Kconfig"
|
||||
source "arch/mips/sgi-ip27/Kconfig"
|
||||
source "arch/mips/sibyte/Kconfig"
|
||||
|
@ -923,11 +762,6 @@ config GENERIC_ISA_DMA
|
|||
config I8259
|
||||
bool
|
||||
|
||||
config LIMITED_DMA
|
||||
bool
|
||||
select HIGHMEM
|
||||
select SYS_SUPPORTS_HIGHMEM
|
||||
|
||||
config MIPS_BONITO64
|
||||
bool
|
||||
|
||||
|
@ -1013,33 +847,6 @@ config MIPS_RM9122
|
|||
config PCI_MARVELL
|
||||
bool
|
||||
|
||||
config SOC_AU1000
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1100
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1500
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1550
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1200
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1X00
|
||||
bool
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_APM_EMULATION
|
||||
select SYS_SUPPORTS_KGDB
|
||||
|
||||
config SERIAL_RM9000
|
||||
bool
|
||||
|
||||
|
@ -1081,9 +888,9 @@ config WDT_RM9000
|
|||
choice
|
||||
prompt "Galileo Chip Clock"
|
||||
#default SYSCLK_83 if MIPS_EV64120
|
||||
depends on MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G
|
||||
depends on MIPS_EV64120 || MOMENCO_OCELOT
|
||||
default SYSCLK_83 if MIPS_EV64120
|
||||
default SYSCLK_100 if MOMENCO_OCELOT || MOMENCO_OCELOT_G
|
||||
default SYSCLK_100 if MOMENCO_OCELOT
|
||||
|
||||
config SYSCLK_75
|
||||
bool "75" if MIPS_EV64120
|
||||
|
@ -1092,7 +899,7 @@ config SYSCLK_83
|
|||
bool "83.3" if MIPS_EV64120
|
||||
|
||||
config SYSCLK_100
|
||||
bool "100" if MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G
|
||||
bool "100" if MIPS_EV64120 || MOMENCO_OCELOT
|
||||
|
||||
endchoice
|
||||
|
||||
|
@ -1131,9 +938,6 @@ config ARC64
|
|||
config BOOT_ELF64
|
||||
bool
|
||||
|
||||
config TOSHIBA_BOARDS
|
||||
bool
|
||||
|
||||
menu "CPU selection"
|
||||
|
||||
choice
|
||||
|
@ -1557,6 +1361,7 @@ config MIPS_MT_SMP
|
|||
bool "Use 1 TC on each available VPE for SMP"
|
||||
depends on SYS_SUPPORTS_MULTITHREADING
|
||||
select CPU_MIPSR2_IRQ_VI
|
||||
select CPU_MIPSR2_IRQ_EI
|
||||
select CPU_MIPSR2_SRS
|
||||
select MIPS_MT
|
||||
select NR_CPUS_DEFAULT_2
|
||||
|
@ -1572,6 +1377,7 @@ config MIPS_MT_SMTC
|
|||
#depends on CPU_MIPS64_R2 # once there is hardware ...
|
||||
depends on SYS_SUPPORTS_MULTITHREADING
|
||||
select CPU_MIPSR2_IRQ_VI
|
||||
select CPU_MIPSR2_IRQ_EI
|
||||
select CPU_MIPSR2_SRS
|
||||
select MIPS_MT
|
||||
select NR_CPUS_DEFAULT_8
|
||||
|
@ -1584,6 +1390,8 @@ config MIPS_MT_SMTC
|
|||
config MIPS_VPE_LOADER
|
||||
bool "VPE loader support."
|
||||
depends on SYS_SUPPORTS_MULTITHREADING
|
||||
select CPU_MIPSR2_IRQ_VI
|
||||
select CPU_MIPSR2_IRQ_EI
|
||||
select MIPS_MT
|
||||
help
|
||||
Includes a loader for loading an elf relocatable object
|
||||
|
|
|
@ -342,15 +342,6 @@ core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \
|
|||
cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot
|
||||
load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000
|
||||
|
||||
#
|
||||
# Momentum Ocelot-G board
|
||||
#
|
||||
# The Ocelot-G setup.o must be linked early - it does the ioremap() for the
|
||||
# mips_io_port_base.
|
||||
#
|
||||
core-$(CONFIG_MOMENCO_OCELOT_G) += arch/mips/momentum/ocelot_g/
|
||||
load-$(CONFIG_MOMENCO_OCELOT_G) += 0xffffffff80100000
|
||||
|
||||
#
|
||||
# Momentum Ocelot-C and -CS boards
|
||||
#
|
||||
|
@ -387,17 +378,6 @@ core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
|
|||
cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
|
||||
load-$(CONFIG_BASLER_EXCITE) += 0x80100000
|
||||
|
||||
#
|
||||
# Momentum Jaguar ATX
|
||||
#
|
||||
core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/
|
||||
cflags-$(CONFIG_MOMENCO_JAGUAR_ATX) += -Iinclude/asm-mips/mach-ja
|
||||
#ifdef CONFIG_JAGUAR_DMALOW
|
||||
#load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff88000000
|
||||
#else
|
||||
load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000
|
||||
#endif
|
||||
|
||||
#
|
||||
# NEC DDB
|
||||
#
|
||||
|
@ -729,3 +709,25 @@ archclean:
|
|||
CLEAN_FILES += vmlinux.32 \
|
||||
vmlinux.64 \
|
||||
vmlinux.ecoff
|
||||
|
||||
quiet_cmd_syscalls_n32 = CALL-N32 $<
|
||||
cmd_syscalls_n32 = $(CONFIG_SHELL) $< $(CC) $(c_flags) -mabi=n32
|
||||
|
||||
quiet_cmd_syscalls_o32 = CALL-O32 $<
|
||||
cmd_syscalls_o32 = $(CONFIG_SHELL) $< $(CC) $(c_flags) -mabi=32
|
||||
|
||||
PHONY += missing-syscalls-n32 missing-syscalls-o32
|
||||
|
||||
missing-syscalls-n32: scripts/checksyscalls.sh FORCE
|
||||
$(call cmd,syscalls_n32)
|
||||
|
||||
missing-syscalls-o32: scripts/checksyscalls.sh FORCE
|
||||
$(call cmd,syscalls_o32)
|
||||
|
||||
archprepare:
|
||||
ifdef CONFIG_MIPS32_N32
|
||||
$(Q)$(MAKE) $(build)=arch/mips missing-syscalls-n32
|
||||
endif
|
||||
ifdef CONFIG_MIPS32_O32
|
||||
$(Q)$(MAKE) $(build)=arch/mips missing-syscalls-o32
|
||||
endif
|
||||
|
|
142
arch/mips/au1000/Kconfig
Normal file
142
arch/mips/au1000/Kconfig
Normal file
|
@ -0,0 +1,142 @@
|
|||
choice
|
||||
prompt "Machine type"
|
||||
depends on MACH_ALCHEMY
|
||||
default MIPS_DB1000
|
||||
|
||||
config MIPS_MTX1
|
||||
bool "4G Systems MTX-1 board"
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SOC_AU1500
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_BOSPORUS
|
||||
bool "Alchemy Bosporus board"
|
||||
select SOC_AU1500
|
||||
select DMA_NONCOHERENT
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1000
|
||||
bool "Alchemy DB1000 board"
|
||||
select SOC_AU1000
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1100
|
||||
bool "Alchemy DB1100 board"
|
||||
select SOC_AU1100
|
||||
select DMA_NONCOHERENT
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1200
|
||||
bool "Alchemy DB1200 board"
|
||||
select SOC_AU1200
|
||||
select DMA_COHERENT
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1500
|
||||
bool "Alchemy DB1500 board"
|
||||
select SOC_AU1500
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_DB1550
|
||||
bool "Alchemy DB1550 board"
|
||||
select SOC_AU1550
|
||||
select HW_HAS_PCI
|
||||
select DMA_NONCOHERENT
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_MIRAGE
|
||||
bool "Alchemy Mirage board"
|
||||
select DMA_NONCOHERENT
|
||||
select SOC_AU1500
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1000
|
||||
bool "Alchemy PB1000 board"
|
||||
select SOC_AU1000
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1100
|
||||
bool "Alchemy PB1100 board"
|
||||
select SOC_AU1100
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1200
|
||||
bool "Alchemy PB1200 board"
|
||||
select SOC_AU1200
|
||||
select DMA_NONCOHERENT
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1500
|
||||
bool "Alchemy PB1500 board"
|
||||
select SOC_AU1500
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_PB1550
|
||||
bool "Alchemy PB1550 board"
|
||||
select SOC_AU1550
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select MIPS_DISABLE_OBSOLETE_IDE
|
||||
select RESOURCES_64BIT if PCI
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MIPS_XXS1500
|
||||
bool "MyCable XXS1500 board"
|
||||
select DMA_NONCOHERENT
|
||||
select SOC_AU1500
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
endchoice
|
||||
|
||||
config SOC_AU1000
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1100
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1500
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1550
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1200
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
|
||||
config SOC_AU1X00
|
||||
bool
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_APM_EMULATION
|
||||
select SYS_SUPPORTS_KGDB
|
|
@ -68,7 +68,7 @@ enum {
|
|||
|
||||
|
||||
static struct resource
|
||||
excite_ctr_resource __attribute__((unused)) = {
|
||||
excite_ctr_resource __maybe_unused = {
|
||||
.name = "GPI counters",
|
||||
.start = 0,
|
||||
.end = 5,
|
||||
|
@ -77,7 +77,7 @@ static struct resource
|
|||
.sibling = NULL,
|
||||
.child = NULL
|
||||
},
|
||||
excite_gpislice_resource __attribute__((unused)) = {
|
||||
excite_gpislice_resource __maybe_unused = {
|
||||
.name = "GPI slices",
|
||||
.start = 0,
|
||||
.end = 1,
|
||||
|
@ -86,7 +86,7 @@ static struct resource
|
|||
.sibling = NULL,
|
||||
.child = NULL
|
||||
},
|
||||
excite_mdio_channel_resource __attribute__((unused)) = {
|
||||
excite_mdio_channel_resource __maybe_unused = {
|
||||
.name = "MDIO channels",
|
||||
.start = 0,
|
||||
.end = 1,
|
||||
|
@ -95,7 +95,7 @@ static struct resource
|
|||
.sibling = NULL,
|
||||
.child = NULL
|
||||
},
|
||||
excite_fifomem_resource __attribute__((unused)) = {
|
||||
excite_fifomem_resource __maybe_unused = {
|
||||
.name = "FIFO memory",
|
||||
.start = 0,
|
||||
.end = 767,
|
||||
|
@ -104,7 +104,7 @@ static struct resource
|
|||
.sibling = NULL,
|
||||
.child = NULL
|
||||
},
|
||||
excite_scram_resource __attribute__((unused)) = {
|
||||
excite_scram_resource __maybe_unused = {
|
||||
.name = "Scratch RAM",
|
||||
.start = EXCITE_PHYS_SCRAM,
|
||||
.end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
|
||||
|
@ -113,7 +113,7 @@ static struct resource
|
|||
.sibling = NULL,
|
||||
.child = NULL
|
||||
},
|
||||
excite_fpga_resource __attribute__((unused)) = {
|
||||
excite_fpga_resource __maybe_unused = {
|
||||
.name = "System FPGA",
|
||||
.start = EXCITE_PHYS_FPGA,
|
||||
.end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
|
||||
|
@ -122,7 +122,7 @@ static struct resource
|
|||
.sibling = NULL,
|
||||
.child = NULL
|
||||
},
|
||||
excite_nand_resource __attribute__((unused)) = {
|
||||
excite_nand_resource __maybe_unused = {
|
||||
.name = "NAND flash control",
|
||||
.start = EXCITE_PHYS_NAND,
|
||||
.end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
|
||||
|
@ -131,7 +131,7 @@ static struct resource
|
|||
.sibling = NULL,
|
||||
.child = NULL
|
||||
},
|
||||
excite_titan_resource __attribute__((unused)) = {
|
||||
excite_titan_resource __maybe_unused = {
|
||||
.name = "TITAN registers",
|
||||
.start = EXCITE_PHYS_TITAN,
|
||||
.end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
# Makefile for the Cobalt micro systems family specific parts of the kernel
|
||||
#
|
||||
|
||||
obj-y := irq.o reset.o setup.o buttons.o
|
||||
obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o
|
||||
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += console.o
|
||||
|
|
63
arch/mips/cobalt/rtc.c
Normal file
63
arch/mips/cobalt/rtc.c
Normal file
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Registration of Cobalt RTC platform device.
|
||||
*
|
||||
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
static struct resource cobalt_rtc_resource[] __initdata = {
|
||||
{
|
||||
.start = 0x70,
|
||||
.end = 0x77,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
{
|
||||
.start = 8,
|
||||
.end = 8,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static __init int cobalt_rtc_add(void)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
int retval;
|
||||
|
||||
pdev = platform_device_alloc("rtc_cmos", -1);
|
||||
if (!pdev)
|
||||
return -ENOMEM;
|
||||
|
||||
retval = platform_device_add_resources(pdev, cobalt_rtc_resource,
|
||||
ARRAY_SIZE(cobalt_rtc_resource));
|
||||
if (retval)
|
||||
goto err_free_device;
|
||||
|
||||
retval = platform_device_add(pdev);
|
||||
if (retval)
|
||||
goto err_free_device;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_device:
|
||||
platform_device_put(pdev);
|
||||
|
||||
return retval;
|
||||
}
|
||||
device_initcall(cobalt_rtc_add);
|
85
arch/mips/cobalt/serial.c
Normal file
85
arch/mips/cobalt/serial.c
Normal file
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Registration of Cobalt UART platform device.
|
||||
*
|
||||
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_8250.h>
|
||||
|
||||
#include <cobalt.h>
|
||||
|
||||
static struct resource cobalt_uart_resource[] __initdata = {
|
||||
{
|
||||
.start = 0x1c800000,
|
||||
.end = 0x1c800007,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = COBALT_SERIAL_IRQ,
|
||||
.end = COBALT_SERIAL_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_serial8250_port cobalt_serial8250_port[] = {
|
||||
{
|
||||
.irq = COBALT_SERIAL_IRQ,
|
||||
.uartclk = 18432000,
|
||||
.iotype = UPIO_MEM,
|
||||
.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
|
||||
.mapbase = 0x1c800000,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
static __init int cobalt_uart_add(void)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
int retval;
|
||||
|
||||
/*
|
||||
* Cobalt Qube1 and RAQ1 have no UART.
|
||||
*/
|
||||
if (cobalt_board_id <= COBALT_BRD_ID_RAQ1)
|
||||
return 0;
|
||||
|
||||
pdev = platform_device_alloc("serial8250", -1);
|
||||
if (!pdev)
|
||||
return -ENOMEM;
|
||||
|
||||
pdev->id = PLAT8250_DEV_PLATFORM;
|
||||
pdev->dev.platform_data = cobalt_serial8250_port;
|
||||
|
||||
retval = platform_device_add_resources(pdev, cobalt_uart_resource, ARRAY_SIZE(cobalt_uart_resource));
|
||||
if (retval)
|
||||
goto err_free_device;
|
||||
|
||||
retval = platform_device_add(pdev);
|
||||
if (retval)
|
||||
goto err_free_device;
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_device:
|
||||
platform_device_put(pdev);
|
||||
|
||||
return retval;
|
||||
}
|
||||
device_initcall(cobalt_uart_add);
|
|
@ -10,11 +10,8 @@
|
|||
*
|
||||
*/
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/time.h>
|
||||
|
@ -27,9 +24,6 @@
|
|||
extern void cobalt_machine_restart(char *command);
|
||||
extern void cobalt_machine_halt(void);
|
||||
extern void cobalt_machine_power_off(void);
|
||||
extern void cobalt_early_console(void);
|
||||
|
||||
int cobalt_board_id;
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
|
@ -95,8 +89,6 @@ static struct resource cobalt_reserved_resources[] = {
|
|||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
static struct uart_port uart;
|
||||
unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
|
||||
int i;
|
||||
|
||||
_machine_restart = cobalt_machine_restart;
|
||||
|
@ -111,29 +103,6 @@ void __init plat_mem_setup(void)
|
|||
/* These resources have been reserved by VIA SuperI/O chip. */
|
||||
for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
|
||||
request_resource(&ioport_resource, cobalt_reserved_resources + i);
|
||||
|
||||
/* Read the cobalt id register out of the PCI config space */
|
||||
PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
|
||||
cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
|
||||
cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
|
||||
cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
|
||||
|
||||
printk("Cobalt board ID: %d\n", cobalt_board_id);
|
||||
|
||||
if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
|
||||
#ifdef CONFIG_SERIAL_8250
|
||||
uart.line = 0;
|
||||
uart.type = PORT_UNKNOWN;
|
||||
uart.uartclk = 18432000;
|
||||
uart.irq = COBALT_SERIAL_IRQ;
|
||||
uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF |
|
||||
UPF_SKIP_TEST;
|
||||
uart.iotype = UPIO_MEM;
|
||||
uart.mapbase = 0x1c800000;
|
||||
|
||||
early_serial_setup(&uart);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20
|
||||
# Tue Feb 20 21:47:24 2007
|
||||
# Linux kernel version: 2.6.21-rc7
|
||||
# Wed Apr 18 14:25:45 2007
|
||||
#
|
||||
CONFIG_MIPS=y
|
||||
|
||||
|
@ -62,7 +62,6 @@ CONFIG_MIPS_COBALT=y
|
|||
# CONFIG_TOSHIBA_JMR3927 is not set
|
||||
# CONFIG_TOSHIBA_RBTX4927 is not set
|
||||
# CONFIG_TOSHIBA_RBTX4938 is not set
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
||||
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
|
||||
|
@ -74,12 +73,14 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
|||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
CONFIG_DMA_NEED_PCI_MAP_STATE=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
||||
CONFIG_I8259=y
|
||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
||||
CONFIG_IRQ_CPU=y
|
||||
CONFIG_MIPS_GT64111=y
|
||||
CONFIG_PCI_GT64XXX_PCI0=y
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
|
||||
#
|
||||
|
@ -179,6 +180,7 @@ CONFIG_SYSVIPC_SYSCTL=y
|
|||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_RELAY=y
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
|
@ -477,7 +479,6 @@ CONFIG_BLK_DEV_LOOP=y
|
|||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_SX8 is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_CDROM_PKTCDVD=y
|
||||
CONFIG_CDROM_PKTCDVD_BUFFERS=8
|
||||
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
|
||||
|
@ -518,7 +519,7 @@ CONFIG_BLK_DEV_IDEPCI=y
|
|||
# CONFIG_BLK_DEV_OPTI621 is not set
|
||||
CONFIG_BLK_DEV_IDEDMA_PCI=y
|
||||
# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
|
||||
# CONFIG_IDEDMA_PCI_AUTO is not set
|
||||
# CONFIG_IDEDMA_ONLYDISK is not set
|
||||
# CONFIG_BLK_DEV_AEC62XX is not set
|
||||
# CONFIG_BLK_DEV_ALI15X3 is not set
|
||||
# CONFIG_BLK_DEV_AMD74XX is not set
|
||||
|
@ -546,7 +547,6 @@ CONFIG_BLK_DEV_TC86C001=y
|
|||
# CONFIG_IDE_ARM is not set
|
||||
CONFIG_BLK_DEV_IDEDMA=y
|
||||
# CONFIG_IDEDMA_IVB is not set
|
||||
# CONFIG_IDEDMA_AUTO is not set
|
||||
# CONFIG_BLK_DEV_HD is not set
|
||||
|
||||
#
|
||||
|
@ -779,7 +779,8 @@ CONFIG_LEGACY_PTY_COUNT=256
|
|||
#
|
||||
# CONFIG_WATCHDOG is not set
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_RTC=y
|
||||
# CONFIG_RTC is not set
|
||||
# CONFIG_GEN_RTC is not set
|
||||
CONFIG_COBALT_LCD=y
|
||||
# CONFIG_DTLK is not set
|
||||
# CONFIG_R3964 is not set
|
||||
|
@ -814,6 +815,11 @@ CONFIG_COBALT_LCD=y
|
|||
# CONFIG_HWMON is not set
|
||||
# CONFIG_HWMON_VID is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
|
@ -827,7 +833,7 @@ CONFIG_COBALT_LCD=y
|
|||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_FIRMWARE_EDID is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
# CONFIG_FB is not set
|
||||
|
||||
#
|
||||
|
@ -835,7 +841,6 @@ CONFIG_COBALT_LCD=y
|
|||
#
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
|
@ -894,7 +899,29 @@ CONFIG_USB_ARCH_HAS_EHCI=y
|
|||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
CONFIG_RTC_LIB=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_HCTOSYS=y
|
||||
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
|
||||
# CONFIG_RTC_DEBUG is not set
|
||||
|
||||
#
|
||||
# RTC interfaces
|
||||
#
|
||||
CONFIG_RTC_INTF_SYSFS=y
|
||||
CONFIG_RTC_INTF_PROC=y
|
||||
CONFIG_RTC_INTF_DEV=y
|
||||
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
|
||||
|
||||
#
|
||||
# RTC drivers
|
||||
#
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
# CONFIG_RTC_DRV_DS1553 is not set
|
||||
# CONFIG_RTC_DRV_DS1742 is not set
|
||||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
# CONFIG_RTC_DRV_TEST is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
# DMA Engine support
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_MIPS=y
|
|||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_MACH_ALCHEMY=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_MIPS=y
|
|||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_MACH_ALCHEMY=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_MIPS=y
|
|||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_MACH_ALCHEMY=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_MIPS=y
|
|||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_MACH_ALCHEMY=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_MIPS=y
|
|||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_MACH_ALCHEMY=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
|
|
@ -1,897 +0,0 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20
|
||||
# Tue Feb 20 21:47:33 2007
|
||||
#
|
||||
CONFIG_MIPS=y
|
||||
|
||||
#
|
||||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
# CONFIG_MIPS_PB1100 is not set
|
||||
# CONFIG_MIPS_PB1500 is not set
|
||||
# CONFIG_MIPS_PB1550 is not set
|
||||
# CONFIG_MIPS_PB1200 is not set
|
||||
# CONFIG_MIPS_DB1000 is not set
|
||||
# CONFIG_MIPS_DB1100 is not set
|
||||
# CONFIG_MIPS_DB1500 is not set
|
||||
# CONFIG_MIPS_DB1550 is not set
|
||||
# CONFIG_MIPS_DB1200 is not set
|
||||
# CONFIG_MIPS_MIRAGE is not set
|
||||
# CONFIG_BASLER_EXCITE is not set
|
||||
# CONFIG_MIPS_COBALT is not set
|
||||
# CONFIG_MACH_DECSTATION is not set
|
||||
# CONFIG_MIPS_EV64120 is not set
|
||||
# CONFIG_MACH_JAZZ is not set
|
||||
# CONFIG_LASAT is not set
|
||||
# CONFIG_MIPS_ATLAS is not set
|
||||
# CONFIG_MIPS_MALTA is not set
|
||||
# CONFIG_MIPS_SEAD is not set
|
||||
# CONFIG_WR_PPMC is not set
|
||||
# CONFIG_MIPS_SIM is not set
|
||||
CONFIG_MOMENCO_JAGUAR_ATX=y
|
||||
# CONFIG_MOMENCO_OCELOT is not set
|
||||
# CONFIG_MOMENCO_OCELOT_3 is not set
|
||||
# CONFIG_MOMENCO_OCELOT_C is not set
|
||||
# CONFIG_MOMENCO_OCELOT_G is not set
|
||||
# CONFIG_MIPS_XXS1500 is not set
|
||||
# CONFIG_PNX8550_JBS is not set
|
||||
# CONFIG_PNX8550_STB810 is not set
|
||||
# CONFIG_DDB5477 is not set
|
||||
# CONFIG_MACH_VR41XX is not set
|
||||
# CONFIG_PMC_YOSEMITE is not set
|
||||
# CONFIG_QEMU is not set
|
||||
# CONFIG_MARKEINS is not set
|
||||
# CONFIG_SGI_IP22 is not set
|
||||
# CONFIG_SGI_IP27 is not set
|
||||
# CONFIG_SGI_IP32 is not set
|
||||
# CONFIG_SIBYTE_BIGSUR is not set
|
||||
# CONFIG_SIBYTE_SWARM is not set
|
||||
# CONFIG_SIBYTE_SENTOSA is not set
|
||||
# CONFIG_SIBYTE_RHONE is not set
|
||||
# CONFIG_SIBYTE_CARMEL is not set
|
||||
# CONFIG_SIBYTE_PTSWARM is not set
|
||||
# CONFIG_SIBYTE_LITTLESUR is not set
|
||||
# CONFIG_SIBYTE_CRHINE is not set
|
||||
# CONFIG_SIBYTE_CRHONE is not set
|
||||
# CONFIG_SNI_RM is not set
|
||||
# CONFIG_TOSHIBA_JMR3927 is not set
|
||||
# CONFIG_TOSHIBA_RBTX4927 is not set
|
||||
# CONFIG_TOSHIBA_RBTX4938 is not set
|
||||
CONFIG_JAGUAR_DMALOW=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
||||
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
|
||||
CONFIG_GENERIC_FIND_NEXT_BIT=y
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
CONFIG_DMA_NEED_PCI_MAP_STATE=y
|
||||
CONFIG_LIMITED_DMA=y
|
||||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
# CONFIG_CPU_LITTLE_ENDIAN is not set
|
||||
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
|
||||
CONFIG_IRQ_CPU=y
|
||||
CONFIG_IRQ_CPU_RM7K=y
|
||||
CONFIG_IRQ_MV64340=y
|
||||
CONFIG_PCI_MARVELL=y
|
||||
CONFIG_SWAP_IO_SPACE=y
|
||||
CONFIG_BOOT_ELF32=y
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
|
||||
#
|
||||
# CPU selection
|
||||
#
|
||||
# CONFIG_CPU_MIPS32_R1 is not set
|
||||
# CONFIG_CPU_MIPS32_R2 is not set
|
||||
# CONFIG_CPU_MIPS64_R1 is not set
|
||||
# CONFIG_CPU_MIPS64_R2 is not set
|
||||
# CONFIG_CPU_R3000 is not set
|
||||
# CONFIG_CPU_TX39XX is not set
|
||||
# CONFIG_CPU_VR41XX is not set
|
||||
# CONFIG_CPU_R4300 is not set
|
||||
# CONFIG_CPU_R4X00 is not set
|
||||
# CONFIG_CPU_TX49XX is not set
|
||||
# CONFIG_CPU_R5000 is not set
|
||||
# CONFIG_CPU_R5432 is not set
|
||||
# CONFIG_CPU_R6000 is not set
|
||||
# CONFIG_CPU_NEVADA is not set
|
||||
# CONFIG_CPU_R8000 is not set
|
||||
# CONFIG_CPU_R10000 is not set
|
||||
# CONFIG_CPU_RM7000 is not set
|
||||
CONFIG_CPU_RM9000=y
|
||||
# CONFIG_CPU_SB1 is not set
|
||||
CONFIG_SYS_HAS_CPU_RM9000=y
|
||||
CONFIG_WEAK_ORDERING=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
|
||||
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
|
||||
|
||||
#
|
||||
# Kernel type
|
||||
#
|
||||
CONFIG_32BIT=y
|
||||
# CONFIG_64BIT is not set
|
||||
CONFIG_PAGE_SIZE_4KB=y
|
||||
# CONFIG_PAGE_SIZE_8KB is not set
|
||||
# CONFIG_PAGE_SIZE_16KB is not set
|
||||
# CONFIG_PAGE_SIZE_64KB is not set
|
||||
CONFIG_BOARD_SCACHE=y
|
||||
CONFIG_RM7000_CPU_SCACHE=y
|
||||
CONFIG_CPU_HAS_PREFETCH=y
|
||||
CONFIG_MIPS_MT_DISABLED=y
|
||||
# CONFIG_MIPS_MT_SMP is not set
|
||||
# CONFIG_MIPS_MT_SMTC is not set
|
||||
# CONFIG_MIPS_VPE_LOADER is not set
|
||||
# CONFIG_64BIT_PHYS_ADDR is not set
|
||||
CONFIG_CPU_HAS_LLSC=y
|
||||
CONFIG_CPU_HAS_SYNC=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_GENERIC_IRQ_PROBE=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_CPU_SUPPORTS_HIGHMEM=y
|
||||
CONFIG_SYS_SUPPORTS_HIGHMEM=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
# CONFIG_SPARSEMEM_STATIC is not set
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
# CONFIG_RESOURCES_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=1
|
||||
# CONFIG_HZ_48 is not set
|
||||
# CONFIG_HZ_100 is not set
|
||||
# CONFIG_HZ_128 is not set
|
||||
# CONFIG_HZ_250 is not set
|
||||
# CONFIG_HZ_256 is not set
|
||||
CONFIG_HZ_1000=y
|
||||
# CONFIG_HZ_1024 is not set
|
||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
||||
CONFIG_HZ=1000
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
CONFIG_LOCKDEP_SUPPORT=y
|
||||
CONFIG_STACKTRACE_SUPPORT=y
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
|
||||
#
|
||||
# Code maturity level options
|
||||
#
|
||||
# CONFIG_EXPERIMENTAL is not set
|
||||
CONFIG_BROKEN_ON_SMP=y
|
||||
CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_SWAP=y
|
||||
CONFIG_SYSVIPC=y
|
||||
# CONFIG_IPC_NS is not set
|
||||
CONFIG_SYSVIPC_SYSCTL=y
|
||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
CONFIG_HOTPLUG=y
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
CONFIG_ELF_CORE=y
|
||||
CONFIG_BASE_FULL=y
|
||||
CONFIG_FUTEX=y
|
||||
CONFIG_EPOLL=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_RT_MUTEXES=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=0
|
||||
# CONFIG_SLOB is not set
|
||||
|
||||
#
|
||||
# Loadable module support
|
||||
#
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_MODVERSIONS is not set
|
||||
CONFIG_MODULE_SRCVERSION_ALL=y
|
||||
CONFIG_KMOD=y
|
||||
|
||||
#
|
||||
# Block layer
|
||||
#
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_LSF is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
#
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
CONFIG_IOSCHED_AS=y
|
||||
CONFIG_IOSCHED_DEADLINE=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
CONFIG_DEFAULT_AS=y
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
# CONFIG_DEFAULT_CFQ is not set
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||
|
||||
#
|
||||
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
|
||||
#
|
||||
CONFIG_HW_HAS_PCI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_MMU=y
|
||||
|
||||
#
|
||||
# PCCARD (PCMCIA/CardBus) support
|
||||
#
|
||||
# CONFIG_PCCARD is not set
|
||||
|
||||
#
|
||||
# PCI Hotplug Support
|
||||
#
|
||||
|
||||
#
|
||||
# Executable file formats
|
||||
#
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_TRAD_SIGNALS=y
|
||||
|
||||
#
|
||||
# Power management options
|
||||
#
|
||||
CONFIG_PM=y
|
||||
# CONFIG_PM_LEGACY is not set
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
# CONFIG_PM_SYSFS_DEPRECATED is not set
|
||||
|
||||
#
|
||||
# Networking
|
||||
#
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
# CONFIG_NETDEBUG is not set
|
||||
# CONFIG_PACKET is not set
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM=y
|
||||
CONFIG_XFRM_USER=m
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IP_MULTICAST is not set
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IP_FIB_HASH=y
|
||||
CONFIG_IP_PNP=y
|
||||
# CONFIG_IP_PNP_DHCP is not set
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_IP_PNP_RARP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
# CONFIG_INET_AH is not set
|
||||
# CONFIG_INET_ESP is not set
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
CONFIG_INET_TUNNEL=m
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=m
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=m
|
||||
CONFIG_INET_XFRM_MODE_BEET=m
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
CONFIG_IPV6=m
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_INET6_XFRM_TUNNEL=m
|
||||
CONFIG_INET6_TUNNEL=m
|
||||
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
|
||||
CONFIG_INET6_XFRM_MODE_TUNNEL=m
|
||||
CONFIG_INET6_XFRM_MODE_BEET=m
|
||||
CONFIG_IPV6_SIT=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
# CONFIG_NETFILTER is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
# CONFIG_VLAN_8021Q is not set
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
|
||||
#
|
||||
# QoS and/or fair queueing
|
||||
#
|
||||
# CONFIG_NET_SCHED is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
#
|
||||
# CONFIG_NET_PKTGEN is not set
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
CONFIG_IEEE80211=m
|
||||
# CONFIG_IEEE80211_DEBUG is not set
|
||||
CONFIG_IEEE80211_CRYPT_WEP=m
|
||||
CONFIG_IEEE80211_CRYPT_CCMP=m
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
CONFIG_FW_LOADER=m
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
|
||||
#
|
||||
# Connector - unified userspace <-> kernelspace linker
|
||||
#
|
||||
CONFIG_CONNECTOR=m
|
||||
|
||||
#
|
||||
# Memory Technology Devices (MTD)
|
||||
#
|
||||
# CONFIG_MTD is not set
|
||||
|
||||
#
|
||||
# Parallel port support
|
||||
#
|
||||
# CONFIG_PARPORT is not set
|
||||
|
||||
#
|
||||
# Plug and Play support
|
||||
#
|
||||
# CONFIG_PNPACPI is not set
|
||||
|
||||
#
|
||||
# Block devices
|
||||
#
|
||||
# CONFIG_BLK_CPQ_DA is not set
|
||||
# CONFIG_BLK_CPQ_CISS_DA is not set
|
||||
# CONFIG_BLK_DEV_DAC960 is not set
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
# CONFIG_BLK_DEV_LOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_SX8 is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_CDROM_PKTCDVD=m
|
||||
CONFIG_CDROM_PKTCDVD_BUFFERS=8
|
||||
CONFIG_ATA_OVER_ETH=m
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
CONFIG_SGI_IOC4=m
|
||||
|
||||
#
|
||||
# ATA/ATAPI/MFM/RLL support
|
||||
#
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
CONFIG_RAID_ATTRS=m
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
|
||||
#
|
||||
# Serial ATA (prod) and Parallel ATA (experimental) drivers
|
||||
#
|
||||
# CONFIG_ATA is not set
|
||||
|
||||
#
|
||||
# Multi-device support (RAID and LVM)
|
||||
#
|
||||
# CONFIG_MD is not set
|
||||
|
||||
#
|
||||
# Fusion MPT device support
|
||||
#
|
||||
# CONFIG_FUSION is not set
|
||||
|
||||
#
|
||||
# IEEE 1394 (FireWire) support
|
||||
#
|
||||
# CONFIG_IEEE1394 is not set
|
||||
|
||||
#
|
||||
# I2O device support
|
||||
#
|
||||
# CONFIG_I2O is not set
|
||||
|
||||
#
|
||||
# Network device support
|
||||
#
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
# CONFIG_TUN is not set
|
||||
|
||||
#
|
||||
# ARCnet devices
|
||||
#
|
||||
# CONFIG_ARCNET is not set
|
||||
|
||||
#
|
||||
# PHY device support
|
||||
#
|
||||
CONFIG_PHYLIB=m
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
CONFIG_MARVELL_PHY=m
|
||||
CONFIG_DAVICOM_PHY=m
|
||||
CONFIG_QSEMI_PHY=m
|
||||
CONFIG_LXT_PHY=m
|
||||
CONFIG_CICADA_PHY=m
|
||||
CONFIG_VITESSE_PHY=m
|
||||
CONFIG_SMSC_PHY=m
|
||||
# CONFIG_BROADCOM_PHY is not set
|
||||
# CONFIG_FIXED_PHY is not set
|
||||
|
||||
#
|
||||
# Ethernet (10 or 100Mbit)
|
||||
#
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
# CONFIG_HAPPYMEAL is not set
|
||||
# CONFIG_SUNGEM is not set
|
||||
# CONFIG_CASSINI is not set
|
||||
# CONFIG_NET_VENDOR_3COM is not set
|
||||
# CONFIG_DM9000 is not set
|
||||
|
||||
#
|
||||
# Tulip family network device support
|
||||
#
|
||||
# CONFIG_NET_TULIP is not set
|
||||
# CONFIG_HP100 is not set
|
||||
CONFIG_NET_PCI=y
|
||||
# CONFIG_PCNET32 is not set
|
||||
# CONFIG_AMD8111_ETH is not set
|
||||
# CONFIG_ADAPTEC_STARFIRE is not set
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_FORCEDETH is not set
|
||||
# CONFIG_DGRS is not set
|
||||
CONFIG_EEPRO100=y
|
||||
# CONFIG_E100 is not set
|
||||
# CONFIG_FEALNX is not set
|
||||
# CONFIG_NATSEMI is not set
|
||||
# CONFIG_NE2K_PCI is not set
|
||||
# CONFIG_8139TOO is not set
|
||||
# CONFIG_SIS900 is not set
|
||||
# CONFIG_EPIC100 is not set
|
||||
# CONFIG_SUNDANCE is not set
|
||||
# CONFIG_TLAN is not set
|
||||
# CONFIG_VIA_RHINE is not set
|
||||
|
||||
#
|
||||
# Ethernet (1000 Mbit)
|
||||
#
|
||||
# CONFIG_ACENIC is not set
|
||||
# CONFIG_DL2K is not set
|
||||
# CONFIG_E1000 is not set
|
||||
# CONFIG_NS83820 is not set
|
||||
# CONFIG_HAMACHI is not set
|
||||
# CONFIG_R8169 is not set
|
||||
# CONFIG_SIS190 is not set
|
||||
# CONFIG_SKGE is not set
|
||||
# CONFIG_SKY2 is not set
|
||||
# CONFIG_SK98LIN is not set
|
||||
# CONFIG_VIA_VELOCITY is not set
|
||||
# CONFIG_TIGON3 is not set
|
||||
# CONFIG_BNX2 is not set
|
||||
CONFIG_MV643XX_ETH=y
|
||||
CONFIG_QLA3XXX=m
|
||||
|
||||
#
|
||||
# Ethernet (10000 Mbit)
|
||||
#
|
||||
# CONFIG_CHELSIO_T1 is not set
|
||||
CONFIG_CHELSIO_T3=m
|
||||
# CONFIG_IXGB is not set
|
||||
# CONFIG_S2IO is not set
|
||||
# CONFIG_MYRI10GE is not set
|
||||
CONFIG_NETXEN_NIC=m
|
||||
|
||||
#
|
||||
# Token Ring devices
|
||||
#
|
||||
# CONFIG_TR is not set
|
||||
|
||||
#
|
||||
# Wireless LAN (non-hamradio)
|
||||
#
|
||||
# CONFIG_NET_RADIO is not set
|
||||
|
||||
#
|
||||
# Wan interfaces
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_FDDI is not set
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
# CONFIG_NETPOLL is not set
|
||||
# CONFIG_NET_POLL_CONTROLLER is not set
|
||||
|
||||
#
|
||||
# ISDN subsystem
|
||||
#
|
||||
# CONFIG_ISDN is not set
|
||||
|
||||
#
|
||||
# Telephony Support
|
||||
#
|
||||
# CONFIG_PHONE is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
# CONFIG_INPUT is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
# CONFIG_SERIAL_8250_EXTENDED is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
# CONFIG_SERIAL_JSM is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
|
||||
|
||||
#
|
||||
# IPMI
|
||||
#
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
|
||||
#
|
||||
# Watchdog Cards
|
||||
#
|
||||
# CONFIG_WATCHDOG is not set
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_RTC is not set
|
||||
# CONFIG_GEN_RTC is not set
|
||||
# CONFIG_DTLK is not set
|
||||
# CONFIG_R3964 is not set
|
||||
# CONFIG_APPLICOM is not set
|
||||
# CONFIG_DRM is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
|
||||
#
|
||||
# TPM devices
|
||||
#
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
# CONFIG_I2C is not set
|
||||
|
||||
#
|
||||
# SPI support
|
||||
#
|
||||
# CONFIG_SPI is not set
|
||||
# CONFIG_SPI_MASTER is not set
|
||||
|
||||
#
|
||||
# Dallas's 1-wire bus
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
|
||||
#
|
||||
# Hardware Monitoring support
|
||||
#
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_HWMON_VID is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
|
||||
#
|
||||
# Digital Video Broadcasting Devices
|
||||
#
|
||||
# CONFIG_DVB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_FIRMWARE_EDID is not set
|
||||
# CONFIG_FB is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
CONFIG_USB_ARCH_HAS_OHCI=y
|
||||
CONFIG_USB_ARCH_HAS_EHCI=y
|
||||
# CONFIG_USB is not set
|
||||
|
||||
#
|
||||
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
|
||||
#
|
||||
|
||||
#
|
||||
# USB Gadget Support
|
||||
#
|
||||
# CONFIG_USB_GADGET is not set
|
||||
|
||||
#
|
||||
# MMC/SD Card support
|
||||
#
|
||||
# CONFIG_MMC is not set
|
||||
|
||||
#
|
||||
# LED devices
|
||||
#
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
|
||||
#
|
||||
# LED drivers
|
||||
#
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
||||
#
|
||||
# InfiniBand support
|
||||
#
|
||||
# CONFIG_INFINIBAND is not set
|
||||
|
||||
#
|
||||
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
|
||||
#
|
||||
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
|
||||
#
|
||||
# DMA Engine support
|
||||
#
|
||||
# CONFIG_DMA_ENGINE is not set
|
||||
|
||||
#
|
||||
# DMA Clients
|
||||
#
|
||||
|
||||
#
|
||||
# DMA Devices
|
||||
#
|
||||
|
||||
#
|
||||
# Auxiliary Display support
|
||||
#
|
||||
|
||||
#
|
||||
# Virtualization
|
||||
#
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_QUOTA is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_GENERIC_ACL=y
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
CONFIG_RAMFS=y
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
|
||||
#
|
||||
# Network File Systems
|
||||
#
|
||||
CONFIG_NFS_FS=y
|
||||
# CONFIG_NFS_V3 is not set
|
||||
# CONFIG_NFS_DIRECTIO is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
|
||||
#
|
||||
# Native Language Support
|
||||
#
|
||||
# CONFIG_NLS is not set
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
# CONFIG_PRINTK_TIME is not set
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
# CONFIG_MAGIC_SYSRQ is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_CROSSCOMPILE=y
|
||||
CONFIG_CMDLINE=""
|
||||
CONFIG_SYS_SUPPORTS_KGDB=y
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_KEYS_DEBUG_PROC_KEYS=y
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_BLKCIPHER=m
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_NULL=m
|
||||
CONFIG_CRYPTO_MD4=m
|
||||
CONFIG_CRYPTO_MD5=m
|
||||
CONFIG_CRYPTO_SHA1=m
|
||||
CONFIG_CRYPTO_SHA256=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_ECB=m
|
||||
CONFIG_CRYPTO_CBC=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_DES=m
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
CONFIG_CRYPTO_TWOFISH_COMMON=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_AES=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_TEA=m
|
||||
CONFIG_CRYPTO_ARC4=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
CONFIG_CRYPTO_DEFLATE=m
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_CRC32C=m
|
||||
CONFIG_CRYPTO_CAMELLIA=m
|
||||
# CONFIG_CRYPTO_TEST is not set
|
||||
|
||||
#
|
||||
# Hardware crypto devices
|
||||
#
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=m
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
CONFIG_CRC16=m
|
||||
CONFIG_CRC32=m
|
||||
CONFIG_LIBCRC32C=m
|
||||
CONFIG_ZLIB_INFLATE=m
|
||||
CONFIG_ZLIB_DEFLATE=m
|
||||
CONFIG_PLIST=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
|
@ -80,7 +80,6 @@ CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
|||
CONFIG_MIPS_TX3927=y
|
||||
CONFIG_SWAP_IO_SPACE=y
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
CONFIG_TOSHIBA_BOARDS=y
|
||||
|
||||
#
|
||||
# CPU selection
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_MIPS=y
|
|||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_MACH_ALCHEMY=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_MIPS=y
|
|||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_MACH_ALCHEMY=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
|
|
@ -9,6 +9,7 @@ CONFIG_MIPS=y
|
|||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
CONFIG_MACH_ALCHEMY=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
|
|
@ -1,14 +1,13 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20
|
||||
# Tue Feb 20 21:47:36 2007
|
||||
# Linux kernel version: 2.6.21
|
||||
# Wed May 9 23:44:19 2007
|
||||
#
|
||||
CONFIG_MIPS=y
|
||||
|
||||
#
|
||||
# Machine selection
|
||||
#
|
||||
CONFIG_ZONE_DMA=y
|
||||
# CONFIG_MIPS_MTX1 is not set
|
||||
# CONFIG_MIPS_BOSPORUS is not set
|
||||
# CONFIG_MIPS_PB1000 is not set
|
||||
|
@ -33,11 +32,9 @@ CONFIG_ZONE_DMA=y
|
|||
# CONFIG_MIPS_SEAD is not set
|
||||
# CONFIG_WR_PPMC is not set
|
||||
# CONFIG_MIPS_SIM is not set
|
||||
# CONFIG_MOMENCO_JAGUAR_ATX is not set
|
||||
# CONFIG_MOMENCO_OCELOT is not set
|
||||
# CONFIG_MOMENCO_OCELOT_3 is not set
|
||||
# CONFIG_MOMENCO_OCELOT_C is not set
|
||||
CONFIG_MOMENCO_OCELOT_G=y
|
||||
# CONFIG_MIPS_XXS1500 is not set
|
||||
# CONFIG_PNX8550_JBS is not set
|
||||
# CONFIG_PNX8550_STB810 is not set
|
||||
|
@ -60,8 +57,9 @@ CONFIG_MOMENCO_OCELOT_G=y
|
|||
# CONFIG_SIBYTE_CRHONE is not set
|
||||
# CONFIG_SNI_RM is not set
|
||||
# CONFIG_TOSHIBA_JMR3927 is not set
|
||||
# CONFIG_TOSHIBA_RBTX4927 is not set
|
||||
CONFIG_TOSHIBA_RBTX4927=y
|
||||
# CONFIG_TOSHIBA_RBTX4938 is not set
|
||||
# CONFIG_TOSHIBA_FPCIB0 is not set
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
||||
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
|
||||
|
@ -70,19 +68,15 @@ CONFIG_GENERIC_HWEIGHT=y
|
|||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
CONFIG_DMA_NEED_PCI_MAP_STATE=y
|
||||
CONFIG_I8259=y
|
||||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
# CONFIG_CPU_LITTLE_ENDIAN is not set
|
||||
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
|
||||
CONFIG_IRQ_CPU=y
|
||||
CONFIG_IRQ_CPU_RM7K=y
|
||||
CONFIG_PCI_MARVELL=y
|
||||
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
||||
CONFIG_SWAP_IO_SPACE=y
|
||||
# CONFIG_SYSCLK_75 is not set
|
||||
# CONFIG_SYSCLK_83 is not set
|
||||
CONFIG_SYSCLK_100=y
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
|
||||
#
|
||||
|
@ -97,18 +91,19 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
|
|||
# CONFIG_CPU_VR41XX is not set
|
||||
# CONFIG_CPU_R4300 is not set
|
||||
# CONFIG_CPU_R4X00 is not set
|
||||
# CONFIG_CPU_TX49XX is not set
|
||||
CONFIG_CPU_TX49XX=y
|
||||
# CONFIG_CPU_R5000 is not set
|
||||
# CONFIG_CPU_R5432 is not set
|
||||
# CONFIG_CPU_R6000 is not set
|
||||
# CONFIG_CPU_NEVADA is not set
|
||||
# CONFIG_CPU_R8000 is not set
|
||||
# CONFIG_CPU_R10000 is not set
|
||||
CONFIG_CPU_RM7000=y
|
||||
# CONFIG_CPU_RM7000 is not set
|
||||
# CONFIG_CPU_RM9000 is not set
|
||||
# CONFIG_CPU_SB1 is not set
|
||||
CONFIG_SYS_HAS_CPU_RM7000=y
|
||||
CONFIG_SYS_HAS_CPU_TX49XX=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
|
||||
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
|
||||
|
||||
|
@ -121,19 +116,15 @@ CONFIG_PAGE_SIZE_4KB=y
|
|||
# CONFIG_PAGE_SIZE_8KB is not set
|
||||
# CONFIG_PAGE_SIZE_16KB is not set
|
||||
# CONFIG_PAGE_SIZE_64KB is not set
|
||||
CONFIG_BOARD_SCACHE=y
|
||||
CONFIG_RM7000_CPU_SCACHE=y
|
||||
CONFIG_CPU_HAS_PREFETCH=y
|
||||
CONFIG_MIPS_MT_DISABLED=y
|
||||
# CONFIG_MIPS_MT_SMP is not set
|
||||
# CONFIG_MIPS_MT_SMTC is not set
|
||||
# CONFIG_MIPS_VPE_LOADER is not set
|
||||
# CONFIG_64BIT_PHYS_ADDR is not set
|
||||
CONFIG_CPU_HAS_LLSC=y
|
||||
CONFIG_CPU_HAS_SYNC=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_GENERIC_IRQ_PROBE=y
|
||||
CONFIG_CPU_SUPPORTS_HIGHMEM=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
|
@ -143,17 +134,17 @@ CONFIG_FLATMEM=y
|
|||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
# CONFIG_SPARSEMEM_STATIC is not set
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_RESOURCES_64BIT=y
|
||||
CONFIG_ZONE_DMA_FLAG=1
|
||||
# CONFIG_RESOURCES_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
# CONFIG_HZ_48 is not set
|
||||
# CONFIG_HZ_100 is not set
|
||||
# CONFIG_HZ_128 is not set
|
||||
# CONFIG_HZ_250 is not set
|
||||
CONFIG_HZ_250=y
|
||||
# CONFIG_HZ_256 is not set
|
||||
CONFIG_HZ_1000=y
|
||||
# CONFIG_HZ_1000 is not set
|
||||
# CONFIG_HZ_1024 is not set
|
||||
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
||||
CONFIG_HZ=1000
|
||||
CONFIG_HZ=250
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
|
@ -183,34 +174,42 @@ CONFIG_SYSVIPC_SYSCTL=y
|
|||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_RELAY=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
# CONFIG_RELAY is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
CONFIG_HOTPLUG=y
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
CONFIG_ELF_CORE=y
|
||||
CONFIG_BASE_FULL=y
|
||||
CONFIG_FUTEX=y
|
||||
CONFIG_EPOLL=y
|
||||
# CONFIG_FUTEX is not set
|
||||
# CONFIG_EPOLL is not set
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_RT_MUTEXES=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
# CONFIG_SLOB is not set
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=0
|
||||
# CONFIG_SLOB is not set
|
||||
|
||||
#
|
||||
# Loadable module support
|
||||
#
|
||||
# CONFIG_MODULES is not set
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_MODULE_UNLOAD is not set
|
||||
# CONFIG_MODVERSIONS is not set
|
||||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
CONFIG_KMOD=y
|
||||
|
||||
#
|
||||
# Block layer
|
||||
|
@ -218,7 +217,7 @@ CONFIG_BASE_SMALL=0
|
|||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
CONFIG_LSF=y
|
||||
# CONFIG_LSF is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
|
@ -238,17 +237,12 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
|
|||
#
|
||||
CONFIG_HW_HAS_PCI=y
|
||||
CONFIG_PCI=y
|
||||
# CONFIG_ARCH_SUPPORTS_MSI is not set
|
||||
CONFIG_MMU=y
|
||||
|
||||
#
|
||||
# PCCARD (PCMCIA/CardBus) support
|
||||
#
|
||||
# CONFIG_PCCARD is not set
|
||||
|
||||
#
|
||||
# PCI Hotplug Support
|
||||
#
|
||||
# CONFIG_HOTPLUG_PCI is not set
|
||||
|
||||
#
|
||||
# Executable file formats
|
||||
|
@ -260,10 +254,7 @@ CONFIG_TRAD_SIGNALS=y
|
|||
#
|
||||
# Power management options
|
||||
#
|
||||
CONFIG_PM=y
|
||||
# CONFIG_PM_LEGACY is not set
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
# CONFIG_PM_SYSFS_DEPRECATED is not set
|
||||
# CONFIG_PM is not set
|
||||
|
||||
#
|
||||
# Networking
|
||||
|
@ -273,25 +264,21 @@ CONFIG_NET=y
|
|||
#
|
||||
# Networking options
|
||||
#
|
||||
# CONFIG_NETDEBUG is not set
|
||||
# CONFIG_PACKET is not set
|
||||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM=y
|
||||
CONFIG_XFRM_USER=y
|
||||
# CONFIG_XFRM_SUB_POLICY is not set
|
||||
CONFIG_XFRM_MIGRATE=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_NET_KEY_MIGRATE=y
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IP_MULTICAST is not set
|
||||
CONFIG_IP_MULTICAST=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IP_FIB_HASH=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_IP_PNP_DHCP is not set
|
||||
# CONFIG_IP_PNP_BOOTP is not set
|
||||
# CONFIG_IP_PNP_RARP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_IP_MROUTE is not set
|
||||
# CONFIG_ARPD is not set
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
# CONFIG_INET_AH is not set
|
||||
|
@ -299,19 +286,19 @@ CONFIG_IP_PNP_DHCP=y
|
|||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
CONFIG_TCP_MD5SIG=y
|
||||
# CONFIG_TCP_MD5SIG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_INET6_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET6_TUNNEL is not set
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
# CONFIG_NETWORK_SECMARK is not set
|
||||
# CONFIG_NETFILTER is not set
|
||||
|
||||
#
|
||||
|
@ -352,13 +339,16 @@ CONFIG_NETWORK_SECMARK=y
|
|||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
CONFIG_IEEE80211=y
|
||||
# CONFIG_IEEE80211_DEBUG is not set
|
||||
CONFIG_IEEE80211_CRYPT_WEP=y
|
||||
CONFIG_IEEE80211_CRYPT_CCMP=y
|
||||
CONFIG_IEEE80211_SOFTMAC=y
|
||||
# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
# CONFIG_AF_RXRPC is not set
|
||||
|
||||
#
|
||||
# Wireless
|
||||
#
|
||||
# CONFIG_CFG80211 is not set
|
||||
# CONFIG_WIRELESS_EXT is not set
|
||||
# CONFIG_MAC80211 is not set
|
||||
# CONFIG_IEEE80211 is not set
|
||||
# CONFIG_RFKILL is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
|
@ -369,18 +359,12 @@ CONFIG_WIRELESS_EXT=y
|
|||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
CONFIG_FW_LOADER=y
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
|
||||
#
|
||||
# Connector - unified userspace <-> kernelspace linker
|
||||
#
|
||||
CONFIG_CONNECTOR=y
|
||||
CONFIG_PROC_EVENTS=y
|
||||
|
||||
#
|
||||
# Memory Technology Devices (MTD)
|
||||
#
|
||||
# CONFIG_CONNECTOR is not set
|
||||
# CONFIG_MTD is not set
|
||||
|
||||
#
|
||||
|
@ -401,21 +385,24 @@ CONFIG_PROC_EVENTS=y
|
|||
# CONFIG_BLK_DEV_DAC960 is not set
|
||||
# CONFIG_BLK_DEV_UMEM is not set
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
# CONFIG_BLK_DEV_LOOP is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_SX8 is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_CDROM_PKTCDVD=y
|
||||
CONFIG_CDROM_PKTCDVD_BUFFERS=8
|
||||
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
|
||||
CONFIG_ATA_OVER_ETH=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=16
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
CONFIG_SGI_IOC4=y
|
||||
# CONFIG_PHANTOM is not set
|
||||
# CONFIG_SGI_IOC4 is not set
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
# CONFIG_BLINK is not set
|
||||
|
||||
#
|
||||
# ATA/ATAPI/MFM/RLL support
|
||||
|
@ -425,7 +412,7 @@ CONFIG_SGI_IOC4=y
|
|||
#
|
||||
# SCSI device support
|
||||
#
|
||||
CONFIG_RAID_ATTRS=y
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
|
||||
|
@ -471,27 +458,13 @@ CONFIG_NETDEVICES=y
|
|||
#
|
||||
# PHY device support
|
||||
#
|
||||
CONFIG_PHYLIB=y
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_QSEMI_PHY=y
|
||||
CONFIG_LXT_PHY=y
|
||||
CONFIG_CICADA_PHY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
# CONFIG_BROADCOM_PHY is not set
|
||||
# CONFIG_FIXED_PHY is not set
|
||||
# CONFIG_PHYLIB is not set
|
||||
|
||||
#
|
||||
# Ethernet (10 or 100Mbit)
|
||||
#
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_GALILEO_64240_ETH=y
|
||||
# CONFIG_MII is not set
|
||||
# CONFIG_HAPPYMEAL is not set
|
||||
# CONFIG_SUNGEM is not set
|
||||
# CONFIG_CASSINI is not set
|
||||
|
@ -503,6 +476,7 @@ CONFIG_GALILEO_64240_ETH=y
|
|||
#
|
||||
# CONFIG_NET_TULIP is not set
|
||||
# CONFIG_HP100 is not set
|
||||
CONFIG_NE2000=y
|
||||
# CONFIG_NET_PCI is not set
|
||||
|
||||
#
|
||||
|
@ -521,18 +495,18 @@ CONFIG_GALILEO_64240_ETH=y
|
|||
# CONFIG_SK98LIN is not set
|
||||
# CONFIG_TIGON3 is not set
|
||||
# CONFIG_BNX2 is not set
|
||||
CONFIG_QLA3XXX=y
|
||||
# CONFIG_QLA3XXX is not set
|
||||
# CONFIG_ATL1 is not set
|
||||
|
||||
#
|
||||
# Ethernet (10000 Mbit)
|
||||
#
|
||||
# CONFIG_CHELSIO_T1 is not set
|
||||
CONFIG_CHELSIO_T3=y
|
||||
# CONFIG_CHELSIO_T3 is not set
|
||||
# CONFIG_IXGB is not set
|
||||
# CONFIG_S2IO is not set
|
||||
# CONFIG_MYRI10GE is not set
|
||||
CONFIG_NETXEN_NIC=y
|
||||
# CONFIG_NETXEN_NIC is not set
|
||||
|
||||
#
|
||||
# Token Ring devices
|
||||
|
@ -540,9 +514,10 @@ CONFIG_NETXEN_NIC=y
|
|||
# CONFIG_TR is not set
|
||||
|
||||
#
|
||||
# Wireless LAN (non-hamradio)
|
||||
# Wireless LAN
|
||||
#
|
||||
# CONFIG_NET_RADIO is not set
|
||||
# CONFIG_WLAN_PRE80211 is not set
|
||||
# CONFIG_WLAN_80211 is not set
|
||||
|
||||
#
|
||||
# Wan interfaces
|
||||
|
@ -570,29 +545,7 @@ CONFIG_NETXEN_NIC=y
|
|||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_TSDEV is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
# CONFIG_INPUT is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
|
@ -601,34 +554,31 @@ CONFIG_SERIO=y
|
|||
# CONFIG_SERIO_I8042 is not set
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
# CONFIG_SERIO_PCIPS2 is not set
|
||||
# CONFIG_SERIO_LIBPS2 is not set
|
||||
CONFIG_SERIO_RAW=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_SERIO_RAW is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
# CONFIG_SERIAL_8250_EXTENDED is not set
|
||||
# CONFIG_SERIAL_8250 is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
CONFIG_SERIAL_TXX9=y
|
||||
CONFIG_HAS_TXX9_SERIAL=y
|
||||
CONFIG_SERIAL_TXX9_NR_UARTS=6
|
||||
CONFIG_SERIAL_TXX9_CONSOLE=y
|
||||
CONFIG_SERIAL_TXX9_STDSERIAL=y
|
||||
# CONFIG_SERIAL_JSM is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
|
@ -656,10 +606,7 @@ CONFIG_LEGACY_PTY_COUNT=256
|
|||
# TPM devices
|
||||
#
|
||||
# CONFIG_TCG_TPM is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
CONFIG_DEVPORT=y
|
||||
# CONFIG_I2C is not set
|
||||
|
||||
#
|
||||
|
@ -672,12 +619,12 @@ CONFIG_LEGACY_PTY_COUNT=256
|
|||
# Dallas's 1-wire bus
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
# CONFIG_HWMON is not set
|
||||
|
||||
#
|
||||
# Hardware Monitoring support
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_HWMON_VID is not set
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
|
@ -692,26 +639,20 @@ CONFIG_LEGACY_PTY_COUNT=256
|
|||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_FIRMWARE_EDID is not set
|
||||
# CONFIG_FB is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Console display driver support
|
||||
# Display device support
|
||||
#
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
# CONFIG_DISPLAY_SUPPORT is not set
|
||||
# CONFIG_VGASTATE is not set
|
||||
# CONFIG_FB is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# HID Devices
|
||||
#
|
||||
# CONFIG_HID is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
|
@ -728,10 +669,6 @@ CONFIG_USB_ARCH_HAS_EHCI=y
|
|||
# USB Gadget Support
|
||||
#
|
||||
# CONFIG_USB_GADGET is not set
|
||||
|
||||
#
|
||||
# MMC/SD Card support
|
||||
#
|
||||
# CONFIG_MMC is not set
|
||||
|
||||
#
|
||||
|
@ -759,7 +696,40 @@ CONFIG_USB_ARCH_HAS_EHCI=y
|
|||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
CONFIG_RTC_LIB=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_HCTOSYS=y
|
||||
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
|
||||
# CONFIG_RTC_DEBUG is not set
|
||||
|
||||
#
|
||||
# RTC interfaces
|
||||
#
|
||||
CONFIG_RTC_INTF_SYSFS=y
|
||||
CONFIG_RTC_INTF_PROC=y
|
||||
CONFIG_RTC_INTF_DEV=y
|
||||
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
|
||||
# CONFIG_RTC_DRV_TEST is not set
|
||||
|
||||
#
|
||||
# I2C RTC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# SPI RTC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_DS1553 is not set
|
||||
CONFIG_RTC_DRV_DS1742=y
|
||||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
# on-CPU RTC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# DMA Engine support
|
||||
|
@ -785,9 +755,7 @@ CONFIG_USB_ARCH_HAS_EHCI=y
|
|||
#
|
||||
# File systems
|
||||
#
|
||||
CONFIG_EXT2_FS=y
|
||||
# CONFIG_EXT2_FS_XATTR is not set
|
||||
# CONFIG_EXT2_FS_XIP is not set
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_EXT4DEV_FS is not set
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
|
@ -801,10 +769,10 @@ CONFIG_FS_POSIX_ACL=y
|
|||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_QUOTA is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
CONFIG_FUSE_FS=y
|
||||
# CONFIG_FUSE_FS is not set
|
||||
CONFIG_GENERIC_ACL=y
|
||||
|
||||
#
|
||||
|
@ -824,21 +792,20 @@ CONFIG_GENERIC_ACL=y
|
|||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
# CONFIG_PROC_KCORE is not set
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
CONFIG_RAMFS=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_ECRYPT_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
|
@ -855,17 +822,17 @@ CONFIG_CONFIGFS_FS=y
|
|||
# Network File Systems
|
||||
#
|
||||
CONFIG_NFS_FS=y
|
||||
# CONFIG_NFS_V3 is not set
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
# CONFIG_NFS_V4 is not set
|
||||
# CONFIG_NFS_DIRECTIO is not set
|
||||
CONFIG_NFSD=y
|
||||
# CONFIG_NFSD_V3 is not set
|
||||
# CONFIG_NFSD_TCP is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_EXPORTFS=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_SUNRPC_BIND34 is not set
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
|
@ -889,10 +856,7 @@ CONFIG_MSDOS_PARTITION=y
|
|||
#
|
||||
# Distributed Lock Manager
|
||||
#
|
||||
CONFIG_DLM=y
|
||||
CONFIG_DLM_TCP=y
|
||||
# CONFIG_DLM_SCTP is not set
|
||||
# CONFIG_DLM_DEBUG is not set
|
||||
# CONFIG_DLM is not set
|
||||
|
||||
#
|
||||
# Profiling support
|
||||
|
@ -910,72 +874,29 @@ CONFIG_ENABLE_MUST_CHECK=y
|
|||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_CROSSCOMPILE=y
|
||||
CONFIG_CMDLINE=""
|
||||
CONFIG_SYS_SUPPORTS_KGDB=y
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_KEYS_DEBUG_PROC_KEYS=y
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_BLKCIPHER=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_XCBC=y
|
||||
CONFIG_CRYPTO_NULL=y
|
||||
CONFIG_CRYPTO_MD4=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_WP512=y
|
||||
CONFIG_CRYPTO_TGR192=y
|
||||
CONFIG_CRYPTO_GF128MUL=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_PCBC=y
|
||||
CONFIG_CRYPTO_LRW=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_FCRYPT=y
|
||||
CONFIG_CRYPTO_BLOWFISH=y
|
||||
CONFIG_CRYPTO_TWOFISH=y
|
||||
CONFIG_CRYPTO_TWOFISH_COMMON=y
|
||||
CONFIG_CRYPTO_SERPENT=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
CONFIG_CRYPTO_CAST5=y
|
||||
CONFIG_CRYPTO_CAST6=y
|
||||
CONFIG_CRYPTO_TEA=y
|
||||
CONFIG_CRYPTO_ARC4=y
|
||||
CONFIG_CRYPTO_KHAZAD=y
|
||||
CONFIG_CRYPTO_ANUBIS=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CAMELLIA=y
|
||||
|
||||
#
|
||||
# Hardware crypto devices
|
||||
#
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC16 is not set
|
||||
CONFIG_CRC32=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_PLIST=y
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_DMA=y
|
|
@ -89,7 +89,6 @@ CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
|||
CONFIG_SWAP_IO_SPACE=y
|
||||
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
||||
CONFIG_HAVE_STD_PC_SERIAL_PORT=y
|
||||
CONFIG_TOSHIBA_BOARDS=y
|
||||
|
||||
#
|
||||
# CPU selection
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20
|
||||
# Tue Feb 20 21:47:41 2007
|
||||
# Linux kernel version: 2.6.21-rc6
|
||||
# Sun Apr 15 01:06:01 2007
|
||||
#
|
||||
CONFIG_MIPS=y
|
||||
|
||||
|
@ -66,10 +66,11 @@ CONFIG_MACH_VR41XX=y
|
|||
# CONFIG_IBM_WORKPAD is not set
|
||||
# CONFIG_NEC_CMBVR4133 is not set
|
||||
CONFIG_TANBAC_TB022X=y
|
||||
# CONFIG_TANBAC_TB0226 is not set
|
||||
# CONFIG_TANBAC_TB0287 is not set
|
||||
# CONFIG_VICTOR_MPC30X is not set
|
||||
# CONFIG_ZAO_CAPCELLA is not set
|
||||
CONFIG_TANBAC_TB0219=y
|
||||
# CONFIG_TANBAC_TB0226 is not set
|
||||
# CONFIG_TANBAC_TB0287 is not set
|
||||
CONFIG_PCI_VR41XX=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
||||
|
@ -184,6 +185,7 @@ CONFIG_SYSVIPC_SYSCTL=y
|
|||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
# CONFIG_RELAY is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
|
@ -375,7 +377,7 @@ CONFIG_FIB_RULES=y
|
|||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_FW_LOADER=m
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
|
||||
#
|
||||
|
@ -415,7 +417,6 @@ CONFIG_BLK_DEV_RAM=y
|
|||
CONFIG_BLK_DEV_RAM_COUNT=16
|
||||
CONFIG_BLK_DEV_RAM_SIZE=4096
|
||||
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
|
||||
|
@ -646,7 +647,7 @@ CONFIG_LEGACY_PTY_COUNT=256
|
|||
# CONFIG_DTLK is not set
|
||||
# CONFIG_R3964 is not set
|
||||
# CONFIG_APPLICOM is not set
|
||||
CONFIG_TANBAC_TB0219=y
|
||||
CONFIG_GPIO_TB0219=y
|
||||
# CONFIG_DRM is not set
|
||||
CONFIG_GPIO_VR41XX=y
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
|
@ -678,6 +679,11 @@ CONFIG_GPIO_VR41XX=y
|
|||
# CONFIG_HWMON is not set
|
||||
# CONFIG_HWMON_VID is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
|
@ -692,7 +698,7 @@ CONFIG_GPIO_VR41XX=y
|
|||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_FIRMWARE_EDID is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
# CONFIG_FB is not set
|
||||
|
||||
#
|
||||
|
@ -700,7 +706,6 @@ CONFIG_GPIO_VR41XX=y
|
|||
#
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
|
@ -831,6 +836,7 @@ CONFIG_USB_MON=y
|
|||
# CONFIG_USB_SISUSBVGA is not set
|
||||
# CONFIG_USB_LD is not set
|
||||
# CONFIG_USB_TRANCEVIBRATOR is not set
|
||||
# CONFIG_USB_IOWARRIOR is not set
|
||||
# CONFIG_USB_TEST is not set
|
||||
|
||||
#
|
|
@ -12,7 +12,8 @@
|
|||
|
||||
extern void prom_putchar(char);
|
||||
|
||||
static void early_console_write(struct console *con, const char *s, unsigned n)
|
||||
static void __init
|
||||
early_console_write(struct console *con, const char *s, unsigned n)
|
||||
{
|
||||
while (n-- && *s) {
|
||||
if (*s == '\n')
|
||||
|
@ -22,14 +23,20 @@ static void early_console_write(struct console *con, const char *s, unsigned n)
|
|||
}
|
||||
}
|
||||
|
||||
static struct console early_console = {
|
||||
static struct console early_console __initdata = {
|
||||
.name = "early",
|
||||
.write = early_console_write,
|
||||
.flags = CON_PRINTBUFFER | CON_BOOT,
|
||||
.index = -1
|
||||
};
|
||||
|
||||
static int early_console_initialized __initdata;
|
||||
|
||||
void __init setup_early_printk(void)
|
||||
{
|
||||
if (early_console_initialized)
|
||||
return;
|
||||
early_console_initialized = 1;
|
||||
|
||||
register_console(&early_console);
|
||||
}
|
||||
|
|
|
@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = {
|
|||
};
|
||||
|
||||
|
||||
void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
|
||||
void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
|
||||
{
|
||||
extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
|
||||
|
||||
_icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000);
|
||||
_icctrl_msc = (unsigned long) ioremap (icubase, 0x40000);
|
||||
|
||||
/* Reset interrupt controller - initialises all registers to 0 */
|
||||
MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
|
||||
|
@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
|
|||
|
||||
switch (imp->im_type) {
|
||||
case MSC01_IRQ_EDGE:
|
||||
set_irq_chip(base+n, &msc_edgeirq_type);
|
||||
set_irq_chip(irqbase+n, &msc_edgeirq_type);
|
||||
if (cpu_has_veic)
|
||||
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
|
||||
else
|
||||
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
|
||||
break;
|
||||
case MSC01_IRQ_LEVEL:
|
||||
set_irq_chip(base+n, &msc_levelirq_type);
|
||||
set_irq_chip(irqbase+n, &msc_levelirq_type);
|
||||
if (cpu_has_veic)
|
||||
MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
|
||||
else
|
||||
|
@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
|
|||
}
|
||||
}
|
||||
|
||||
irq_base = base;
|
||||
irq_base = irqbase;
|
||||
|
||||
MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
|
||||
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
|
||||
static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
|
||||
|
||||
int __devinit allocate_irqno(void)
|
||||
int allocate_irqno(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
|
@ -59,7 +59,7 @@ void __init alloc_legacy_irqno(void)
|
|||
BUG_ON(test_and_set_bit(i, irq_map));
|
||||
}
|
||||
|
||||
void __devinit free_irqno(unsigned int irq)
|
||||
void free_irqno(unsigned int irq)
|
||||
{
|
||||
smp_mb__before_clear_bit();
|
||||
clear_bit(irq, irq_map);
|
||||
|
|
|
@ -306,7 +306,7 @@ static unsigned int __init calibrate_hpt(void)
|
|||
|
||||
struct clocksource clocksource_mips = {
|
||||
.name = "MIPS",
|
||||
.mask = 0xffffffff,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
|
|
|
@ -927,9 +927,9 @@ asmlinkage void do_reserved(struct pt_regs *regs)
|
|||
(regs->cp0_cause & 0x7f) >> 2);
|
||||
}
|
||||
|
||||
asmlinkage void do_default_vi(struct pt_regs *regs)
|
||||
static asmlinkage void do_default_vi(void)
|
||||
{
|
||||
show_regs(regs);
|
||||
show_regs(get_irq_regs());
|
||||
panic("Caught unexpected vectored interrupt.");
|
||||
}
|
||||
|
||||
|
@ -1128,7 +1128,7 @@ void mips_srs_free(int set)
|
|||
clear_bit(set, &sr->sr_allocated);
|
||||
}
|
||||
|
||||
static void *set_vi_srs_handler(int n, void *addr, int srs)
|
||||
static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
|
||||
{
|
||||
unsigned long handler;
|
||||
unsigned long old_handler = vi_handlers[n];
|
||||
|
@ -1217,7 +1217,7 @@ static void *set_vi_srs_handler(int n, void *addr, int srs)
|
|||
return (void *)old_handler;
|
||||
}
|
||||
|
||||
void *set_vi_handler(int n, void *addr)
|
||||
void *set_vi_handler(int n, vi_handler_t addr)
|
||||
{
|
||||
return set_vi_srs_handler(n, addr, 0);
|
||||
}
|
||||
|
|
|
@ -9,4 +9,4 @@ obj-y += iomap.o
|
|||
obj-$(CONFIG_PCI) += iomap-pci.o
|
||||
|
||||
# libgcc-style stuff needed in the kernel
|
||||
lib-y += ashldi3.o ashrdi3.o lshrdi3.o
|
||||
lib-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o
|
||||
|
|
19
arch/mips/lib/ucmpdi2.c
Normal file
19
arch/mips/lib/ucmpdi2.c
Normal file
|
@ -0,0 +1,19 @@
|
|||
#include <linux/module.h>
|
||||
|
||||
#include "libgcc.h"
|
||||
|
||||
word_type __ucmpdi2 (unsigned long a, unsigned long b)
|
||||
{
|
||||
const DWunion au = {.ll = a};
|
||||
const DWunion bu = {.ll = b};
|
||||
|
||||
if ((unsigned int) au.s.high < (unsigned int) bu.s.high)
|
||||
return 0;
|
||||
else if ((unsigned int) au.s.high > (unsigned int) bu.s.high)
|
||||
return 2;
|
||||
if ((unsigned int) au.s.low < (unsigned int) bu.s.low)
|
||||
return 0;
|
||||
else if ((unsigned int) au.s.low > (unsigned int) bu.s.low)
|
||||
return 2;
|
||||
return 1;
|
||||
}
|
|
@ -311,16 +311,21 @@ void __init arch_init_irq(void)
|
|||
if (!cpu_has_veic)
|
||||
mips_cpu_irq_init();
|
||||
|
||||
switch(mips_revision_corid) {
|
||||
case MIPS_REVISION_CORID_CORE_MSC:
|
||||
case MIPS_REVISION_CORID_CORE_FPGA2:
|
||||
case MIPS_REVISION_CORID_CORE_FPGA3:
|
||||
case MIPS_REVISION_CORID_CORE_24K:
|
||||
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
|
||||
switch(mips_revision_sconid) {
|
||||
case MIPS_REVISION_SCON_SOCIT:
|
||||
case MIPS_REVISION_SCON_ROCIT:
|
||||
if (cpu_has_veic)
|
||||
init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
|
||||
init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
|
||||
else
|
||||
init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
|
||||
init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
|
||||
break;
|
||||
|
||||
case MIPS_REVISION_SCON_SOCITSC:
|
||||
case MIPS_REVISION_SCON_SOCITSCP:
|
||||
if (cpu_has_veic)
|
||||
init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
|
||||
else
|
||||
init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
|
||||
}
|
||||
|
||||
if (cpu_has_veic) {
|
||||
|
|
|
@ -80,7 +80,6 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
|
|||
pagefault_enable();
|
||||
}
|
||||
|
||||
#ifndef CONFIG_LIMITED_DMA
|
||||
/*
|
||||
* This is the same as kmap_atomic() but can map memory that doesn't
|
||||
* have a struct page associated with it.
|
||||
|
@ -99,7 +98,6 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
|
|||
|
||||
return (void*) vaddr;
|
||||
}
|
||||
#endif /* CONFIG_LIMITED_DMA */
|
||||
|
||||
struct page *__kmap_atomic_to_page(void *ptr)
|
||||
{
|
||||
|
|
|
@ -424,9 +424,6 @@ void __init mem_init(void)
|
|||
continue;
|
||||
}
|
||||
ClearPageReserved(page);
|
||||
#ifdef CONFIG_LIMITED_DMA
|
||||
set_page_address(page, lowmem_page_address(page));
|
||||
#endif
|
||||
init_page_count(page);
|
||||
__free_page(page);
|
||||
totalhigh_pages++;
|
||||
|
|
|
@ -35,24 +35,24 @@
|
|||
#include <asm/smp.h>
|
||||
#include <asm/war.h>
|
||||
|
||||
static __init int __attribute__((unused)) r45k_bvahwbug(void)
|
||||
static __init int __maybe_unused r45k_bvahwbug(void)
|
||||
{
|
||||
/* XXX: We should probe for the presence of this bug, but we don't. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int __attribute__((unused)) r4k_250MHZhwbug(void)
|
||||
static __init int __maybe_unused r4k_250MHZhwbug(void)
|
||||
{
|
||||
/* XXX: We should probe for the presence of this bug, but we don't. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int __attribute__((unused)) bcm1250_m3_war(void)
|
||||
static __init int __maybe_unused bcm1250_m3_war(void)
|
||||
{
|
||||
return BCM1250_M3_WAR;
|
||||
}
|
||||
|
||||
static __init int __attribute__((unused)) r10000_llsc_war(void)
|
||||
static __init int __maybe_unused r10000_llsc_war(void)
|
||||
{
|
||||
return R10000_LLSC_WAR;
|
||||
}
|
||||
|
@ -511,18 +511,18 @@ L_LA(_r3000_write_probe_fail)
|
|||
#define i_ehb(buf) i_sll(buf, 0, 0, 3)
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
static __init int __attribute__((unused)) in_compat_space_p(long addr)
|
||||
static __init int __maybe_unused in_compat_space_p(long addr)
|
||||
{
|
||||
/* Is this address in 32bit compat space? */
|
||||
return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
|
||||
}
|
||||
|
||||
static __init int __attribute__((unused)) rel_highest(long val)
|
||||
static __init int __maybe_unused rel_highest(long val)
|
||||
{
|
||||
return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
|
||||
}
|
||||
|
||||
static __init int __attribute__((unused)) rel_higher(long val)
|
||||
static __init int __maybe_unused rel_higher(long val)
|
||||
{
|
||||
return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
|
||||
}
|
||||
|
@ -556,8 +556,8 @@ static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
|
|||
i_lui(buf, rs, rel_hi(addr));
|
||||
}
|
||||
|
||||
static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs,
|
||||
long addr)
|
||||
static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs,
|
||||
long addr)
|
||||
{
|
||||
i_LA_mostly(buf, rs, addr);
|
||||
if (rel_lo(addr))
|
||||
|
@ -636,8 +636,8 @@ static __init void copy_handler(struct reloc *rel, struct label *lab,
|
|||
move_labels(lab, first, end, off);
|
||||
}
|
||||
|
||||
static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
|
||||
u32 *addr)
|
||||
static __init int __maybe_unused insn_has_bdelay(struct reloc *rel,
|
||||
u32 *addr)
|
||||
{
|
||||
for (; rel->lab != label_invalid; rel++) {
|
||||
if (rel->addr == addr
|
||||
|
@ -650,15 +650,15 @@ static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
|
|||
}
|
||||
|
||||
/* convenience functions for labeled branches */
|
||||
static void __init __attribute__((unused))
|
||||
static void __init __maybe_unused
|
||||
il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
|
||||
{
|
||||
r_mips_pc16(r, *p, l);
|
||||
i_bltz(p, reg, 0);
|
||||
}
|
||||
|
||||
static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r,
|
||||
enum label_id l)
|
||||
static void __init __maybe_unused il_b(u32 **p, struct reloc **r,
|
||||
enum label_id l)
|
||||
{
|
||||
r_mips_pc16(r, *p, l);
|
||||
i_b(p, 0);
|
||||
|
@ -671,7 +671,7 @@ static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg,
|
|||
i_beqz(p, reg, 0);
|
||||
}
|
||||
|
||||
static void __init __attribute__((unused))
|
||||
static void __init __maybe_unused
|
||||
il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
|
||||
{
|
||||
r_mips_pc16(r, *p, l);
|
||||
|
@ -692,7 +692,7 @@ static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
|
|||
i_bgezl(p, reg, 0);
|
||||
}
|
||||
|
||||
static void __init __attribute__((unused))
|
||||
static void __init __maybe_unused
|
||||
il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
|
||||
{
|
||||
r_mips_pc16(r, *p, l);
|
||||
|
@ -810,7 +810,7 @@ static __initdata u32 final_handler[64];
|
|||
*
|
||||
* As if we MIPS hackers wouldn't know how to nop pipelines happy ...
|
||||
*/
|
||||
static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p)
|
||||
static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
|
||||
{
|
||||
switch (current_cpu_data.cputype) {
|
||||
/* Found by experiment: R4600 v2.0 needs this, too. */
|
||||
|
@ -1098,7 +1098,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
|
|||
* TMP and PTR are scratch.
|
||||
* TMP will be clobbered, PTR will hold the pgd entry.
|
||||
*/
|
||||
static __init void __attribute__((unused))
|
||||
static __init void __maybe_unused
|
||||
build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
|
||||
{
|
||||
long pgdc = (long)pgd_current;
|
||||
|
|
|
@ -1,6 +0,0 @@
|
|||
config JAGUAR_DMALOW
|
||||
bool "Low DMA Mode"
|
||||
depends on MOMENCO_JAGUAR_ATX
|
||||
help
|
||||
Select to Y if jump JP5 is set on your board, N otherwise. Normally
|
||||
the jumper is set, so if you feel unsafe, just say Y.
|
|
@ -1,12 +0,0 @@
|
|||
#
|
||||
# Makefile for Momentum Computer's Jaguar-ATX board.
|
||||
#
|
||||
# Note! Dependencies are done automagically by 'make dep', which also
|
||||
# removes any old dependencies. DON'T put your own dependencies here
|
||||
# unless it's something special (ie not a .c file).
|
||||
#
|
||||
|
||||
obj-y += irq.o platform.o prom.o reset.o setup.o
|
||||
|
||||
obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o
|
||||
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
|
|
@ -1,125 +0,0 @@
|
|||
|
||||
#if defined(CONFIG_REMOTE_DEBUG)
|
||||
|
||||
#include <asm/serial.h> /* For the serial port location and base baud */
|
||||
|
||||
/* --- CONFIG --- */
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned int uint32;
|
||||
|
||||
/* --- END OF CONFIG --- */
|
||||
|
||||
#define UART16550_BAUD_2400 2400
|
||||
#define UART16550_BAUD_4800 4800
|
||||
#define UART16550_BAUD_9600 9600
|
||||
#define UART16550_BAUD_19200 19200
|
||||
#define UART16550_BAUD_38400 38400
|
||||
#define UART16550_BAUD_57600 57600
|
||||
#define UART16550_BAUD_115200 115200
|
||||
|
||||
#define UART16550_PARITY_NONE 0
|
||||
#define UART16550_PARITY_ODD 0x08
|
||||
#define UART16550_PARITY_EVEN 0x18
|
||||
#define UART16550_PARITY_MARK 0x28
|
||||
#define UART16550_PARITY_SPACE 0x38
|
||||
|
||||
#define UART16550_DATA_5BIT 0x0
|
||||
#define UART16550_DATA_6BIT 0x1
|
||||
#define UART16550_DATA_7BIT 0x2
|
||||
#define UART16550_DATA_8BIT 0x3
|
||||
|
||||
#define UART16550_STOP_1BIT 0x0
|
||||
#define UART16550_STOP_2BIT 0x4
|
||||
|
||||
/* ----------------------------------------------------- */
|
||||
|
||||
/* === CONFIG === */
|
||||
|
||||
/* [jsun] we use the second serial port for kdb */
|
||||
#define BASE OCELOT_SERIAL1_BASE
|
||||
#define MAX_BAUD OCELOT_BASE_BAUD
|
||||
|
||||
/* === END OF CONFIG === */
|
||||
|
||||
#define REG_OFFSET 4
|
||||
|
||||
/* register offset */
|
||||
#define OFS_RCV_BUFFER 0
|
||||
#define OFS_TRANS_HOLD 0
|
||||
#define OFS_SEND_BUFFER 0
|
||||
#define OFS_INTR_ENABLE (1*REG_OFFSET)
|
||||
#define OFS_INTR_ID (2*REG_OFFSET)
|
||||
#define OFS_DATA_FORMAT (3*REG_OFFSET)
|
||||
#define OFS_LINE_CONTROL (3*REG_OFFSET)
|
||||
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
|
||||
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
|
||||
#define OFS_LINE_STATUS (5*REG_OFFSET)
|
||||
#define OFS_MODEM_STATUS (6*REG_OFFSET)
|
||||
#define OFS_RS232_INPUT (6*REG_OFFSET)
|
||||
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
|
||||
|
||||
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
|
||||
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
|
||||
|
||||
|
||||
/* memory-mapped read/write of the port */
|
||||
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
|
||||
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
|
||||
|
||||
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
|
||||
{
|
||||
/* disable interrupts */
|
||||
UART16550_WRITE(OFS_INTR_ENABLE, 0);
|
||||
|
||||
/* set up baud rate */
|
||||
{
|
||||
uint32 divisor;
|
||||
|
||||
/* set DIAB bit */
|
||||
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
|
||||
|
||||
/* set divisor */
|
||||
divisor = MAX_BAUD / baud;
|
||||
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
|
||||
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
|
||||
|
||||
/* clear DIAB bit */
|
||||
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
|
||||
}
|
||||
|
||||
/* set data format */
|
||||
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
|
||||
}
|
||||
|
||||
static int remoteDebugInitialized = 0;
|
||||
|
||||
uint8 getDebugChar(void)
|
||||
{
|
||||
if (!remoteDebugInitialized) {
|
||||
remoteDebugInitialized = 1;
|
||||
debugInit(UART16550_BAUD_38400,
|
||||
UART16550_DATA_8BIT,
|
||||
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
|
||||
}
|
||||
|
||||
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
|
||||
return UART16550_READ(OFS_RCV_BUFFER);
|
||||
}
|
||||
|
||||
|
||||
int putDebugChar(uint8 byte)
|
||||
{
|
||||
if (!remoteDebugInitialized) {
|
||||
remoteDebugInitialized = 1;
|
||||
debugInit(UART16550_BAUD_38400,
|
||||
UART16550_DATA_8BIT,
|
||||
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
|
||||
}
|
||||
|
||||
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
|
||||
UART16550_WRITE(OFS_SEND_BUFFER, byte);
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,94 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2002 Momentum Computer, Inc.
|
||||
* Author: Matthew Dharm, mdharm@momenco.com
|
||||
*
|
||||
* Based on work by:
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & STATUSF_IP0)
|
||||
do_IRQ(0);
|
||||
else if (pending & STATUSF_IP1)
|
||||
do_IRQ(1);
|
||||
else if (pending & STATUSF_IP2)
|
||||
do_IRQ(2);
|
||||
else if (pending & STATUSF_IP3)
|
||||
do_IRQ(3);
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(4);
|
||||
else if (pending & STATUSF_IP5)
|
||||
do_IRQ(5);
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(6);
|
||||
else if (pending & STATUSF_IP7)
|
||||
ll_timer_interrupt(7);
|
||||
else {
|
||||
/*
|
||||
* Now look at the extended interrupts
|
||||
*/
|
||||
pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
|
||||
if (pending & STATUSF_IP8)
|
||||
ll_mv64340_irq();
|
||||
}
|
||||
}
|
||||
|
||||
static struct irqaction cascade_mv64340 = {
|
||||
no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
/*
|
||||
* Clear all of the interrupts while we change the able around a bit.
|
||||
* int-handler is not on bootstrap
|
||||
*/
|
||||
clear_c0_status(ST0_IM);
|
||||
|
||||
mips_cpu_irq_init();
|
||||
rm7k_cpu_irq_init();
|
||||
|
||||
/* set up the cascading interrupts */
|
||||
setup_irq(8, &cascade_mv64340);
|
||||
|
||||
mv64340_irq_init(16);
|
||||
|
||||
set_c0_status(ST0_IM);
|
||||
}
|
|
@ -1,101 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2001, 2002, 2004 Ralf Baechle
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/major.h>
|
||||
#include <linux/termios.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/tty.h>
|
||||
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <asm/serial.h>
|
||||
|
||||
/* SUPERIO uart register map */
|
||||
struct ja_uartregs {
|
||||
union {
|
||||
volatile u8 pad0[3];
|
||||
volatile u8 rbr; /* read only, DLAB == 0 */
|
||||
volatile u8 pad1[3];
|
||||
volatile u8 thr; /* write only, DLAB == 0 */
|
||||
volatile u8 pad2[3];
|
||||
volatile u8 dll; /* DLAB == 1 */
|
||||
} u1;
|
||||
union {
|
||||
volatile u8 pad0[3];
|
||||
volatile u8 ier; /* DLAB == 0 */
|
||||
volatile u8 pad1[3];
|
||||
volatile u8 dlm; /* DLAB == 1 */
|
||||
} u2;
|
||||
union {
|
||||
volatile u8 pad0[3];
|
||||
volatile u8 iir; /* read only */
|
||||
volatile u8 pad1[3];
|
||||
volatile u8 fcr; /* write only */
|
||||
} u3;
|
||||
volatile u8 pad0[3];
|
||||
volatile u8 iu_lcr;
|
||||
volatile u8 pad1[3];
|
||||
volatile u8 iu_mcr;
|
||||
volatile u8 pad2[3];
|
||||
volatile u8 iu_lsr;
|
||||
volatile u8 pad3[3];
|
||||
volatile u8 iu_msr;
|
||||
volatile u8 pad4[3];
|
||||
volatile u8 iu_scr;
|
||||
} ja_uregs_t;
|
||||
|
||||
#define iu_rbr u1.rbr
|
||||
#define iu_thr u1.thr
|
||||
#define iu_dll u1.dll
|
||||
#define iu_ier u2.ier
|
||||
#define iu_dlm u2.dlm
|
||||
#define iu_iir u3.iir
|
||||
#define iu_fcr u3.fcr
|
||||
|
||||
extern unsigned long uart_base;
|
||||
|
||||
static inline struct ja_uartregs *console_uart(void)
|
||||
{
|
||||
return (struct ja_uartregs *) (uart_base + 0x23UL);
|
||||
}
|
||||
|
||||
void prom_putchar(char c)
|
||||
{
|
||||
struct ja_uartregs *uart = console_uart();
|
||||
|
||||
while ((uart->iu_lsr & 0x20) == 0);
|
||||
uart->iu_thr = c;
|
||||
}
|
||||
|
||||
static void inline ja_console_probe(void)
|
||||
{
|
||||
struct uart_port up;
|
||||
|
||||
/*
|
||||
* Register to interrupt zero because we share the interrupt with
|
||||
* the serial driver which we don't properly support yet.
|
||||
*/
|
||||
memset(&up, 0, sizeof(up));
|
||||
up.membase = (unsigned char *) uart_base + 0x23UL;
|
||||
up.irq = JAGUAR_ATX_SERIAL1_IRQ;
|
||||
up.uartclk = JAGUAR_ATX_UART_CLK;
|
||||
up.regshift = 2;
|
||||
up.iotype = UPIO_MEM;
|
||||
up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
|
||||
up.line = 0;
|
||||
|
||||
if (early_serial_setup(&up))
|
||||
printk(KERN_ERR "Early serial init of port 0 failed\n");
|
||||
}
|
||||
|
||||
__init void ja_setup_console(void)
|
||||
{
|
||||
ja_console_probe();
|
||||
}
|
|
@ -1,54 +0,0 @@
|
|||
/*
|
||||
* Jaguar-ATX Board Register Definitions
|
||||
*
|
||||
* (C) 2002 Momentum Computer Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef __JAGUAR_ATX_FPGA_H__
|
||||
#define __JAGUAR_ATX_FPGA_H__
|
||||
|
||||
#define JAGUAR_ATX_REG_BOARDREV 0x0
|
||||
#define JAGUAR_ATX_REG_FPGA_REV 0x1
|
||||
#define JAGUAR_ATX_REG_FPGA_TYPE 0x2
|
||||
#define JAGUAR_ATX_REG_RESET_STATUS 0x3
|
||||
#define JAGUAR_ATX_REG_BOARD_STATUS 0x4
|
||||
#define JAGUAR_ATX_REG_RESERVED1 0x5
|
||||
#define JAGUAR_ATX_REG_SET 0x6
|
||||
#define JAGUAR_ATX_REG_CLR 0x7
|
||||
#define JAGUAR_ATX_REG_EEPROM_MODE 0x9
|
||||
#define JAGUAR_ATX_REG_RESERVED2 0xa
|
||||
#define JAGUAR_ATX_REG_RESERVED3 0xb
|
||||
#define JAGUAR_ATX_REG_RESERVED4 0xc
|
||||
#define JAGUAR_ATX_REG_PHY_INTSTAT 0xd
|
||||
#define JAGUAR_ATX_REG_RESERVED5 0xe
|
||||
#define JAGUAR_ATX_REG_RESERVED6 0xf
|
||||
|
||||
#define JAGUAR_ATX_CS0_ADDR 0xfc000000L
|
||||
|
||||
extern unsigned long ja_fpga_base;
|
||||
|
||||
#define __FPGA_REG_TO_ADDR(reg) \
|
||||
((void *) ja_fpga_base + JAGUAR_ATX_REG_##reg)
|
||||
#define JAGUAR_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
|
||||
#define JAGUAR_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
|
||||
|
||||
#endif
|
|
@ -1,208 +0,0 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/if_ether.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/mv643xx.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "jaguar_atx_fpga.h"
|
||||
|
||||
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
|
||||
|
||||
static struct resource mv643xx_eth_shared_resources[] = {
|
||||
[0] = {
|
||||
.name = "ethernet shared base",
|
||||
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
|
||||
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
|
||||
MV643XX_ETH_SHARED_REGS_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device mv643xx_eth_shared_device = {
|
||||
.name = MV643XX_ETH_SHARED_NAME,
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
|
||||
.resource = mv643xx_eth_shared_resources,
|
||||
};
|
||||
|
||||
#define MV_SRAM_BASE 0xfe000000UL
|
||||
#define MV_SRAM_SIZE (256 * 1024)
|
||||
|
||||
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
|
||||
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
|
||||
|
||||
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
|
||||
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
|
||||
|
||||
#define MV64x60_IRQ_ETH_0 48
|
||||
#define MV64x60_IRQ_ETH_1 49
|
||||
#define MV64x60_IRQ_ETH_2 50
|
||||
|
||||
static struct resource mv64x60_eth0_resources[] = {
|
||||
[0] = {
|
||||
.name = "eth0 irq",
|
||||
.start = MV64x60_IRQ_ETH_0,
|
||||
.end = MV64x60_IRQ_ETH_0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mv643xx_eth_platform_data eth0_pd = {
|
||||
.port_number = 0,
|
||||
|
||||
.tx_sram_addr = MV_SRAM_BASE_ETH0,
|
||||
.tx_sram_size = MV_SRAM_TXRING_SIZE,
|
||||
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
|
||||
|
||||
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
|
||||
.rx_sram_size = MV_SRAM_RXRING_SIZE,
|
||||
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
|
||||
};
|
||||
|
||||
static struct platform_device eth0_device = {
|
||||
.name = MV643XX_ETH_NAME,
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
|
||||
.resource = mv64x60_eth0_resources,
|
||||
.dev = {
|
||||
.platform_data = ð0_pd,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource mv64x60_eth1_resources[] = {
|
||||
[0] = {
|
||||
.name = "eth1 irq",
|
||||
.start = MV64x60_IRQ_ETH_1,
|
||||
.end = MV64x60_IRQ_ETH_1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mv643xx_eth_platform_data eth1_pd = {
|
||||
.port_number = 1,
|
||||
|
||||
.tx_sram_addr = MV_SRAM_BASE_ETH1,
|
||||
.tx_sram_size = MV_SRAM_TXRING_SIZE,
|
||||
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
|
||||
|
||||
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
|
||||
.rx_sram_size = MV_SRAM_RXRING_SIZE,
|
||||
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
|
||||
};
|
||||
|
||||
static struct platform_device eth1_device = {
|
||||
.name = MV643XX_ETH_NAME,
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
|
||||
.resource = mv64x60_eth1_resources,
|
||||
.dev = {
|
||||
.platform_data = ð1_pd,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource mv64x60_eth2_resources[] = {
|
||||
[0] = {
|
||||
.name = "eth2 irq",
|
||||
.start = MV64x60_IRQ_ETH_2,
|
||||
.end = MV64x60_IRQ_ETH_2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mv643xx_eth_platform_data eth2_pd = {
|
||||
.port_number = 2,
|
||||
};
|
||||
|
||||
static struct platform_device eth2_device = {
|
||||
.name = MV643XX_ETH_NAME,
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
|
||||
.resource = mv64x60_eth2_resources,
|
||||
.dev = {
|
||||
.platform_data = ð2_pd,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
|
||||
&mv643xx_eth_shared_device,
|
||||
ð0_device,
|
||||
ð1_device,
|
||||
ð2_device,
|
||||
};
|
||||
|
||||
static u8 __init exchange_bit(u8 val, u8 cs)
|
||||
{
|
||||
/* place the data */
|
||||
JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
|
||||
udelay(1);
|
||||
|
||||
/* turn the clock on */
|
||||
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
|
||||
udelay(1);
|
||||
|
||||
/* turn the clock off and read-strobe */
|
||||
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
|
||||
|
||||
/* return the data */
|
||||
return (JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
|
||||
}
|
||||
|
||||
static void __init get_mac(char dest[6])
|
||||
{
|
||||
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
|
||||
int i,j;
|
||||
|
||||
for (i = 0; i < 12; i++)
|
||||
exchange_bit(read_opcode[i], 1);
|
||||
|
||||
for (j = 0; j < 6; j++) {
|
||||
dest[j] = 0;
|
||||
for (i = 0; i < 8; i++) {
|
||||
dest[j] <<= 1;
|
||||
dest[j] |= exchange_bit(0, 1);
|
||||
}
|
||||
}
|
||||
|
||||
/* turn off CS */
|
||||
exchange_bit(0,0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Copy and increment ethernet MAC address by a small value.
|
||||
*
|
||||
* This is useful for systems where the only one MAC address is stored in
|
||||
* non-volatile memory for multiple ports.
|
||||
*/
|
||||
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
|
||||
unsigned int add)
|
||||
{
|
||||
int i;
|
||||
|
||||
BUG_ON(add >= 256);
|
||||
|
||||
for (i = ETH_ALEN; i >= 0; i--) {
|
||||
dst[i] = src[i] + add;
|
||||
add = dst[i] < src[i]; /* compute carry */
|
||||
}
|
||||
|
||||
WARN_ON(add);
|
||||
}
|
||||
|
||||
static int __init mv643xx_eth_add_pds(void)
|
||||
{
|
||||
unsigned char mac[ETH_ALEN];
|
||||
int ret;
|
||||
|
||||
get_mac(mac);
|
||||
eth_mac_add(eth0_pd.mac_addr, mac, 0);
|
||||
eth_mac_add(eth1_pd.mac_addr, mac, 1);
|
||||
eth_mac_add(eth2_pd.mac_addr, mac, 2);
|
||||
ret = platform_add_devices(mv643xx_eth_pd_devs,
|
||||
ARRAY_SIZE(mv643xx_eth_pd_devs));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
device_initcall(mv643xx_eth_add_pds);
|
||||
|
||||
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
|
|
@ -1,210 +0,0 @@
|
|||
/*
|
||||
* Copyright 2002 Momentum Computer Inc.
|
||||
* Author: Matthew Dharm <mdharm@momenco.com>
|
||||
*
|
||||
* Louis Hamilton, Red Hat, Inc.
|
||||
* hamilton@redhat.com [MIPS64 modifications]
|
||||
*
|
||||
* Based on Ocelot Linux port, which is
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/mv643xx.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/pmon.h>
|
||||
|
||||
#include "jaguar_atx_fpga.h"
|
||||
|
||||
extern void ja_setup_console(void);
|
||||
|
||||
struct callvectors *debug_vectors;
|
||||
|
||||
extern unsigned long cpu_clock;
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Momentum Jaguar-ATX";
|
||||
}
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
|
||||
unsigned long signext(unsigned long addr)
|
||||
{
|
||||
addr &= 0xffffffff;
|
||||
return (unsigned long)((int)addr);
|
||||
}
|
||||
|
||||
void *get_arg(unsigned long args, int arc)
|
||||
{
|
||||
unsigned long ul;
|
||||
unsigned char *puc, uc;
|
||||
|
||||
args += (arc * 4);
|
||||
ul = (unsigned long)signext(args);
|
||||
puc = (unsigned char *)ul;
|
||||
if (puc == 0)
|
||||
return (void *)0;
|
||||
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
uc = *puc++;
|
||||
l = (unsigned long)uc;
|
||||
uc = *puc++;
|
||||
ul |= (((unsigned long)uc) << 8);
|
||||
uc = *puc++;
|
||||
ul |= (((unsigned long)uc) << 16);
|
||||
uc = *puc++;
|
||||
ul |= (((unsigned long)uc) << 24);
|
||||
#else
|
||||
uc = *puc++;
|
||||
ul = ((unsigned long)uc) << 24;
|
||||
uc = *puc++;
|
||||
ul |= (((unsigned long)uc) << 16);
|
||||
uc = *puc++;
|
||||
ul |= (((unsigned long)uc) << 8);
|
||||
uc = *puc++;
|
||||
ul |= ((unsigned long)uc);
|
||||
#endif
|
||||
ul = signext(ul);
|
||||
|
||||
return (void *)ul;
|
||||
}
|
||||
|
||||
char *arg64(unsigned long addrin, int arg_index)
|
||||
{
|
||||
unsigned long args;
|
||||
char *p;
|
||||
|
||||
args = signext(addrin);
|
||||
p = (char *)get_arg(args, arg_index);
|
||||
|
||||
return p;
|
||||
}
|
||||
#endif /* CONFIG_64BIT */
|
||||
|
||||
/* PMON passes arguments in C main() style */
|
||||
void __init prom_init(void)
|
||||
{
|
||||
int argc = fw_arg0;
|
||||
char **arg = (char **) fw_arg1;
|
||||
char **env = (char **) fw_arg2;
|
||||
struct callvectors *cv = (struct callvectors *) fw_arg3;
|
||||
int i;
|
||||
|
||||
#ifdef CONFIG_SERIAL_8250_CONSOLE
|
||||
// ja_setup_console(); /* The very first thing. */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
char *ptr;
|
||||
|
||||
printk("Mips64 Jaguar-ATX\n");
|
||||
/* save the PROM vectors for debugging use */
|
||||
debug_vectors = (struct callvectors *)signext((unsigned long)cv);
|
||||
|
||||
/* arg[0] is "g", the rest is boot parameters */
|
||||
arcs_cmdline[0] = '\0';
|
||||
|
||||
for (i = 1; i < argc; i++) {
|
||||
ptr = (char *)arg64((unsigned long)arg, i);
|
||||
if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
|
||||
sizeof(arcs_cmdline))
|
||||
break;
|
||||
strcat(arcs_cmdline, ptr);
|
||||
strcat(arcs_cmdline, " ");
|
||||
}
|
||||
|
||||
i = 0;
|
||||
while (1) {
|
||||
ptr = (char *)arg64((unsigned long)env, i);
|
||||
if (! ptr)
|
||||
break;
|
||||
|
||||
if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
|
||||
marvell_base = simple_strtol(ptr + strlen("gtbase="),
|
||||
NULL, 16);
|
||||
|
||||
if ((marvell_base & 0xffffffff00000000) == 0)
|
||||
marvell_base |= 0xffffffff00000000;
|
||||
|
||||
printk("marvell_base set to 0x%016lx\n", marvell_base);
|
||||
}
|
||||
if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
|
||||
cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
|
||||
NULL, 10);
|
||||
printk("cpu_clock set to %d\n", cpu_clock);
|
||||
}
|
||||
i++;
|
||||
}
|
||||
printk("arcs_cmdline: %s\n", arcs_cmdline);
|
||||
|
||||
#else /* CONFIG_64BIT */
|
||||
/* save the PROM vectors for debugging use */
|
||||
debug_vectors = cv;
|
||||
|
||||
/* arg[0] is "g", the rest is boot parameters */
|
||||
arcs_cmdline[0] = '\0';
|
||||
for (i = 1; i < argc; i++) {
|
||||
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
|
||||
>= sizeof(arcs_cmdline))
|
||||
break;
|
||||
strcat(arcs_cmdline, arg[i]);
|
||||
strcat(arcs_cmdline, " ");
|
||||
}
|
||||
|
||||
while (*env) {
|
||||
if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
|
||||
marvell_base = simple_strtol(*env + strlen("gtbase="),
|
||||
NULL, 16);
|
||||
}
|
||||
if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
|
||||
cpu_clock = simple_strtol(*env + strlen("cpuclock="),
|
||||
NULL, 10);
|
||||
}
|
||||
env++;
|
||||
}
|
||||
#endif /* CONFIG_64BIT */
|
||||
mips_machgroup = MACH_GROUP_MOMENCO;
|
||||
mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
|
||||
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
|
||||
{
|
||||
}
|
||||
|
||||
int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
|
||||
{
|
||||
/* Clear the semaphore */
|
||||
*(volatile uint32_t *)(0xbb000a68) = 0x80000000;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void prom_init_secondary(void)
|
||||
{
|
||||
clear_c0_config(CONF_CM_CMASK);
|
||||
set_c0_config(0x2);
|
||||
|
||||
clear_c0_status(ST0_IM);
|
||||
set_c0_status(0x1ffff);
|
||||
}
|
||||
|
||||
void prom_smp_finish(void)
|
||||
{
|
||||
}
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Copyright (C) 1997, 2001 Ralf Baechle
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* Copyright (C) 2002 Momentum Computer Inc.
|
||||
* Author: Matthew Dharm <mdharm@momenco.com>
|
||||
*
|
||||
* Louis Hamilton, Red Hat, Inc.
|
||||
* hamilton@redhat.com [MIPS64 modifications]
|
||||
*/
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
void momenco_jaguar_restart(char *command)
|
||||
{
|
||||
/* base address of timekeeper portion of part */
|
||||
#ifdef CONFIG_64BIT
|
||||
void *nvram = (void*) 0xfffffffffc807000;
|
||||
#else
|
||||
void *nvram = (void*) 0xfc807000;
|
||||
#endif
|
||||
/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
|
||||
writeb(0x84, nvram + 0xff7);
|
||||
|
||||
/* wait for the watchdog to go off */
|
||||
mdelay(100+(1000/16));
|
||||
|
||||
/* if the watchdog fails for some reason, let people know */
|
||||
printk(KERN_NOTICE "Watchdog reset failed\n");
|
||||
}
|
||||
|
||||
void momenco_jaguar_halt(void)
|
||||
{
|
||||
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
|
||||
while (1)
|
||||
__asm__(".set\tmips3\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
}
|
||||
|
||||
void momenco_jaguar_power_off(void)
|
||||
{
|
||||
momenco_jaguar_halt();
|
||||
}
|
|
@ -1,475 +0,0 @@
|
|||
/*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Momentum Computer Jaguar-ATX board dependent boot routines
|
||||
*
|
||||
* Copyright (C) 1996, 1997, 2001, 04, 06 Ralf Baechle (ralf@linux-mips.org)
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Copyright (C) 2001 Red Hat, Inc.
|
||||
* Copyright (C) 2002 Momentum Computer
|
||||
*
|
||||
* Author: Matthew Dharm, Momentum Computer
|
||||
* mdharm@momenco.com
|
||||
*
|
||||
* Louis Hamilton, Red Hat, Inc.
|
||||
* hamilton@redhat.com [MIPS64 modifications]
|
||||
*
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/bcd.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/mv643xx.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
#include "jaguar_atx_fpga.h"
|
||||
|
||||
extern unsigned long mv64340_sram_base;
|
||||
unsigned long cpu_clock;
|
||||
|
||||
/* These functions are used for rebooting or halting the machine*/
|
||||
extern void momenco_jaguar_restart(char *command);
|
||||
extern void momenco_jaguar_halt(void);
|
||||
extern void momenco_jaguar_power_off(void);
|
||||
|
||||
void momenco_time_init(void);
|
||||
|
||||
static char reset_reason;
|
||||
|
||||
static inline unsigned long ENTRYLO(unsigned long paddr)
|
||||
{
|
||||
return ((paddr & PAGE_MASK) |
|
||||
(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
|
||||
_CACHE_UNCACHED)) >> 6;
|
||||
}
|
||||
|
||||
void __init bus_error_init(void) { /* nothing */ }
|
||||
|
||||
/*
|
||||
* Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
|
||||
* to be hit on every IRQ anyway - there's absolutely no point in letting it be
|
||||
* a random TLB entry, as it'll just cause needless churning of the TLB. And we
|
||||
* use the other half for the serial port, which is just a PITA otherwise :)
|
||||
*
|
||||
* Device Physical Virtual
|
||||
* MV64340 Internal Regs 0xf4000000 0xf4000000
|
||||
* Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
|
||||
* NVRAM (CS1) 0xfc800000 0xfc800000
|
||||
* UARTs (CS2) 0xfd000000 0xfd000000
|
||||
* Internal SRAM 0xfe000000 0xfe000000
|
||||
* M-Systems DOC (CS3) 0xff000000 0xff000000
|
||||
*/
|
||||
|
||||
static __init void wire_stupidity_into_tlb(void)
|
||||
{
|
||||
#ifdef CONFIG_32BIT
|
||||
write_c0_wired(0);
|
||||
local_flush_tlb_all();
|
||||
|
||||
/* marvell and extra space */
|
||||
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
|
||||
0xf4000000UL, PM_64K);
|
||||
/* fpga, rtc, and uart */
|
||||
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
|
||||
0xfc000000UL, PM_16M);
|
||||
// /* m-sys and internal SRAM */
|
||||
// add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
|
||||
// 0xfe000000UL, PM_16M);
|
||||
|
||||
marvell_base = 0xf4000000;
|
||||
//mv64340_sram_base = 0xfe000000; /* Currently unused */
|
||||
#endif
|
||||
}
|
||||
|
||||
unsigned long marvell_base = 0xf4000000L;
|
||||
unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
|
||||
unsigned long uart_base = 0xfd000000L;
|
||||
static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
|
||||
|
||||
EXPORT_SYMBOL(marvell_base);
|
||||
|
||||
static __init int per_cpu_mappings(void)
|
||||
{
|
||||
marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
|
||||
ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
|
||||
uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
|
||||
rtc_base = ioremap(0xfc000000UL, 0x8000);
|
||||
// ioremap(0xfe000000, 32 << 20);
|
||||
write_c0_wired(0);
|
||||
local_flush_tlb_all();
|
||||
ja_setup_console();
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(per_cpu_mappings);
|
||||
|
||||
unsigned long m48t37y_get_time(void)
|
||||
{
|
||||
unsigned int year, month, day, hour, min, sec;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&rtc_lock, flags);
|
||||
/* stop the update */
|
||||
rtc_base[0x7ff8] = 0x40;
|
||||
|
||||
year = BCD2BIN(rtc_base[0x7fff]);
|
||||
year += BCD2BIN(rtc_base[0x7ff1]) * 100;
|
||||
|
||||
month = BCD2BIN(rtc_base[0x7ffe]);
|
||||
|
||||
day = BCD2BIN(rtc_base[0x7ffd]);
|
||||
|
||||
hour = BCD2BIN(rtc_base[0x7ffb]);
|
||||
min = BCD2BIN(rtc_base[0x7ffa]);
|
||||
sec = BCD2BIN(rtc_base[0x7ff9]);
|
||||
|
||||
/* start the update */
|
||||
rtc_base[0x7ff8] = 0x00;
|
||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
|
||||
return mktime(year, month, day, hour, min, sec);
|
||||
}
|
||||
|
||||
int m48t37y_set_time(unsigned long sec)
|
||||
{
|
||||
struct rtc_time tm;
|
||||
unsigned long flags;
|
||||
|
||||
/* convert to a more useful format -- note months count from 0 */
|
||||
to_tm(sec, &tm);
|
||||
tm.tm_mon += 1;
|
||||
|
||||
spin_lock_irqsave(&rtc_lock, flags);
|
||||
/* enable writing */
|
||||
rtc_base[0x7ff8] = 0x80;
|
||||
|
||||
/* year */
|
||||
rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
|
||||
rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
|
||||
|
||||
/* month */
|
||||
rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
|
||||
|
||||
/* day */
|
||||
rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
|
||||
|
||||
/* hour/min/sec */
|
||||
rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
|
||||
rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
|
||||
rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
|
||||
|
||||
/* day of week -- not really used, but let's keep it up-to-date */
|
||||
rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
|
||||
|
||||
/* disable writing */
|
||||
rtc_base[0x7ff8] = 0x00;
|
||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init plat_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
setup_irq(8, irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ugly but the least of all evils. TLB initialization did flush the TLB so
|
||||
* We need to setup mappings again before we can touch the RTC.
|
||||
*/
|
||||
void momenco_time_init(void)
|
||||
{
|
||||
wire_stupidity_into_tlb();
|
||||
|
||||
mips_hpt_frequency = cpu_clock / 2;
|
||||
|
||||
rtc_mips_get_time = m48t37y_get_time;
|
||||
rtc_mips_set_time = m48t37y_set_time;
|
||||
}
|
||||
|
||||
static struct resource mv_pci_io_mem0_resource = {
|
||||
.name = "MV64340 PCI0 IO MEM",
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
static struct resource mv_pci_mem0_resource = {
|
||||
.name = "MV64340 PCI0 MEM",
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
static struct mv_pci_controller mv_bus0_controller = {
|
||||
.pcic = {
|
||||
.pci_ops = &mv_pci_ops,
|
||||
.mem_resource = &mv_pci_mem0_resource,
|
||||
.io_resource = &mv_pci_io_mem0_resource,
|
||||
},
|
||||
.config_addr = MV64340_PCI_0_CONFIG_ADDR,
|
||||
.config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
|
||||
};
|
||||
|
||||
static uint32_t mv_io_base, mv_io_size;
|
||||
|
||||
static void ja_pci0_init(void)
|
||||
{
|
||||
uint32_t mem0_base, mem0_size;
|
||||
uint32_t io_base, io_size;
|
||||
|
||||
io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
|
||||
io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
|
||||
mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
|
||||
mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
|
||||
|
||||
mv_pci_io_mem0_resource.start = 0;
|
||||
mv_pci_io_mem0_resource.end = io_size - 1;
|
||||
mv_pci_mem0_resource.start = mem0_base;
|
||||
mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
|
||||
mv_bus0_controller.pcic.mem_offset = mem0_base;
|
||||
mv_bus0_controller.pcic.io_offset = 0;
|
||||
|
||||
ioport_resource.end = io_size - 1;
|
||||
|
||||
register_pci_controller(&mv_bus0_controller.pcic);
|
||||
|
||||
mv_io_base = io_base;
|
||||
mv_io_size = io_size;
|
||||
}
|
||||
|
||||
static struct resource mv_pci_io_mem1_resource = {
|
||||
.name = "MV64340 PCI1 IO MEM",
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
static struct resource mv_pci_mem1_resource = {
|
||||
.name = "MV64340 PCI1 MEM",
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
static struct mv_pci_controller mv_bus1_controller = {
|
||||
.pcic = {
|
||||
.pci_ops = &mv_pci_ops,
|
||||
.mem_resource = &mv_pci_mem1_resource,
|
||||
.io_resource = &mv_pci_io_mem1_resource,
|
||||
},
|
||||
.config_addr = MV64340_PCI_1_CONFIG_ADDR,
|
||||
.config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
|
||||
};
|
||||
|
||||
static __init void ja_pci1_init(void)
|
||||
{
|
||||
uint32_t mem0_base, mem0_size;
|
||||
uint32_t io_base, io_size;
|
||||
|
||||
io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
|
||||
io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
|
||||
mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
|
||||
mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
|
||||
|
||||
/*
|
||||
* Here we assume the I/O window of second bus to be contiguous with
|
||||
* the first. A gap is no problem but would waste address space for
|
||||
* remapping the port space.
|
||||
*/
|
||||
mv_pci_io_mem1_resource.start = mv_io_size;
|
||||
mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
|
||||
mv_pci_mem1_resource.start = mem0_base;
|
||||
mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
|
||||
mv_bus1_controller.pcic.mem_offset = mem0_base;
|
||||
mv_bus1_controller.pcic.io_offset = 0;
|
||||
|
||||
ioport_resource.end = io_base + io_size -mv_io_base - 1;
|
||||
|
||||
register_pci_controller(&mv_bus1_controller.pcic);
|
||||
|
||||
mv_io_size = io_base + io_size - mv_io_base;
|
||||
}
|
||||
|
||||
static __init int __init ja_pci_init(void)
|
||||
{
|
||||
unsigned long io_v_base;
|
||||
uint32_t enable;
|
||||
|
||||
enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
|
||||
|
||||
/*
|
||||
* We require at least one enabled I/O or PCI memory window or we
|
||||
* will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
|
||||
*/
|
||||
if (enable & (0x01 << 9) || enable & (0x01 << 10))
|
||||
ja_pci0_init();
|
||||
|
||||
if (enable & (0x01 << 14) || enable & (0x01 << 15))
|
||||
ja_pci1_init();
|
||||
|
||||
if (mv_io_size) {
|
||||
io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
|
||||
if (!io_v_base)
|
||||
panic("Could not ioremap I/O port range");
|
||||
|
||||
set_io_port_base(io_v_base);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(ja_pci_init);
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
unsigned int tmpword;
|
||||
|
||||
board_time_init = momenco_time_init;
|
||||
|
||||
_machine_restart = momenco_jaguar_restart;
|
||||
_machine_halt = momenco_jaguar_halt;
|
||||
pm_power_off = momenco_jaguar_power_off;
|
||||
|
||||
/*
|
||||
* initrd_start = (unsigned long)jaguar_initrd_start;
|
||||
* initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size;
|
||||
* initrd_below_start_ok = 1;
|
||||
*/
|
||||
|
||||
wire_stupidity_into_tlb();
|
||||
|
||||
/*
|
||||
* shut down ethernet ports, just to be sure our memory doesn't get
|
||||
* corrupted by random ethernet traffic.
|
||||
*/
|
||||
MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
|
||||
MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
|
||||
MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
|
||||
MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
|
||||
MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
|
||||
MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
|
||||
while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
|
||||
while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
|
||||
while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
|
||||
while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
|
||||
while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
|
||||
while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
|
||||
MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
|
||||
MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
|
||||
MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
|
||||
MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
|
||||
MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2),
|
||||
MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
|
||||
|
||||
/* Turn off the Bit-Error LED */
|
||||
JAGUAR_FPGA_WRITE(0x80, CLR);
|
||||
|
||||
tmpword = JAGUAR_FPGA_READ(BOARDREV);
|
||||
if (tmpword < 26)
|
||||
printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
|
||||
'A'+tmpword);
|
||||
else
|
||||
printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
|
||||
tmpword);
|
||||
|
||||
tmpword = JAGUAR_FPGA_READ(FPGA_REV);
|
||||
printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
|
||||
tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
|
||||
printk("Reset reason: 0x%x\n", tmpword);
|
||||
switch (tmpword) {
|
||||
case 0x1:
|
||||
printk(" - Power-up reset\n");
|
||||
break;
|
||||
case 0x2:
|
||||
printk(" - Push-button reset\n");
|
||||
break;
|
||||
case 0x8:
|
||||
printk(" - Watchdog reset\n");
|
||||
break;
|
||||
case 0x10:
|
||||
printk(" - JTAG reset\n");
|
||||
break;
|
||||
default:
|
||||
printk(" - Unknown reset cause\n");
|
||||
}
|
||||
reset_reason = tmpword;
|
||||
JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
|
||||
|
||||
tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
|
||||
printk("Board Status register: 0x%02x\n", tmpword);
|
||||
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
|
||||
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
|
||||
|
||||
/* 256MiB of RM9000x2 DDR */
|
||||
// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
|
||||
|
||||
/* 128MiB of MV-64340 DDR */
|
||||
// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
|
||||
|
||||
/* XXX Memory configuration should be picked up from PMON2k */
|
||||
#ifdef CONFIG_JAGUAR_DMALOW
|
||||
printk("Jaguar ATX DMA-low mode set\n");
|
||||
add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
|
||||
add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
|
||||
#else
|
||||
/* 128MiB of MV-64340 DDR RAM */
|
||||
printk("Jaguar ATX DMA-low mode is not set\n");
|
||||
add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
|
||||
#endif
|
||||
|
||||
#ifdef GEMDEBUG_TRACEBUFFER
|
||||
{
|
||||
unsigned int tbControl;
|
||||
tbControl =
|
||||
0 << 26 | /* post trigger delay 0 */
|
||||
0x2 << 16 | /* sequential trace mode */
|
||||
// 0x0 << 16 | /* non-sequential trace mode */
|
||||
// 0xf << 4 | /* watchpoints disabled */
|
||||
2 << 2 | /* armed */
|
||||
2 ; /* interrupt disabled */
|
||||
printk ("setting tbControl = %08lx\n", tbControl);
|
||||
write_32bit_cp0_set1_register($22, tbControl);
|
||||
__asm__ __volatile__(".set noreorder\n\t" \
|
||||
"nop; nop; nop; nop; nop; nop;\n\t" \
|
||||
"nop; nop; nop; nop; nop; nop;\n\t" \
|
||||
".set reorder\n\t");
|
||||
|
||||
}
|
||||
#endif
|
||||
}
|
|
@ -1,6 +0,0 @@
|
|||
#
|
||||
# Makefile for Momentum Computer's Ocelot-G board.
|
||||
#
|
||||
|
||||
obj-y += irq.o gt-irq.o prom.o reset.o setup.o
|
||||
obj-$(CONFIG_KGDB) += dbg_io.o
|
|
@ -1,121 +0,0 @@
|
|||
|
||||
#include <asm/serial.h> /* For the serial port location and base baud */
|
||||
|
||||
/* --- CONFIG --- */
|
||||
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned int uint32;
|
||||
|
||||
/* --- END OF CONFIG --- */
|
||||
|
||||
#define UART16550_BAUD_2400 2400
|
||||
#define UART16550_BAUD_4800 4800
|
||||
#define UART16550_BAUD_9600 9600
|
||||
#define UART16550_BAUD_19200 19200
|
||||
#define UART16550_BAUD_38400 38400
|
||||
#define UART16550_BAUD_57600 57600
|
||||
#define UART16550_BAUD_115200 115200
|
||||
|
||||
#define UART16550_PARITY_NONE 0
|
||||
#define UART16550_PARITY_ODD 0x08
|
||||
#define UART16550_PARITY_EVEN 0x18
|
||||
#define UART16550_PARITY_MARK 0x28
|
||||
#define UART16550_PARITY_SPACE 0x38
|
||||
|
||||
#define UART16550_DATA_5BIT 0x0
|
||||
#define UART16550_DATA_6BIT 0x1
|
||||
#define UART16550_DATA_7BIT 0x2
|
||||
#define UART16550_DATA_8BIT 0x3
|
||||
|
||||
#define UART16550_STOP_1BIT 0x0
|
||||
#define UART16550_STOP_2BIT 0x4
|
||||
|
||||
/* ----------------------------------------------------- */
|
||||
|
||||
/* === CONFIG === */
|
||||
|
||||
/* [jsun] we use the second serial port for kdb */
|
||||
#define BASE OCELOT_SERIAL1_BASE
|
||||
#define MAX_BAUD OCELOT_BASE_BAUD
|
||||
|
||||
/* === END OF CONFIG === */
|
||||
|
||||
#define REG_OFFSET 4
|
||||
|
||||
/* register offset */
|
||||
#define OFS_RCV_BUFFER 0
|
||||
#define OFS_TRANS_HOLD 0
|
||||
#define OFS_SEND_BUFFER 0
|
||||
#define OFS_INTR_ENABLE (1*REG_OFFSET)
|
||||
#define OFS_INTR_ID (2*REG_OFFSET)
|
||||
#define OFS_DATA_FORMAT (3*REG_OFFSET)
|
||||
#define OFS_LINE_CONTROL (3*REG_OFFSET)
|
||||
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
|
||||
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
|
||||
#define OFS_LINE_STATUS (5*REG_OFFSET)
|
||||
#define OFS_MODEM_STATUS (6*REG_OFFSET)
|
||||
#define OFS_RS232_INPUT (6*REG_OFFSET)
|
||||
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
|
||||
|
||||
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
|
||||
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
|
||||
|
||||
|
||||
/* memory-mapped read/write of the port */
|
||||
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
|
||||
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
|
||||
|
||||
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
|
||||
{
|
||||
/* disable interrupts */
|
||||
UART16550_WRITE(OFS_INTR_ENABLE, 0);
|
||||
|
||||
/* set up baud rate */
|
||||
{
|
||||
uint32 divisor;
|
||||
|
||||
/* set DIAB bit */
|
||||
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
|
||||
|
||||
/* set divisor */
|
||||
divisor = MAX_BAUD / baud;
|
||||
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
|
||||
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
|
||||
|
||||
/* clear DIAB bit */
|
||||
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
|
||||
}
|
||||
|
||||
/* set data format */
|
||||
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
|
||||
}
|
||||
|
||||
static int remoteDebugInitialized = 0;
|
||||
|
||||
uint8 getDebugChar(void)
|
||||
{
|
||||
if (!remoteDebugInitialized) {
|
||||
remoteDebugInitialized = 1;
|
||||
debugInit(UART16550_BAUD_38400,
|
||||
UART16550_DATA_8BIT,
|
||||
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
|
||||
}
|
||||
|
||||
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
|
||||
return UART16550_READ(OFS_RCV_BUFFER);
|
||||
}
|
||||
|
||||
|
||||
int putDebugChar(uint8 byte)
|
||||
{
|
||||
if (!remoteDebugInitialized) {
|
||||
remoteDebugInitialized = 1;
|
||||
debugInit(UART16550_BAUD_38400,
|
||||
UART16550_DATA_8BIT,
|
||||
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
|
||||
}
|
||||
|
||||
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
|
||||
UART16550_WRITE(OFS_SEND_BUFFER, byte);
|
||||
return 1;
|
||||
}
|
|
@ -1,212 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* Copyright 2002 Momentum Computer
|
||||
* Author: mdharm@momenco.com
|
||||
*
|
||||
* arch/mips/momentum/ocelot_g/gt_irq.c
|
||||
* Interrupt routines for gt64240. Currently it only handles timer irq.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <asm/gt64240.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
unsigned long bus_clock;
|
||||
|
||||
/*
|
||||
* These are interrupt handlers for the GT on-chip interrupts. They
|
||||
* all come in to the MIPS on a single interrupt line, and have to
|
||||
* be handled and ack'ed differently than other MIPS interrupts.
|
||||
*/
|
||||
|
||||
#if 0
|
||||
|
||||
struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
|
||||
void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
|
||||
|
||||
/*
|
||||
* Hooks IRQ handler to the system. When the system is interrupted
|
||||
* the interrupt service routine is called.
|
||||
*
|
||||
* Inputs :
|
||||
* int_cause - The interrupt cause number. In EVB64120 two parameters
|
||||
* are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
|
||||
* bit_num - Indicates which bit number in the cause register
|
||||
* isr_ptr - Pointer to the interrupt service routine
|
||||
*/
|
||||
void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
|
||||
{
|
||||
irq_handlers[int_cause][bit_num].routine = isr_ptr;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Enables the IRQ on Galileo Chip
|
||||
*
|
||||
* Inputs :
|
||||
* int_cause - The interrupt cause number. In EVB64120 two parameters
|
||||
* are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
|
||||
* bit_num - Indicates which bit number in the cause register
|
||||
*
|
||||
* Outputs :
|
||||
* 1 if successful, 0 if failure
|
||||
*/
|
||||
int enable_galileo_irq(int int_cause, int bit_num)
|
||||
{
|
||||
if (int_cause == INT_CAUSE_MAIN)
|
||||
SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
|
||||
else if (int_cause == INT_CAUSE_HIGH)
|
||||
SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
|
||||
(1 << bit_num));
|
||||
else
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disables the IRQ on Galileo Chip
|
||||
*
|
||||
* Inputs :
|
||||
* int_cause - The interrupt cause number. In EVB64120 two parameters
|
||||
* are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
|
||||
* bit_num - Indicates which bit number in the cause register
|
||||
*
|
||||
* Outputs :
|
||||
* 1 if successful, 0 if failure
|
||||
*/
|
||||
int disable_galileo_irq(int int_cause, int bit_num)
|
||||
{
|
||||
if (int_cause == INT_CAUSE_MAIN)
|
||||
RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER,
|
||||
(1 << bit_num));
|
||||
else if (int_cause == INT_CAUSE_HIGH)
|
||||
RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
|
||||
(1 << bit_num));
|
||||
else
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
#endif /* 0 */
|
||||
|
||||
/*
|
||||
* Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
|
||||
*
|
||||
* We route the timer interrupt to P0_INT# (IRQ 6), and that's all this
|
||||
* routine can handle, for now.
|
||||
*
|
||||
* In the future, we'll route more interrupts to this pin, and that's why
|
||||
* we keep this particular structure in the function.
|
||||
*/
|
||||
|
||||
static irqreturn_t gt64240_p0int_irq(int irq, void *dev)
|
||||
{
|
||||
uint32_t irq_src, irq_src_mask;
|
||||
int handled;
|
||||
|
||||
/* get the low interrupt cause register */
|
||||
irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER);
|
||||
|
||||
/* get the mask register for this pin */
|
||||
irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW);
|
||||
|
||||
/* mask off only the interrupts we're interested in */
|
||||
irq_src = irq_src & irq_src_mask;
|
||||
|
||||
handled = IRQ_NONE;
|
||||
|
||||
/* Check for timer interrupt */
|
||||
if (irq_src & 0x00000100) {
|
||||
handled = IRQ_HANDLED;
|
||||
irq_src &= ~0x00000100;
|
||||
|
||||
/* Clear any pending cause bits */
|
||||
MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
|
||||
|
||||
/* handle the timer call */
|
||||
do_timer(1);
|
||||
#ifndef CONFIG_SMP
|
||||
update_process_times(user_mode(get_irq_regs()));
|
||||
#endif
|
||||
}
|
||||
|
||||
if (irq_src) {
|
||||
printk(KERN_INFO
|
||||
"UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n",
|
||||
irq_src);
|
||||
}
|
||||
|
||||
return handled;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes timer using galileo's built in timer.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This will ignore the standard MIPS timer interrupt handler
|
||||
* that is passed in as *irq (=irq0 in ../kernel/time.c).
|
||||
* We will do our own timer interrupt handling.
|
||||
*/
|
||||
void gt64240_time_init(void)
|
||||
{
|
||||
static struct irqaction timer;
|
||||
|
||||
/* Stop the timer -- we'll use timer #0 */
|
||||
MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0);
|
||||
|
||||
/* Load timer value for 100 Hz */
|
||||
MV_WRITE(TIMER_COUNTER0, bus_clock / 100);
|
||||
|
||||
/*
|
||||
* Create the IRQ structure entry for the timer. Since we're too early
|
||||
* in the boot process to use the "request_irq()" call, we'll hard-code
|
||||
* the values to the correct interrupt line.
|
||||
*/
|
||||
timer.handler = >64240_p0int_irq;
|
||||
timer.flags = IRQF_SHARED | IRQF_DISABLED;
|
||||
timer.name = "timer";
|
||||
timer.dev_id = NULL;
|
||||
timer.next = NULL;
|
||||
timer.mask = CPU_MASK_NONE;
|
||||
irq_desc[6].action = &timer;
|
||||
|
||||
enable_irq(6);
|
||||
|
||||
/* Clear any pending cause bits */
|
||||
MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0);
|
||||
|
||||
/* Enable the interrupt for timer 0 */
|
||||
MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1);
|
||||
|
||||
/* Enable the timer interrupt for GT-64240 pin P0_INT# */
|
||||
MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100);
|
||||
|
||||
/* Configure and start the timer */
|
||||
MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3);
|
||||
}
|
||||
|
||||
void gt64240_irq_init(void)
|
||||
{
|
||||
#if 0
|
||||
int i, j;
|
||||
|
||||
/* Reset irq handlers pointers to NULL */
|
||||
for (i = 0; i < MAX_CAUSE_REGS; i++) {
|
||||
for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) {
|
||||
irq_handlers[i][j].next = NULL;
|
||||
irq_handlers[i][j].sync = 0;
|
||||
irq_handlers[i][j].routine = NULL;
|
||||
irq_handlers[i][j].data = NULL;
|
||||
}
|
||||
}
|
||||
#endif /* 0 */
|
||||
}
|
|
@ -1,101 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
|
||||
* Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status();
|
||||
|
||||
if (pending & STATUSF_IP2)
|
||||
do_IRQ(2);
|
||||
else if (pending & STATUSF_IP3)
|
||||
do_IRQ(3);
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(4);
|
||||
else if (pending & STATUSF_IP5)
|
||||
do_IRQ(5);
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(6);
|
||||
else if (pending & STATUSF_IP7)
|
||||
do_IRQ(7);
|
||||
else {
|
||||
/*
|
||||
* Now look at the extended interrupts
|
||||
*/
|
||||
pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
|
||||
|
||||
if (pending & STATUSF_IP8)
|
||||
do_IRQ(8);
|
||||
else if (pending & STATUSF_IP9)
|
||||
do_IRQ(9);
|
||||
else if (pending & STATUSF_IP10)
|
||||
do_IRQ(10);
|
||||
else if (pending & STATUSF_IP11)
|
||||
do_IRQ(11);
|
||||
else
|
||||
spurious_interrupt();
|
||||
}
|
||||
}
|
||||
|
||||
extern void gt64240_irq_init(void);
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
/*
|
||||
* Clear all of the interrupts while we change the able around a bit.
|
||||
* int-handler is not on bootstrap
|
||||
*/
|
||||
clear_c0_status(ST0_IM);
|
||||
local_irq_disable();
|
||||
|
||||
mips_cpu_irq_init();
|
||||
rm7k_cpu_irq_init();
|
||||
|
||||
gt64240_irq_init();
|
||||
}
|
|
@ -1,30 +0,0 @@
|
|||
/*
|
||||
* Ocelot Board Register Definitions
|
||||
*
|
||||
* (C) 2001 Red Hat, Inc.
|
||||
*
|
||||
* GPL'd
|
||||
*/
|
||||
#ifndef __MOMENCO_OCELOT_PLD_H__
|
||||
#define __MOMENCO_OCELOT_PLD_H__
|
||||
|
||||
#define OCELOT_CS0_ADDR (0xfc000000)
|
||||
|
||||
#define OCELOT_REG_BOARDREV (0)
|
||||
#define OCELOT_REG_PLD1_ID (1)
|
||||
#define OCELOT_REG_PLD2_ID (2)
|
||||
#define OCELOT_REG_RESET_STATUS (3)
|
||||
#define OCELOT_REG_BOARD_STATUS (4)
|
||||
#define OCELOT_REG_CPCI_ID (5)
|
||||
#define OCELOT_REG_I2C_CTRL (8)
|
||||
#define OCELOT_REG_EEPROM_MODE (9)
|
||||
#define OCELOT_REG_INTMASK (10)
|
||||
#define OCELOT_REG_INTSTATUS (11)
|
||||
#define OCELOT_REG_INTSET (12)
|
||||
#define OCELOT_REG_INTCLR (13)
|
||||
|
||||
#define __PLD_REG_TO_ADDR(reg) ((void *) OCELOT_CS0_ADDR + OCELOT_REG_##reg)
|
||||
#define OCELOT_PLD_WRITE(x, reg) writeb(x, __PLD_REG_TO_ADDR(reg))
|
||||
#define OCELOT_PLD_READ(reg) readb(__PLD_REG_TO_ADDR(reg))
|
||||
|
||||
#endif /* __MOMENCO_OCELOT_PLD_H__ */
|
|
@ -1,84 +0,0 @@
|
|||
/*
|
||||
* Copyright 2002 Momentum Computer Inc.
|
||||
* Author: Matthew Dharm <mdharm@momenco.com>
|
||||
*
|
||||
* Based on Ocelot Linux port, which is
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/pmon.h>
|
||||
#include <asm/gt64240.h>
|
||||
|
||||
#include "ocelot_pld.h"
|
||||
|
||||
struct callvectors* debug_vectors;
|
||||
|
||||
extern unsigned long marvell_base;
|
||||
extern unsigned long bus_clock;
|
||||
|
||||
#ifdef CONFIG_GALILEO_GT64240_ETH
|
||||
extern unsigned char prom_mac_addr_base[6];
|
||||
#endif
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Momentum Ocelot";
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
int argc = fw_arg0;
|
||||
char **arg = (char **) fw_arg1;
|
||||
char **env = (char **) fw_arg2;
|
||||
struct callvectors *cv = (struct callvectors *) fw_arg3;
|
||||
int i;
|
||||
|
||||
/* save the PROM vectors for debugging use */
|
||||
debug_vectors = cv;
|
||||
|
||||
/* arg[0] is "g", the rest is boot parameters */
|
||||
arcs_cmdline[0] = '\0';
|
||||
for (i = 1; i < argc; i++) {
|
||||
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
|
||||
>= sizeof(arcs_cmdline))
|
||||
break;
|
||||
strcat(arcs_cmdline, arg[i]);
|
||||
strcat(arcs_cmdline, " ");
|
||||
}
|
||||
|
||||
mips_machgroup = MACH_GROUP_MOMENCO;
|
||||
mips_machtype = MACH_MOMENCO_OCELOT_G;
|
||||
|
||||
#ifdef CONFIG_GALILEO_GT64240_ETH
|
||||
/* get the base MAC address for on-board ethernet ports */
|
||||
memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
|
||||
#endif
|
||||
|
||||
while (*env) {
|
||||
if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
|
||||
marvell_base = simple_strtol(*env + strlen("gtbase="),
|
||||
NULL, 16);
|
||||
}
|
||||
if (strncmp("busclock", *env, strlen("busclock")) == 0) {
|
||||
bus_clock = simple_strtol(*env + strlen("busclock="),
|
||||
NULL, 10);
|
||||
}
|
||||
env++;
|
||||
}
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
|
@ -1,47 +0,0 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Copyright (C) 1997, 2001 Ralf Baechle
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*/
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
void momenco_ocelot_restart(char *command)
|
||||
{
|
||||
void *nvram = ioremap_nocache(0x2c807000, 0x1000);
|
||||
|
||||
if (!nvram) {
|
||||
printk(KERN_NOTICE "ioremap of reset register failed\n");
|
||||
return;
|
||||
}
|
||||
writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to
|
||||
assert reset in 1/16 second */
|
||||
mdelay(10+(1000/16));
|
||||
iounmap(nvram);
|
||||
printk(KERN_NOTICE "Watchdog reset failed\n");
|
||||
}
|
||||
|
||||
void momenco_ocelot_halt(void)
|
||||
{
|
||||
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
|
||||
while (1)
|
||||
__asm__(".set\tmips3\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
}
|
||||
|
||||
void momenco_ocelot_power_off(void)
|
||||
{
|
||||
momenco_ocelot_halt();
|
||||
}
|
|
@ -1,267 +0,0 @@
|
|||
/*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines
|
||||
*
|
||||
* Copyright (C) 1996, 1997, 2001 Ralf Baechle
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Copyright (C) 2001 Red Hat, Inc.
|
||||
* Copyright (C) 2002 Momentum Computer
|
||||
*
|
||||
* Author: Matthew Dharm, Momentum Computer
|
||||
* mdharm@momenco.com
|
||||
*
|
||||
* Author: RidgeRun, Inc.
|
||||
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/vmalloc.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gt64240.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/pci.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
#include "ocelot_pld.h"
|
||||
|
||||
#ifdef CONFIG_GALILEO_GT64240_ETH
|
||||
extern unsigned char prom_mac_addr_base[6];
|
||||
#endif
|
||||
|
||||
unsigned long marvell_base;
|
||||
|
||||
/* These functions are used for rebooting or halting the machine*/
|
||||
extern void momenco_ocelot_restart(char *command);
|
||||
extern void momenco_ocelot_halt(void);
|
||||
extern void momenco_ocelot_power_off(void);
|
||||
|
||||
extern void gt64240_time_init(void);
|
||||
extern void momenco_ocelot_irq_setup(void);
|
||||
|
||||
static char reset_reason;
|
||||
|
||||
static unsigned long ENTRYLO(unsigned long paddr)
|
||||
{
|
||||
return ((paddr & PAGE_MASK) |
|
||||
(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
|
||||
_CACHE_UNCACHED)) >> 6;
|
||||
}
|
||||
|
||||
/* setup code for a handoff from a version 2 PMON 2000 PROM */
|
||||
void PMON_v2_setup(void)
|
||||
{
|
||||
/* A wired TLB entry for the GT64240 and the serial port. The
|
||||
GT64240 is going to be hit on every IRQ anyway - there's
|
||||
absolutely no point in letting it be a random TLB entry, as
|
||||
it'll just cause needless churning of the TLB. And we use
|
||||
the other half for the serial port, which is just a PITA
|
||||
otherwise :)
|
||||
|
||||
Device Physical Virtual
|
||||
GT64240 Internal Regs 0xf4000000 0xe0000000
|
||||
UARTs (CS2) 0xfd000000 0xe0001000
|
||||
*/
|
||||
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
|
||||
0xf4000000, PM_64K);
|
||||
add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000),
|
||||
0xfd000000, PM_4K);
|
||||
|
||||
/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
|
||||
in the CS[012] region. We can't use ioremap() yet. The NVRAM
|
||||
is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
|
||||
|
||||
Ocelot PLD (CS0) 0xfc000000 0xe0020000
|
||||
NVRAM (CS1) 0xfc800000 0xe0030000
|
||||
*/
|
||||
add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000),
|
||||
0xfc000000, PM_64K);
|
||||
add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000),
|
||||
0xfc800000, PM_64K);
|
||||
|
||||
marvell_base = 0xf4000000;
|
||||
}
|
||||
|
||||
extern int rm7k_tcache_enabled;
|
||||
|
||||
/*
|
||||
* This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
|
||||
*/
|
||||
#define Page_Invalidate_T 0x16
|
||||
static void __init setup_l3cache(unsigned long size)
|
||||
{
|
||||
int register i;
|
||||
|
||||
printk("Enabling L3 cache...");
|
||||
|
||||
/* Enable the L3 cache in the GT64120A's CPU Configuration register */
|
||||
MV_WRITE(0, MV_READ(0) | (1<<14));
|
||||
|
||||
/* Enable the L3 cache in the CPU */
|
||||
set_c0_config(1<<12 /* CONF_TE */);
|
||||
|
||||
/* Clear the cache */
|
||||
write_c0_taglo(0);
|
||||
write_c0_taghi(0);
|
||||
|
||||
for (i=0; i < size; i+= 4096) {
|
||||
__asm__ __volatile__ (
|
||||
".set noreorder\n\t"
|
||||
".set mips3\n\t"
|
||||
"cache %1, (%0)\n\t"
|
||||
".set mips0\n\t"
|
||||
".set reorder"
|
||||
:
|
||||
: "r" (KSEG0ADDR(i)),
|
||||
"i" (Page_Invalidate_T));
|
||||
}
|
||||
|
||||
/* Let the RM7000 MM code know that the tertiary cache is enabled */
|
||||
rm7k_tcache_enabled = 1;
|
||||
|
||||
printk("Done\n");
|
||||
}
|
||||
|
||||
void __init plat_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
|
||||
unsigned int tmpword;
|
||||
|
||||
board_time_init = gt64240_time_init;
|
||||
|
||||
_machine_restart = momenco_ocelot_restart;
|
||||
_machine_halt = momenco_ocelot_halt;
|
||||
pm_power_off = momenco_ocelot_power_off;
|
||||
|
||||
/*
|
||||
* initrd_start = (unsigned long)ocelot_initrd_start;
|
||||
* initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
|
||||
* initrd_below_start_ok = 1;
|
||||
*/
|
||||
|
||||
/* do handoff reconfiguration */
|
||||
PMON_v2_setup();
|
||||
|
||||
#ifdef CONFIG_GALILEO_GT64240_ETH
|
||||
/* get the mac addr */
|
||||
memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
|
||||
#endif
|
||||
|
||||
/* Turn off the Bit-Error LED */
|
||||
OCELOT_PLD_WRITE(0x80, INTCLR);
|
||||
|
||||
tmpword = OCELOT_PLD_READ(BOARDREV);
|
||||
if (tmpword < 26)
|
||||
printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword);
|
||||
else
|
||||
printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword);
|
||||
|
||||
tmpword = OCELOT_PLD_READ(PLD1_ID);
|
||||
printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
|
||||
tmpword = OCELOT_PLD_READ(PLD2_ID);
|
||||
printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
|
||||
tmpword = OCELOT_PLD_READ(RESET_STATUS);
|
||||
printk("Reset reason: 0x%x\n", tmpword);
|
||||
reset_reason = tmpword;
|
||||
OCELOT_PLD_WRITE(0xff, RESET_STATUS);
|
||||
|
||||
tmpword = OCELOT_PLD_READ(BOARD_STATUS);
|
||||
printk("Board Status register: 0x%02x\n", tmpword);
|
||||
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
|
||||
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
|
||||
printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
|
||||
printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
|
||||
printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
|
||||
|
||||
if (tmpword&12)
|
||||
l3func((1<<(((tmpword&12) >> 2)+20)));
|
||||
|
||||
switch(tmpword &3) {
|
||||
case 3:
|
||||
/* 512MiB -- two banks of 256MiB */
|
||||
add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM);
|
||||
/*
|
||||
add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
|
||||
*/
|
||||
break;
|
||||
case 2:
|
||||
/* 256MiB -- two banks of 128MiB */
|
||||
add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM);
|
||||
add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
|
||||
break;
|
||||
case 1:
|
||||
/* 128MiB -- 64MiB per bank */
|
||||
add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
|
||||
add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
|
||||
break;
|
||||
case 0:
|
||||
/* 64MiB */
|
||||
add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
|
||||
break;
|
||||
}
|
||||
|
||||
/* FIXME: Fix up the DiskOnChip mapping */
|
||||
MV_WRITE(0x468, 0xfef73);
|
||||
}
|
||||
|
||||
/* This needs to be one of the first initcalls, because no I/O port access
|
||||
can work before this */
|
||||
|
||||
static int io_base_ioremap(void)
|
||||
{
|
||||
/* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
|
||||
unsigned long io_remap_range;
|
||||
|
||||
io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000);
|
||||
if (!io_remap_range)
|
||||
panic("Could not ioremap I/O port range");
|
||||
|
||||
set_io_port_base(io_remap_range - 0xc0000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
module_init(io_base_ioremap);
|
|
@ -30,11 +30,9 @@ obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
|
|||
obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
|
||||
obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
|
||||
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
|
||||
obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o
|
||||
obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
|
||||
obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o
|
||||
obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o
|
||||
obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o
|
||||
obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
|
||||
pci-yosemite.o
|
||||
obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o
|
||||
|
|
|
@ -17,9 +17,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
#include <asm/mach-cobalt/cobalt.h>
|
||||
|
||||
extern int cobalt_board_id;
|
||||
#include <cobalt.h>
|
||||
|
||||
static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
|
||||
{
|
||||
|
@ -115,6 +113,27 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
|
|||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
|
||||
qube_raq_galileo_fixup);
|
||||
|
||||
int cobalt_board_id;
|
||||
|
||||
static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
|
||||
{
|
||||
u8 id;
|
||||
int retval;
|
||||
|
||||
retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
|
||||
if (retval) {
|
||||
panic("Cannot read board ID");
|
||||
return;
|
||||
}
|
||||
|
||||
cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
|
||||
|
||||
printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
|
||||
qube_raq_via_board_id_fixup);
|
||||
|
||||
static char irq_tab_qube1[] __initdata = {
|
||||
[COBALT_PCICONF_CPU] = 0,
|
||||
[COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
|
||||
|
|
|
@ -1,43 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Marvell MV64340 interrupt fixup code.
|
||||
*
|
||||
* Marvell wants an NDA for their docs so this was written without
|
||||
* documentation. You've been warned.
|
||||
*
|
||||
* Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
/*
|
||||
* WARNING: Example of how _NOT_ to do it.
|
||||
*/
|
||||
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
int bus = dev->bus->number;
|
||||
|
||||
if (bus == 0 && slot == 1)
|
||||
return 3; /* PCI-X A */
|
||||
if (bus == 0 && slot == 2)
|
||||
return 4; /* PCI-X B */
|
||||
if (bus == 1 && slot == 1)
|
||||
return 5; /* PCI A */
|
||||
if (bus == 1 && slot == 2)
|
||||
return 6; /* PCI B */
|
||||
|
||||
return 0;
|
||||
panic("Whooops in pcibios_map_irq");
|
||||
}
|
||||
|
||||
/* Do platform specific device initialization at pci_enable_device() time */
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
|
@ -1,37 +0,0 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
int bus = dev->bus->number;
|
||||
|
||||
if (bus == 0 && slot == 1) /* Intel 82543 Gigabit MAC */
|
||||
return 2; /* irq_nr is 2 for INT0 */
|
||||
|
||||
if (bus == 0 && slot == 2) /* Intel 82543 Gigabit MAC */
|
||||
return 3; /* irq_nr is 3 for INT1 */
|
||||
|
||||
if (bus == 1 && slot == 3) /* Intel 21555 bridge */
|
||||
return 5; /* irq_nr is 8 for INT6 */
|
||||
|
||||
if (bus == 1 && slot == 4) /* PMC Slot */
|
||||
return 9; /* irq_nr is 9 for INT7 */
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Do platform specific device initialization at pci_enable_device() time */
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
|
@ -1,97 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
|
||||
*
|
||||
* This doesn't really fly - but I don't have a GT64240 system for testing.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <asm/gt64240.h>
|
||||
|
||||
/*
|
||||
* We assume these address ranges have been programmed into the GT-64240 by
|
||||
* the firmware. PMON in case of the Ocelot G does that. Note the size of
|
||||
* the I/O range is completly stupid; I/O mappings are limited to at most
|
||||
* 256 bytes by the PCI spec and deprecated; and just to make things worse
|
||||
* apparently many devices don't decode more than 64k of I/O space.
|
||||
*/
|
||||
|
||||
#define gt_io_size 0x20000000UL
|
||||
#define gt_io_base 0xe0000000UL
|
||||
|
||||
static struct resource gt_pci_mem0_resource = {
|
||||
.name = "MV64240 PCI0 MEM",
|
||||
.start = 0xc0000000UL,
|
||||
.end = 0xcfffffffUL,
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
static struct resource gt_pci_io_mem0_resource = {
|
||||
.name = "MV64240 PCI0 IO MEM",
|
||||
.start = 0xe0000000UL,
|
||||
.end = 0xefffffffUL,
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
static struct mv_pci_controller gt_bus0_controller = {
|
||||
.pcic = {
|
||||
.pci_ops = &mv_pci_ops,
|
||||
.mem_resource = >_pci_mem0_resource,
|
||||
.mem_offset = 0xc0000000UL,
|
||||
.io_resource = >_pci_io_mem0_resource,
|
||||
.io_offset = 0x00000000UL
|
||||
},
|
||||
.config_addr = PCI_0CONFIGURATION_ADDRESS,
|
||||
.config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
|
||||
};
|
||||
|
||||
static struct resource gt_pci_mem1_resource = {
|
||||
.name = "MV64240 PCI1 MEM",
|
||||
.start = 0xd0000000UL,
|
||||
.end = 0xdfffffffUL,
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
static struct resource gt_pci_io_mem1_resource = {
|
||||
.name = "MV64240 PCI1 IO MEM",
|
||||
.start = 0xf0000000UL,
|
||||
.end = 0xffffffffUL,
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
static struct mv_pci_controller gt_bus1_controller = {
|
||||
.pcic = {
|
||||
.pci_ops = &mv_pci_ops,
|
||||
.mem_resource = >_pci_mem1_resource,
|
||||
.mem_offset = 0xd0000000UL,
|
||||
.io_resource = >_pci_io_mem1_resource,
|
||||
.io_offset = 0x10000000UL
|
||||
},
|
||||
.config_addr = PCI_1CONFIGURATION_ADDRESS,
|
||||
.config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
|
||||
};
|
||||
|
||||
static __init int __init ocelot_g_pci_init(void)
|
||||
{
|
||||
unsigned long io_v_base;
|
||||
|
||||
if (gt_io_size) {
|
||||
io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size);
|
||||
if (!io_v_base)
|
||||
panic("Could not ioremap I/O port range");
|
||||
|
||||
set_io_port_base(io_v_base);
|
||||
}
|
||||
|
||||
register_pci_controller(>_bus0_controller.pcic);
|
||||
register_pci_controller(>_bus1_controller.pcic);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(ocelot_g_pci_init);
|
|
@ -246,7 +246,7 @@ comment "Platform RTC drivers"
|
|||
config RTC_DRV_CMOS
|
||||
tristate "PC-style 'CMOS'"
|
||||
depends on RTC_CLASS && (X86 || ALPHA || ARM26 || ARM \
|
||||
|| M32R || ATARI || POWERPC)
|
||||
|| M32R || ATARI || POWERPC || MIPS)
|
||||
help
|
||||
Say "yes" here to get direct support for the real time clock
|
||||
found in every PC or ACPI-based system, and some other boards.
|
||||
|
|
|
@ -689,7 +689,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
|
|||
}
|
||||
|
||||
#define atomic64_cmpxchg(v, o, n) \
|
||||
(((__typeof__((v)->counter)))cmpxchg(&((v)->counter), (o), (n)))
|
||||
((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
|
||||
#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
|
||||
|
||||
/**
|
||||
|
|
|
@ -119,9 +119,9 @@
|
|||
*/
|
||||
#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */
|
||||
#define MACH_MOMENCO_OCELOT 0
|
||||
#define MACH_MOMENCO_OCELOT_G 1
|
||||
#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */
|
||||
#define MACH_MOMENCO_OCELOT_C 2
|
||||
#define MACH_MOMENCO_JAGUAR_ATX 3
|
||||
#define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */
|
||||
#define MACH_MOMENCO_OCELOT_3 4
|
||||
|
||||
/*
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <asm/mipsregs.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/hazards.h>
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/current.h>
|
||||
|
@ -38,34 +39,16 @@ extern void _init_fpu(void);
|
|||
extern void _save_fp(struct task_struct *);
|
||||
extern void _restore_fp(struct task_struct *);
|
||||
|
||||
#if defined(CONFIG_CPU_SB1)
|
||||
#define __enable_fpu_hazard() \
|
||||
do { \
|
||||
asm(".set push \n\t" \
|
||||
".set mips64 \n\t" \
|
||||
".set noreorder \n\t" \
|
||||
"ssnop \n\t" \
|
||||
"bnezl $0, .+4 \n\t" \
|
||||
"ssnop \n\t" \
|
||||
".set pop"); \
|
||||
} while (0)
|
||||
#else
|
||||
#define __enable_fpu_hazard() \
|
||||
do { \
|
||||
asm("nop;nop;nop;nop"); /* max. hazard */ \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#define __enable_fpu() \
|
||||
do { \
|
||||
set_c0_status(ST0_CU1); \
|
||||
__enable_fpu_hazard(); \
|
||||
enable_fpu_hazard(); \
|
||||
} while (0)
|
||||
|
||||
#define __disable_fpu() \
|
||||
do { \
|
||||
clear_c0_status(ST0_CU1); \
|
||||
/* We don't care about the c0 hazard here */ \
|
||||
disable_fpu_hazard(); \
|
||||
} while (0)
|
||||
|
||||
#define enable_fpu() \
|
||||
|
|
|
@ -178,4 +178,36 @@ ASMMACRO(back_to_back_c0_hazard,
|
|||
|
||||
#endif
|
||||
|
||||
|
||||
/* FPU hazards */
|
||||
|
||||
#if defined(CONFIG_CPU_SB1)
|
||||
ASMMACRO(enable_fpu_hazard,
|
||||
.set push;
|
||||
.set mips64;
|
||||
.set noreorder;
|
||||
_ssnop;
|
||||
bnezl $0,.+4;
|
||||
_ssnop;
|
||||
.set pop
|
||||
)
|
||||
ASMMACRO(disable_fpu_hazard,
|
||||
)
|
||||
|
||||
#elif defined(CONFIG_CPU_MIPSR2)
|
||||
ASMMACRO(enable_fpu_hazard,
|
||||
_ehb
|
||||
)
|
||||
ASMMACRO(disable_fpu_hazard,
|
||||
_ehb
|
||||
)
|
||||
#else
|
||||
ASMMACRO(enable_fpu_hazard,
|
||||
nop; nop; nop; nop
|
||||
)
|
||||
ASMMACRO(disable_fpu_hazard,
|
||||
_ehb
|
||||
)
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_HAZARDS_H */
|
||||
|
|
|
@ -48,46 +48,6 @@ extern pte_t *pkmap_page_table;
|
|||
extern void * kmap_high(struct page *page);
|
||||
extern void kunmap_high(struct page *page);
|
||||
|
||||
/*
|
||||
* CONFIG_LIMITED_DMA is for systems with DMA limitations such as Momentum's
|
||||
* Jaguar ATX. This option exploits the highmem code in the kernel so is
|
||||
* always enabled together with CONFIG_HIGHMEM but at this time doesn't
|
||||
* actually add highmem functionality.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LIMITED_DMA
|
||||
|
||||
/*
|
||||
* These are the default functions for the no-highmem case from
|
||||
* <linux/highmem.h>
|
||||
*/
|
||||
static inline void *kmap(struct page *page)
|
||||
{
|
||||
might_sleep();
|
||||
return page_address(page);
|
||||
}
|
||||
|
||||
#define kunmap(page) do { (void) (page); } while (0)
|
||||
|
||||
static inline void *kmap_atomic(struct page *page, enum km_type type)
|
||||
{
|
||||
pagefault_disable();
|
||||
return page_address(page);
|
||||
}
|
||||
|
||||
static inline void kunmap_atomic(void *kvaddr, enum km_type type)
|
||||
{
|
||||
pagefault_enable();
|
||||
}
|
||||
|
||||
#define kmap_atomic_pfn(pfn, idx) kmap_atomic(pfn_to_page(pfn), (idx))
|
||||
|
||||
#define kmap_atomic_to_page(ptr) virt_to_page(ptr)
|
||||
|
||||
#define flush_cache_kmaps() do { } while (0)
|
||||
|
||||
#else /* LIMITED_DMA */
|
||||
|
||||
extern void *__kmap(struct page *page);
|
||||
extern void __kunmap(struct page *page);
|
||||
extern void *__kmap_atomic(struct page *page, enum km_type type);
|
||||
|
@ -103,8 +63,6 @@ extern struct page *__kmap_atomic_to_page(void *ptr);
|
|||
|
||||
#define flush_cache_kmaps() flush_cache_all()
|
||||
|
||||
#endif /* LIMITED_DMA */
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* _ASM_HIGHMEM_H */
|
||||
|
|
|
@ -69,6 +69,8 @@
|
|||
#define COBALT_BRD_ID_QUBE2 0x5
|
||||
#define COBALT_BRD_ID_RAQ2 0x6
|
||||
|
||||
extern int cobalt_board_id;
|
||||
|
||||
#define PCI_CFG_SET(devfn,where) \
|
||||
GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) | \
|
||||
(PCI_FUNC (devfn) << 8) | (where)))
|
||||
|
|
|
@ -1,45 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2003, 2004 Ralf Baechle
|
||||
*/
|
||||
#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
/*
|
||||
* Momentum Jaguar ATX always has the RM9000 processor.
|
||||
*/
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_has_mips16 0
|
||||
#define cpu_has_divec 0
|
||||
#define cpu_has_vce 0
|
||||
#define cpu_has_cache_cdex_p 0
|
||||
#define cpu_has_cache_cdex_s 0
|
||||
#define cpu_has_prefetch 1
|
||||
#define cpu_has_mcheck 0
|
||||
#define cpu_has_ejtag 0
|
||||
|
||||
#define cpu_has_llsc 1
|
||||
#define cpu_has_vtag_icache 0
|
||||
#define cpu_has_dc_aliases 0
|
||||
#define cpu_has_ic_fills_f_dc 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_icache_snoops_remote_store 0
|
||||
|
||||
#define cpu_has_nofpuex 0
|
||||
#define cpu_has_64bits 1
|
||||
|
||||
#define cpu_has_inclusive_pcaches 0
|
||||
|
||||
#define cpu_dcache_line_size() 32
|
||||
#define cpu_icache_line_size() 32
|
||||
#define cpu_scache_line_size() 32
|
||||
|
||||
#define cpu_has_mips32r1 0
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
|
||||
#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
|
|
@ -1,20 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
|
||||
* Copyright (C) 2000, 2002 Maciej W. Rozycki
|
||||
* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef __ASM_MACH_JA_SPACES_H
|
||||
#define __ASM_MACH_JA_SPACES_H
|
||||
|
||||
/*
|
||||
* Memory above this physical address will be considered highmem.
|
||||
*/
|
||||
#define HIGHMEM_START 0x08000000UL
|
||||
|
||||
#include_next <spaces.h>
|
||||
|
||||
#endif /* __ASM_MACH_JA_SPACES_H */
|
|
@ -25,6 +25,10 @@
|
|||
#include <asm/mips-boards/msc01_pci.h>
|
||||
#include <asm/gt64120.h>
|
||||
|
||||
/* Mips interrupt controller found in SOCit variations */
|
||||
#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
|
||||
#define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
|
||||
|
||||
/*
|
||||
* Malta I/O ports base address for the Galileo GT64120 and Algorithmics
|
||||
* Bonito system controllers.
|
||||
|
|
|
@ -94,10 +94,7 @@
|
|||
/*
|
||||
* MIPS System controller interrupt register base.
|
||||
*
|
||||
* FIXME - are these macros specific to Malta and co or to the MSC? If the
|
||||
* latter, they should be moved elsewhere.
|
||||
*/
|
||||
#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
|
||||
|
||||
/*****************************************************************************
|
||||
* Absolute register addresses
|
||||
|
@ -144,7 +141,7 @@ typedef struct msc_irqmap {
|
|||
#define MSC01_IRQ_LEVEL 0
|
||||
#define MSC01_IRQ_EDGE 1
|
||||
|
||||
extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq);
|
||||
extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
|
||||
extern void ll_msc_irq(void);
|
||||
|
||||
#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
|
||||
|
|
|
@ -190,10 +190,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
|
|||
#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
|
||||
#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
|
||||
|
||||
#ifdef CONFIG_LIMITED_DMA
|
||||
#define WANT_PAGE_VIRTUAL
|
||||
#endif
|
||||
|
||||
#include <asm-generic/memory_model.h>
|
||||
#include <asm-generic/page.h>
|
||||
|
||||
|
|
|
@ -81,25 +81,6 @@
|
|||
#define STD_SERIAL_PORT_DEFNS
|
||||
#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
|
||||
|
||||
#ifdef CONFIG_MOMENCO_JAGUAR_ATX
|
||||
/* Ordinary NS16552 duart with a 20MHz crystal. */
|
||||
#define JAGUAR_ATX_UART_CLK 20000000
|
||||
#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
|
||||
|
||||
#define JAGUAR_ATX_SERIAL1_IRQ 6
|
||||
#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
|
||||
|
||||
#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
|
||||
{ .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \
|
||||
.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
|
||||
.iomem_base = (u8 *) base, iomem_reg_shift: 2, \
|
||||
io_type: SERIAL_IO_MEM }
|
||||
#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
|
||||
_JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
|
||||
#else
|
||||
#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MOMENCO_OCELOT_3
|
||||
#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
|
||||
#define OCELOT_3_SERIAL_IRQ 6
|
||||
|
@ -134,27 +115,6 @@
|
|||
#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MOMENCO_OCELOT_G
|
||||
/* Ordinary NS16552 duart with a 20MHz crystal. */
|
||||
#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
|
||||
|
||||
#define OCELOT_G_SERIAL1_IRQ 4
|
||||
#if 0
|
||||
#define OCELOT_G_SERIAL1_BASE 0xe0001020
|
||||
#else
|
||||
#define OCELOT_G_SERIAL1_BASE 0xfd000020
|
||||
#endif
|
||||
|
||||
#define _OCELOT_G_SERIAL_INIT(int, base) \
|
||||
{ .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
|
||||
.iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
|
||||
.io_type = SERIAL_IO_MEM }
|
||||
#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
|
||||
_OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
|
||||
#else
|
||||
#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MOMENCO_OCELOT_C
|
||||
/* Ordinary NS16552 duart with a 20MHz crystal. */
|
||||
#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
|
||||
|
@ -210,7 +170,6 @@
|
|||
IP32_SERIAL_PORT_DEFNS \
|
||||
JAZZ_SERIAL_PORT_DEFNS \
|
||||
STD_SERIAL_PORT_DEFNS \
|
||||
MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
|
||||
MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
|
||||
MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
|
||||
MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
|
||||
|
|
|
@ -464,7 +464,10 @@ static inline unsigned long __cmpxchg_local(volatile void * ptr,
|
|||
|
||||
extern void set_handler (unsigned long offset, void *addr, unsigned long len);
|
||||
extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
|
||||
extern void *set_vi_handler (int n, void *addr);
|
||||
|
||||
typedef void (*vi_handler_t)(void);
|
||||
extern void *set_vi_handler (int n, vi_handler_t addr);
|
||||
|
||||
extern void *set_except_vector(int n, void *addr);
|
||||
extern unsigned long ebase;
|
||||
extern void per_cpu_trap_init(void);
|
||||
|
|
Loading…
Reference in a new issue