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drm/amd/pm: update driver if header for smu_13_0_7
update driver if header for smu_13_0_7 Signed-off-by: lyndonli <Lyndon.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0.x
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2 changed files with 80 additions and 39 deletions
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@ -25,10 +25,10 @@
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// *** IMPORTANT ***
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// PMFW TEAM: Always increment the interface version on any change to this file
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#define SMU13_DRIVER_IF_VERSION 0x2C
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#define SMU13_DRIVER_IF_VERSION 0x35
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//Increment this version if SkuTable_t or BoardTable_t change
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#define PPTABLE_VERSION 0x20
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#define PPTABLE_VERSION 0x27
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#define NUM_GFXCLK_DPM_LEVELS 16
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#define NUM_SOCCLK_DPM_LEVELS 8
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@ -96,7 +96,7 @@
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#define FEATURE_MEM_TEMP_READ_BIT 47
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#define FEATURE_ATHUB_MMHUB_PG_BIT 48
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#define FEATURE_SOC_PCC_BIT 49
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#define FEATURE_SPARE_50_BIT 50
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#define FEATURE_EDC_PWRBRK_BIT 50
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#define FEATURE_SPARE_51_BIT 51
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#define FEATURE_SPARE_52_BIT 52
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#define FEATURE_SPARE_53_BIT 53
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@ -282,15 +282,15 @@ typedef enum {
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} I2cControllerPort_e;
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typedef enum {
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I2C_CONTROLLER_NAME_VR_GFX = 0,
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I2C_CONTROLLER_NAME_VR_SOC,
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I2C_CONTROLLER_NAME_VR_VMEMP,
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I2C_CONTROLLER_NAME_VR_VDDIO,
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I2C_CONTROLLER_NAME_LIQUID0,
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I2C_CONTROLLER_NAME_LIQUID1,
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I2C_CONTROLLER_NAME_PLX,
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I2C_CONTROLLER_NAME_OTHER,
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I2C_CONTROLLER_NAME_COUNT,
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I2C_CONTROLLER_NAME_VR_GFX = 0,
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I2C_CONTROLLER_NAME_VR_SOC,
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I2C_CONTROLLER_NAME_VR_VMEMP,
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I2C_CONTROLLER_NAME_VR_VDDIO,
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I2C_CONTROLLER_NAME_LIQUID0,
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I2C_CONTROLLER_NAME_LIQUID1,
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I2C_CONTROLLER_NAME_PLX,
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I2C_CONTROLLER_NAME_FAN_INTAKE,
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I2C_CONTROLLER_NAME_COUNT,
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} I2cControllerName_e;
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typedef enum {
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@ -302,6 +302,7 @@ typedef enum {
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I2C_CONTROLLER_THROTTLER_LIQUID0,
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I2C_CONTROLLER_THROTTLER_LIQUID1,
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I2C_CONTROLLER_THROTTLER_PLX,
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I2C_CONTROLLER_THROTTLER_FAN_INTAKE,
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I2C_CONTROLLER_THROTTLER_INA3221,
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I2C_CONTROLLER_THROTTLER_COUNT,
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} I2cControllerThrottler_e;
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@ -309,8 +310,9 @@ typedef enum {
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typedef enum {
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I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
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I2C_CONTROLLER_PROTOCOL_VR_IR35217,
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I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
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I2C_CONTROLLER_PROTOCOL_TMP_MAX31875,
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I2C_CONTROLLER_PROTOCOL_INA3221,
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I2C_CONTROLLER_PROTOCOL_TMP_MAX6604,
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I2C_CONTROLLER_PROTOCOL_COUNT,
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} I2cControllerProtocol_e;
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@ -690,6 +692,9 @@ typedef struct {
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#define PP_OD_FEATURE_UCLK_BIT 8
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#define PP_OD_FEATURE_ZERO_FAN_BIT 9
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#define PP_OD_FEATURE_TEMPERATURE_BIT 10
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#define PP_OD_FEATURE_POWER_FEATURE_CTRL_BIT 11
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#define PP_OD_FEATURE_ASIC_TDC_BIT 12
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#define PP_OD_FEATURE_COUNT 13
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typedef enum {
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PP_OD_POWER_FEATURE_ALWAYS_ENABLED,
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@ -697,6 +702,11 @@ typedef enum {
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PP_OD_POWER_FEATURE_ALWAYS_DISABLED,
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} PP_OD_POWER_FEATURE_e;
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typedef enum {
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FAN_MODE_AUTO = 0,
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FAN_MODE_MANUAL_LINEAR,
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} FanMode_e;
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typedef struct {
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uint32_t FeatureCtrlMask;
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@ -708,8 +718,8 @@ typedef struct {
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uint8_t RuntimePwrSavingFeaturesCtrl;
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//Frequency changes
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int16_t GfxclkFmin; // MHz
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int16_t GfxclkFmax; // MHz
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int16_t GfxclkFmin; // MHz
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int16_t GfxclkFmax; // MHz
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uint16_t UclkFmin; // MHz
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uint16_t UclkFmax; // MHz
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@ -730,7 +740,12 @@ typedef struct {
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uint8_t MaxOpTemp;
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uint8_t Padding[4];
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uint32_t Spare[12];
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uint16_t GfxVoltageFullCtrlMode;
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uint16_t GfxclkFullCtrlMode;
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uint16_t UclkFullCtrlMode;
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int16_t AsicTdc;
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uint32_t Spare[10];
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uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround
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} OverDriveTable_t;
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@ -748,8 +763,8 @@ typedef struct {
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uint8_t IdlePwrSavingFeaturesCtrl;
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uint8_t RuntimePwrSavingFeaturesCtrl;
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uint16_t GfxclkFmin; // MHz
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uint16_t GfxclkFmax; // MHz
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int16_t GfxclkFmin; // MHz
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int16_t GfxclkFmax; // MHz
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uint16_t UclkFmin; // MHz
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uint16_t UclkFmax; // MHz
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@ -769,7 +784,12 @@ typedef struct {
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uint8_t MaxOpTemp;
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uint8_t Padding[4];
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uint32_t Spare[12];
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uint16_t GfxVoltageFullCtrlMode;
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uint16_t GfxclkFullCtrlMode;
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uint16_t UclkFullCtrlMode;
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int16_t AsicTdc;
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uint32_t Spare[10];
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} OverDriveLimits_t;
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@ -903,7 +923,8 @@ typedef struct {
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uint16_t FanStartTempMin;
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uint16_t FanStartTempMax;
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uint32_t Spare[12];
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uint16_t PowerMinPpt0[POWER_SOURCE_COUNT];
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uint32_t Spare[11];
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} MsgLimits_t;
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@ -1086,11 +1107,13 @@ typedef struct {
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uint32_t GfxoffSpare[15];
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// GFX GPO
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float DfllBtcMasterScalerM;
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uint32_t DfllBtcMasterScalerM;
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int32_t DfllBtcMasterScalerB;
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float DfllBtcSlaveScalerM;
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uint32_t DfllBtcSlaveScalerM;
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int32_t DfllBtcSlaveScalerB;
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uint32_t GfxGpoSpare[12];
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uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg
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uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg
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uint32_t GfxGpoSpare[10];
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// GFX DCS
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@ -1106,7 +1129,10 @@ typedef struct {
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uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
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uint32_t DcsSpare[16];
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uint32_t DcsSpare[14];
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// UCLK section
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uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz
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// UCLK section
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uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations
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@ -1163,13 +1189,14 @@ typedef struct {
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uint16_t IntakeTempHighIntakeAcousticLimit;
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uint16_t IntakeTempAcouticLimitReleaseRate;
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uint16_t FanStalledTempLimitOffset;
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int16_t FanAbnormalTempLimitOffset;
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uint16_t FanStalledTriggerRpm;
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uint16_t FanAbnormalTriggerRpm;
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uint16_t FanPadding;
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uint32_t FanSpare[14];
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uint16_t FanAbnormalTriggerRpmCoeff;
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uint16_t FanAbnormalDetectionEnable;
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uint8_t FanIntakeSensorSupport;
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uint8_t FanIntakePadding[3];
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uint32_t FanSpare[13];
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// SECTION: VDD_GFX AVFS
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uint8_t OverrideGfxAvfsFuses;
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@ -1193,7 +1220,6 @@ typedef struct {
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uint32_t dGbV_dT_vmin;
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uint32_t dGbV_dT_vmax;
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//Unused: PMFW-9370
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uint32_t V2F_vmin_range_low;
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uint32_t V2F_vmin_range_high;
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uint32_t V2F_vmax_range_low;
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@ -1238,8 +1264,21 @@ typedef struct {
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// SECTION: Advanced Options
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uint32_t DebugOverrides;
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// Section: Total Board Power idle vs active coefficients
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uint8_t TotalBoardPowerSupport;
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uint8_t TotalBoardPowerPadding[3];
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int16_t TotalIdleBoardPowerM;
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int16_t TotalIdleBoardPowerB;
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int16_t TotalBoardPowerM;
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int16_t TotalBoardPowerB;
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QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT];
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QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT];
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QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT];
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// SECTION: Sku Reserved
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uint32_t Spare[64];
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uint32_t Spare[43];
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// Padding for MMHUB - do not modify this
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uint32_t MmHubPadding[8];
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@ -1304,7 +1343,8 @@ typedef struct {
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// SECTION: Clock Spread Spectrum
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// UCLK Spread Spectrum
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uint16_t UclkSpreadPadding;
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uint8_t UclkTrainingModeSpreadPercent; // Q4.4
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uint8_t UclkSpreadPadding;
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uint16_t UclkSpreadFreq; // kHz
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// UCLK Spread Spectrum
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@ -1317,11 +1357,7 @@ typedef struct {
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// Section: Memory Config
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uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e
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uint8_t PaddingMem1[3];
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// Section: Total Board Power
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uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
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uint16_t BoardPowerPadding;
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uint8_t PaddingMem1[7];
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// SECTION: UMC feature flags
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uint8_t HsrEnabled;
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uint16_t Vcn1ActivityPercentage ;
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uint32_t EnergyAccumulator;
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uint16_t AverageSocketPower ;
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uint16_t AverageSocketPower;
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uint16_t AverageTotalBoardPower;
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uint16_t AvgTemperature[TEMP_COUNT];
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uint16_t AvgTemperatureFanIntake;
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uint8_t PcieRate ;
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uint8_t PcieWidth ;
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#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5
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#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6
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#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7
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#define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8
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#define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9
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#endif
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@ -31,7 +31,7 @@
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x07
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10 0x32
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x35
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#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_10 0x1D
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#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
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