EDAC, mce_amd_inj: Cleanup and simplify README

Save us an indentation level, widen to 80 cols, make the text more
succinct and slender. Use i as the bank variable, same as what the
documentation uses.

Signed-off-by: Borislav Petkov <bp@suse.de>

drivers/edac/mce_amd_inj.c

@@ -253,37 +253,41 @@ MCE_INJECT_GET(bank);
 DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n");
 
 static const char readme_msg[] =
-	"\nDescription of the files and their usages:\n\n"
-	"status:  Set a value to be programmed into MCx_STATUS(bank)\n"
-	"\t The status bits provide insight into the type of\n"
-	"\t error that caused the MCE.\n\n"
-	"misc:	 Set value of MCx_MISC(bank)\n"
-	"\t misc register provides auxiliary info about the error. This\n"
-	"\t register is typically used for error thresholding purpose and\n"
-	"\t validity of the register is indicated by MCx_STATUS[MiscV]\n\n"
-	"addr:	 Error address value to be written to MCx_ADDR(bank)\n"
-	"\t This register is used to log address information associated\n"
-	"\t with the error.\n\n"
-	"Note:	 See respective BKDGs for the exact bit definitions of the\n"
-	"\t above registers as they mirror the MCi_[STATUS | MISC | ADDR]\n"
-	"\t hardware registers.\n\n"
-	"bank:	 Specify the bank you want to inject the error into.\n"
-	"\t The number of banks in a processor varies and is family/model\n"
-	"\t dependent. So, a sanity check performed while writing.\n"
-	"\t Writing to this file will trigger a #MC or APIC interrupts or\n"
-	"\t invoke the error decoder routines for AMD processors. The value\n"
-	"\t in 'flags' file decides which of above actions is triggered.\n\n"
-	"flags:	 Write to this file to speficy the error injection policy.\n"
-	"\t Allowed values:\n"
-	"\t\t\"sw\"  -	SW error injection, Only calls error decoder\n"
-	"\t\t\troutines to print error info in human readable format\n"
-	"\t\t\"hw\"  -	HW error injection, Forces a #MC,\n"
-	"\t\t\tcauses exception handler to handle the error\n"
-	"\t\t\tif UC or poll handler catches it if CE\n"
-	"\t\t\tWarning: Might cause system panic if MCx_STATUS[PCC]\n"
-	"\t\t\tis set. For debug purposes, consider setting\n"
-	"\t\t\t/<debugfs_mountpoint>/mce/fake_panic\n"
-	"cpu:	 The cpu to inject the error on.\n\n";
+"Description of the files and their usages:\n"
+"\n"
+"Note1: i refers to the bank number below.\n"
+"Note2: See respective BKDGs for the exact bit definitions of the files below\n"
+"as they mirror the hardware registers.\n"
+"\n"
+"status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n"
+"\t attributes of the error which caused the MCE.\n"
+"\n"
+"misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n"
+"\t used for error thresholding purposes and its validity is indicated by\n"
+"\t MCi_STATUS[MiscV].\n"
+"\n"
+"addr:\t Error address value to be written to MCi_ADDR. Log address information\n"
+"\t associated with the error.\n"
+"\n"
+"cpu:\t The CPU to inject the error on.\n"
+"\n"
+"bank:\t Specify the bank you want to inject the error into: the number of\n"
+"\t banks in a processor varies and is family/model-specific, therefore, the\n"
+"\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
+"\t injection.\n"
+"\n"
+"flags:\t Injection type to be performed. Writing to this file will trigger a\n"
+"\t real machine check, an APIC interrupt or invoke the error decoder routines\n"
+"\t for AMD processors.\n"
+"\n"
+"\t Allowed error injection types:\n"
+"\t  - \"sw\": Software error injection. Decode error to a human-readable \n"
+"\t    format only. Safe to use.\n"
+"\t  - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
+"\t    handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
+"\t    is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
+"\t    before injecting.\n"
+"\n";
 
 static ssize_t
 inj_readme_read(struct file *filp, char __user *ubuf,