mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-03 17:40:04 +00:00
drm/amd/display: Populate socclk entries for dcn3.02/3.03
[Why] Initialize socclk entries in bandwidth params for dcn302, dcn303. [How] Fetch the sockclk values from smu for the DPM levels and for the DPM levels where smu returns 0, previous level values are reported. Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
d7940911fc
commit
f30f551587
3 changed files with 14 additions and 4 deletions
|
@ -190,6 +190,10 @@ void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
|
||||||
&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
|
&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
|
||||||
&num_levels);
|
&num_levels);
|
||||||
|
|
||||||
|
/* SOCCLK */
|
||||||
|
dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,
|
||||||
|
&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
|
||||||
|
&num_levels);
|
||||||
// DPREFCLK ???
|
// DPREFCLK ???
|
||||||
|
|
||||||
/* DISPCLK */
|
/* DISPCLK */
|
||||||
|
|
|
@ -1399,10 +1399,13 @@ void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
|
||||||
dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
|
dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
|
||||||
dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
|
dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
|
||||||
dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz;
|
dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz;
|
||||||
|
if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
|
||||||
|
dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
|
||||||
|
else
|
||||||
|
dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
|
||||||
/* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */
|
/* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */
|
||||||
/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
|
/* FCLK, PHYCLK_D18, DSCCLK */
|
||||||
dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
|
dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
|
||||||
dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz;
|
|
||||||
dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
|
dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
|
||||||
}
|
}
|
||||||
/* re-init DML with updated bb */
|
/* re-init DML with updated bb */
|
||||||
|
|
|
@ -1327,10 +1327,13 @@ void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
|
||||||
dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
|
dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
|
||||||
dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
|
dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
|
||||||
dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz;
|
dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz;
|
||||||
|
if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
|
||||||
|
dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
|
||||||
|
else
|
||||||
|
dcn3_03_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
|
||||||
/* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */
|
/* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */
|
||||||
/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
|
/* FCLK, PHYCLK_D18, DSCCLK */
|
||||||
dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
|
dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
|
||||||
dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz;
|
|
||||||
dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
|
dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
|
||||||
}
|
}
|
||||||
/* re-init DML with updated bb */
|
/* re-init DML with updated bb */
|
||||||
|
|
Loading…
Reference in a new issue