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drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
In GuC submission mode, driver has to provide a list of registers to be save/restored during gpu reset, make the max no. of registers value consistent with that of the value defined in FW. If they are not in sync then register save/restore during gpu reset won't work as expected. Cc: Alex Dai <yu.dai@intel.com> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1453132776-22229-1-git-send-email-arun.siluvery@linux.intel.com Reviewed-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -370,7 +370,7 @@ struct guc_policies {
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#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
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#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
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#define GUC_REGSET_MAX_REGISTERS 20
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#define GUC_REGSET_MAX_REGISTERS 25
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#define GUC_MMIO_WHITE_LIST_START 0x24d0
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#define GUC_MMIO_WHITE_LIST_MAX 12
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#define GUC_S3_SAVE_SPACE_PAGES 10
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