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Code Issues Releases Wiki Activity

drm/amdgpu: Stop clearing kiq position during unload 

Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform
IDLE-SAVE after VF fini. CPG also needs to be active in save command.

v2: drop unused variable (Alex)

Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
YuBiao Wang 2022-11-10 14:53:10 +08:00 committed by Alex Deucher
parent 2ebf61f2cf
commit f3416dc88a
2 changed files with 10 additions and 10 deletions
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16
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@ -4392,7 +4392,6 @@ static int gfx_v11_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
uint32_t tmp;
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
@ -4411,15 +4410,14 @@ static int gfx_v11_0_hw_fini(void *handle)
amdgpu_mes_kiq_hw_fini(adev);
}
if (amdgpu_sriov_vf(adev)) {
gfx_v11_0_cp_gfx_enable(adev, false);
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
tmp &= 0xffffff00;
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
if (amdgpu_sriov_vf(adev))
/* Remove the steps disabling CPG and clearing KIQ position,
* so that CP could perform IDLE-SAVE during switch. Those
* steps are necessary to avoid a DMAR error in gfx9 but it is
* not reproduced on gfx11.
*/
return 0;
}
gfx_v11_0_cp_enable(adev, false);
gfx_v11_0_enable_gui_idle_interrupt(adev, false);

4
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
View File

@ -1253,7 +1253,9 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
if (adev->mes.ring.sched.ready)
mes_v11_0_kiq_dequeue_sched(adev);
mes_v11_0_enable(adev, false);
if (!amdgpu_sriov_vf(adev))
mes_v11_0_enable(adev, false);
return 0;
}