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drm/amdgpu: Stop clearing kiq position during unload
Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform IDLE-SAVE after VF fini. CPG also needs to be active in save command. v2: drop unused variable (Alex) Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2ebf61f2cf
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2 changed files with 10 additions and 10 deletions
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@ -4392,7 +4392,6 @@ static int gfx_v11_0_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int r;
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uint32_t tmp;
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amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
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@ -4411,15 +4410,14 @@ static int gfx_v11_0_hw_fini(void *handle)
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amdgpu_mes_kiq_hw_fini(adev);
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}
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if (amdgpu_sriov_vf(adev)) {
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gfx_v11_0_cp_gfx_enable(adev, false);
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/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
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tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
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tmp &= 0xffffff00;
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WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
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if (amdgpu_sriov_vf(adev))
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/* Remove the steps disabling CPG and clearing KIQ position,
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* so that CP could perform IDLE-SAVE during switch. Those
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* steps are necessary to avoid a DMAR error in gfx9 but it is
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* not reproduced on gfx11.
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*/
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return 0;
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}
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gfx_v11_0_cp_enable(adev, false);
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gfx_v11_0_enable_gui_idle_interrupt(adev, false);
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@ -1253,7 +1253,9 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
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if (adev->mes.ring.sched.ready)
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mes_v11_0_kiq_dequeue_sched(adev);
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if (!amdgpu_sriov_vf(adev))
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mes_v11_0_enable(adev, false);
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return 0;
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}
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