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ACPICA: Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table
ACPICA commit 2d8dc0383d3c908389053afbdc329bbd52f009ce The CXL 3.0 Specification [1] adds two new structures to the CXL Early Discovery Table (CEDT). The CEDT may include zero or more entries of these types: CXIMS: CXL XOR Interleave Math Structure Enables the host to find a targets position in an Interleave Target List when XOR Math is used. RDPAS: RCEC Downstream Post Association Structure Enables the host to locate the Downstream Port(s) that report errors to a given Root Complex Event Collector (RCEC). Link: https://www.computeexpresslink.org/spec-landing # [1] Link: https://github.com/acpica/acpica/commit/2d8dc038 Signed-off-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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1 changed files with 34 additions and 1 deletions
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@ -329,7 +329,9 @@ struct acpi_cedt_header {
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enum acpi_cedt_type {
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enum acpi_cedt_type {
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ACPI_CEDT_TYPE_CHBS = 0,
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ACPI_CEDT_TYPE_CHBS = 0,
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ACPI_CEDT_TYPE_CFMWS = 1,
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ACPI_CEDT_TYPE_CFMWS = 1,
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ACPI_CEDT_TYPE_RESERVED = 2,
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ACPI_CEDT_TYPE_CXIMS = 2,
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ACPI_CEDT_TYPE_RDPAS = 3,
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ACPI_CEDT_TYPE_RESERVED = 4,
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};
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};
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/* Values for version field above */
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/* Values for version field above */
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@ -380,6 +382,7 @@ struct acpi_cedt_cfmws_target_element {
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/* Values for Interleave Arithmetic field above */
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/* Values for Interleave Arithmetic field above */
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#define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
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#define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
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#define ACPI_CEDT_CFMWS_ARITHMETIC_XOR (1)
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/* Values for Restrictions field above */
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/* Values for Restrictions field above */
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@ -389,6 +392,36 @@ struct acpi_cedt_cfmws_target_element {
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#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
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#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
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#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
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#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
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/* 2: CXL XOR Interleave Math Structure */
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struct acpi_cedt_cxims {
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struct acpi_cedt_header header;
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u16 reserved1;
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u8 hbig;
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u8 nr_xormaps;
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u64 xormap_list[];
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};
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/* 3: CXL RCEC Downstream Port Association Structure */
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struct acpi_cedt_rdpas {
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struct acpi_cedt_header header;
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u8 reserved1;
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u16 length;
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u16 segment;
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u16 bdf;
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u8 protocol;
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u64 address;
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};
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/* Masks for bdf field above */
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#define ACPI_CEDT_RDPAS_BUS_MASK 0xff00
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#define ACPI_CEDT_RDPAS_DEVICE_MASK 0x00f8
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#define ACPI_CEDT_RDPAS_FUNCTION_MASK 0x0007
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#define ACPI_CEDT_RDPAS_PROTOCOL_IO (0)
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#define ACPI_CEDT_RDPAS_PROTOCOL_CACHEMEM (1)
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/*******************************************************************************
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/*******************************************************************************
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*
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*
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* CPEP - Corrected Platform Error Polling table (ACPI 4.0)
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* CPEP - Corrected Platform Error Polling table (ACPI 4.0)
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