ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
Add a dsb after the isb to ensure that the previous writes to the CP15 registers take effect before we enable the MMU. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume)
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mcr p15, 0, r4, c10, c2, 0 @ write PRRR
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mcr p15, 0, r4, c10, c2, 0 @ write PRRR
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mcr p15, 0, r5, c10, c2, 1 @ write NMRR
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mcr p15, 0, r5, c10, c2, 1 @ write NMRR
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isb
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isb
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dsb
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mov r0, r9 @ control register
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mov r0, r9 @ control register
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mov r2, r7, lsr #14 @ get TTB0 base
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mov r2, r7, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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mov r2, r2, lsl #14
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