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arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling
Add the GPU's OPP table. This is from the downstream ChromeOS kernel, adapted to the new upstream opp-supported-hw binning format. Also add dynamic-power-coefficient for the GPU. Also add label for mfg1 power domain. This is to be used at the board level to add a regulator supply for the power domain. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-5-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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1 changed files with 139 additions and 1 deletions
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@ -647,6 +647,142 @@ clk32k: oscillator-32k {
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clock-output-names = "clk32k";
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clock-output-names = "clk32k";
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};
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};
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gpu_opp_table: opp-table-gpu {
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compatible = "operating-points-v2";
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opp-299000000 {
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opp-hz = /bits/ 64 <299000000>;
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opp-microvolt = <612500>;
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opp-supported-hw = <0xff>;
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};
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opp-332000000 {
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opp-hz = /bits/ 64 <332000000>;
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opp-microvolt = <625000>;
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opp-supported-hw = <0xff>;
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};
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opp-366000000 {
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opp-hz = /bits/ 64 <366000000>;
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opp-microvolt = <637500>;
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opp-supported-hw = <0xff>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <643750>;
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opp-supported-hw = <0xff>;
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};
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opp-434000000 {
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opp-hz = /bits/ 64 <434000000>;
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opp-microvolt = <656250>;
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opp-supported-hw = <0xff>;
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};
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opp-484000000 {
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opp-hz = /bits/ 64 <484000000>;
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opp-microvolt = <668750>;
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opp-supported-hw = <0xff>;
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};
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opp-535000000 {
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opp-hz = /bits/ 64 <535000000>;
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opp-microvolt = <687500>;
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opp-supported-hw = <0xff>;
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};
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opp-586000000 {
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opp-hz = /bits/ 64 <586000000>;
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opp-microvolt = <700000>;
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opp-supported-hw = <0xff>;
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};
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opp-637000000 {
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opp-hz = /bits/ 64 <637000000>;
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opp-microvolt = <712500>;
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opp-supported-hw = <0xff>;
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};
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opp-690000000 {
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opp-hz = /bits/ 64 <690000000>;
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opp-microvolt = <737500>;
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opp-supported-hw = <0xff>;
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};
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opp-743000000 {
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opp-hz = /bits/ 64 <743000000>;
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opp-microvolt = <756250>;
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opp-supported-hw = <0xff>;
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};
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opp-796000000 {
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opp-hz = /bits/ 64 <796000000>;
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opp-microvolt = <781250>;
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opp-supported-hw = <0xff>;
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};
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opp-850000000 {
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opp-hz = /bits/ 64 <850000000>;
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opp-microvolt = <800000>;
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opp-supported-hw = <0xff>;
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};
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opp-900000000-3 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <850000>;
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opp-supported-hw = <0x8>;
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};
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opp-900000000-4 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <837500>;
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opp-supported-hw = <0x10>;
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};
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opp-900000000-5 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <825000>;
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opp-supported-hw = <0x30>;
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};
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opp-950000000-3 {
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opp-hz = /bits/ 64 <950000000>;
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opp-microvolt = <900000>;
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opp-supported-hw = <0x8>;
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};
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opp-950000000-4 {
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opp-hz = /bits/ 64 <950000000>;
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opp-microvolt = <875000>;
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opp-supported-hw = <0x10>;
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};
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opp-950000000-5 {
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opp-hz = /bits/ 64 <950000000>;
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opp-microvolt = <850000>;
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opp-supported-hw = <0x30>;
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};
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opp-1000000000-3 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <950000>;
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opp-supported-hw = <0x8>;
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};
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opp-1000000000-4 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <912500>;
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opp-supported-hw = <0x10>;
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};
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opp-1000000000-5 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <875000>;
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opp-supported-hw = <0x30>;
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};
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};
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pmu-a55 {
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pmu-a55 {
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compatible = "arm,cortex-a55-pmu";
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compatible = "arm,cortex-a55-pmu";
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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@ -765,7 +901,7 @@ mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
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#size-cells = <0>;
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#size-cells = <0>;
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#power-domain-cells = <1>;
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#power-domain-cells = <1>;
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power-domain@MT8186_POWER_DOMAIN_MFG1 {
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mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
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reg = <MT8186_POWER_DOMAIN_MFG1>;
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reg = <MT8186_POWER_DOMAIN_MFG1>;
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mediatek,infracfg = <&infracfg_ao>;
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mediatek,infracfg = <&infracfg_ao>;
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#address-cells = <1>;
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#address-cells = <1>;
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@ -1558,6 +1694,8 @@ gpu: gpu@13040000 {
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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nvmem-cells = <&gpu_speedbin>;
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nvmem-cells = <&gpu_speedbin>;
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nvmem-cell-names = "speed-bin";
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nvmem-cell-names = "speed-bin";
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operating-points-v2 = <&gpu_opp_table>;
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dynamic-power-coefficient = <4687>;
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status = "disabled";
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status = "disabled";
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};
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};
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