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Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git 

ath.git patches for v5.14. Major changes:

ath11k

* support for WCN6855 PCI hardware

wcn36xx

* WoWLAN support with magic packets and GTK rekeying
This commit is contained in:
Kalle Valo 2021-06-15 18:47:30 +03:00
parent 314538041b 8f78caa226
commit f39c2d1a18
33 changed files with 1046 additions and 132 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/net/wireless/ath/ath10k/ahb.c
View File

@ -442,14 +442,7 @@ static int ath10k_ahb_resource_init(struct ath10k *ar)
pdev = ar_ahb->pdev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ath10k_err(ar, "failed to get memory resource\n");
ret = -ENXIO;
goto out;
}
ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res);
ar_ahb->mem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(ar_ahb->mem)) {
ath10k_err(ar, "mem ioremap error\n");
ret = PTR_ERR(ar_ahb->mem);

2
drivers/net/wireless/ath/ath10k/htt_rx.c
View File

@ -1787,7 +1787,6 @@ static bool ath10k_htt_rx_h_frag_pn_check(struct ath10k *ar,
struct ath10k_peer *peer;
union htt_rx_pn_t *last_pn, new_pn = {0};
struct ieee80211_hdr *hdr;
bool more_frags;
u8 tid, frag_number;
u32 seq;
@ -1805,7 +1804,6 @@ static bool ath10k_htt_rx_h_frag_pn_check(struct ath10k *ar,
last_pn = &peer->frag_tids_last_pn[tid];
new_pn.pn48 = ath10k_htt_rx_h_get_pn(ar, skb, offset, enctype);
more_frags = ieee80211_has_morefrags(hdr->frame_control);
frag_number = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
seq = (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;

1
drivers/net/wireless/ath/ath10k/mac.c
View File

@ -5592,6 +5592,7 @@ static int ath10k_add_interface(struct ieee80211_hw *hw,
if (arvif->nohwcrypt &&
!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
ret = -EINVAL;
ath10k_warn(ar, "cryptmode module param needed for sw crypto\n");
goto err;
}

14
drivers/net/wireless/ath/ath10k/pci.c
View File

@ -3685,8 +3685,10 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
if (bus_params.chip_id != 0xffffffff) {
if (!ath10k_pci_chip_is_supported(pdev->device,
bus_params.chip_id))
bus_params.chip_id)) {
ret = -ENODEV;
goto err_unsupported;
}
}
}
@ -3697,11 +3699,15 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
}
bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
if (bus_params.chip_id == 0xffffffff)
if (bus_params.chip_id == 0xffffffff) {
ret = -ENODEV;
goto err_unsupported;
}
if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id))
goto err_free_irq;
if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
ret = -ENODEV;
goto err_unsupported;
}
ret = ath10k_core_register(ar, &bus_params);
if (ret) {

1
drivers/net/wireless/ath/ath10k/pci.h
View File

@ -235,7 +235,6 @@ u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
void ath10k_pci_hif_power_down(struct ath10k *ar);
int ath10k_pci_alloc_pipes(struct ath10k *ar);
void ath10k_pci_free_pipes(struct ath10k *ar);
void ath10k_pci_free_pipes(struct ath10k *ar);
void ath10k_pci_rx_replenish_retry(struct timer_list *t);
void ath10k_pci_ce_deinit(struct ath10k *ar);
void ath10k_pci_init_napi(struct ath10k *ar);

1
drivers/net/wireless/ath/ath10k/wmi.h
View File

@ -7418,7 +7418,6 @@ int ath10k_wmi_wait_for_unified_ready(struct ath10k *ar);
struct sk_buff *ath10k_wmi_alloc_skb(struct ath10k *ar, u32 len);
int ath10k_wmi_connect(struct ath10k *ar);
struct sk_buff *ath10k_wmi_alloc_skb(struct ath10k *ar, u32 len);
int ath10k_wmi_cmd_send(struct ath10k *ar, struct sk_buff *skb, u32 cmd_id);
int ath10k_wmi_cmd_send_nowait(struct ath10k *ar, struct sk_buff *skb,
u32 cmd_id);

47
drivers/net/wireless/ath/ath11k/core.c
View File

@ -70,6 +70,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.cold_boot_calib = true,
.supports_suspend = false,
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
.fix_l1ss = true,
},
{
.hw_rev = ATH11K_HW_IPQ6018_HW10,
@ -110,6 +111,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.cold_boot_calib = true,
.supports_suspend = false,
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
.fix_l1ss = true,
},
{
.name = "qca6390 hw2.0",
@ -149,6 +151,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.cold_boot_calib = false,
.supports_suspend = true,
.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
.fix_l1ss = true,
},
{
.name = "qcn9074 hw1.0",
@ -186,6 +189,47 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.cold_boot_calib = false,
.supports_suspend = false,
.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
.fix_l1ss = true,
},
{
.name = "wcn6855 hw2.0",
.hw_rev = ATH11K_HW_WCN6855_HW20,
.fw = {
.dir = "WCN6855/hw2.0",
.board_size = 256 * 1024,
.cal_size = 256 * 1024,
},
.max_radios = 3,
.bdf_addr = 0x4B0C0000,
.hw_ops = &wcn6855_ops,
.ring_mask = &ath11k_hw_ring_mask_qca6390,
.internal_sleep_clock = true,
.regs = &wcn6855_regs,
.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
.host_ce_config = ath11k_host_ce_config_qca6390,
.ce_count = 9,
.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
.target_ce_count = 9,
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
.svc_to_ce_map_len = 14,
.single_pdev_only = true,
.rxdma1_enable = false,
.num_rxmda_per_pdev = 2,
.rx_mac_buf_ring = true,
.vdev_start_delay = true,
.htt_peer_map_v2 = false,
.tcl_0_only = true,
.spectral_fft_sz = 0,
.interface_modes = BIT(NL80211_IFTYPE_STATION) |
BIT(NL80211_IFTYPE_AP),
.supports_monitor = false,
.supports_shadow_regs = true,
.idle_ps = true,
.cold_boot_calib = false,
.supports_suspend = true,
.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
.fix_l1ss = false,
},
};
@ -488,7 +532,8 @@ static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
if (len < ALIGN(ie_len, 4)) {
ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
ie_id, ie_len, len);
return -EINVAL;
ret = -EINVAL;
goto err;
}
switch (ie_id) {

1
drivers/net/wireless/ath/ath11k/core.h
View File

@ -107,6 +107,7 @@ enum ath11k_hw_rev {
ATH11K_HW_QCA6390_HW20,
ATH11K_HW_IPQ6018_HW10,
ATH11K_HW_QCN9074_HW10,
ATH11K_HW_WCN6855_HW20,
};
enum ath11k_firmware_mode {

16
drivers/net/wireless/ath/ath11k/dp.c
View File

@ -342,7 +342,6 @@ static int ath11k_dp_srng_common_setup(struct ath11k_base *ab)
struct ath11k_dp *dp = &ab->dp;
struct hal_srng *srng;
int i, ret;
u32 ring_hash_map;
ret = ath11k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
HAL_SW2WBM_RELEASE, 0, 0,
@ -439,20 +438,9 @@ static int ath11k_dp_srng_common_setup(struct ath11k_base *ab)
}
/* When hash based routing of rx packet is enabled, 32 entries to map
* the hash values to the ring will be configured. Each hash entry uses
* three bits to map to a particular ring. The ring mapping will be
* 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:Not used.
* the hash values to the ring will be configured.
*/
ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
HAL_HASH_ROUTING_RING_SW2 << 3 |
HAL_HASH_ROUTING_RING_SW3 << 6 |
HAL_HASH_ROUTING_RING_SW4 << 9 |
HAL_HASH_ROUTING_RING_SW1 << 12 |
HAL_HASH_ROUTING_RING_SW2 << 15 |
HAL_HASH_ROUTING_RING_SW3 << 18 |
HAL_HASH_ROUTING_RING_SW4 << 21;
ath11k_hal_reo_hw_setup(ab, ring_hash_map);
ab->hw_params.hw_ops->reo_setup(ab);
return 0;

10
drivers/net/wireless/ath/ath11k/hal.c
View File

@ -382,6 +382,16 @@ static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val);
if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) {
ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr);
val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
((u64)srng->ring_base_paddr >>
HAL_ADDR_MSB_REG_SHIFT)) |
FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE,
(srng->entry_size * srng->num_entries));
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
}
/* interrupt setup */
/* NOTE: IPQ8074 v2 requires the interrupt timer threshold in the
* unit of 8 usecs instead of 1 usec (as required by v1).

3
drivers/net/wireless/ath/ath11k/hal.h
View File

@ -120,6 +120,7 @@ struct ath11k_base;
#define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008
#define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c
#define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010
#define HAL_REO1_MISC_CTL 0x00000630
#define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb
#define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb
#define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id
@ -280,6 +281,7 @@ struct ath11k_base;
#define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23)
#define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2)
#define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3)
#define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17)
/* CE ring bit field mask and shift */
#define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
@ -906,7 +908,6 @@ void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
u32 start_seq, enum hal_pn_type type);
void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
struct hal_srng *srng);
void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map);
void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
struct hal_wbm_idle_scatter_list *sbuf,
u32 nsbufs, u32 tot_link_desc,

42
drivers/net/wireless/ath/ath11k/hal_rx.c
View File

@ -801,43 +801,6 @@ void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
}
}
void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map)
{
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
u32 val;
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
HAL_SRNG_RING_ID_REO2SW1) |
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
ring_hash_map));
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
ring_hash_map));
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
ring_hash_map));
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
ring_hash_map));
}
static enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
struct hal_rx_mon_ppdu_info *ppdu_info,
@ -1128,12 +1091,9 @@ ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
break;
}
case HAL_RX_MPDU_START: {
struct hal_rx_mpdu_info *mpdu_info =
(struct hal_rx_mpdu_info *)tlv_data;
u16 peer_id;
peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
__le32_to_cpu(mpdu_info->info0));
peer_id = ab->hw_params.hw_ops->mpdu_info_get_peerid(tlv_data);
if (peer_id)
ppdu_info->peer_id = peer_id;
break;

8
drivers/net/wireless/ath/ath11k/hal_rx.h
View File

@ -254,12 +254,20 @@ struct hal_rx_phyrx_rssi_legacy_info {
} __packed;
#define HAL_RX_MPDU_INFO_INFO0_PEERID GENMASK(31, 16)
#define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 GENMASK(15, 0)
struct hal_rx_mpdu_info {
__le32 rsvd0;
__le32 info0;
__le32 rsvd1[21];
} __packed;
struct hal_rx_mpdu_info_wcn6855 {
__le32 rsvd0[8];
__le32 info0;
__le32 rsvd1[14];
} __packed;
#define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
struct hal_rx_ppdu_end_duration {
__le32 rsvd0[9];

391
drivers/net/wireless/ath/ath11k/hw.c
View File

@ -10,6 +10,7 @@
#include "hw.h"
#include "core.h"
#include "ce.h"
#include "hif.h"
/* Map from pdev index to hw mac index */
static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
@ -45,6 +46,13 @@ static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab,
true);
}
static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab,
struct hal_tcl_data_cmd *tcl_cmd)
{
tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
true);
}
static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
struct target_resource_config *config)
{
@ -91,6 +99,52 @@ static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
config->num_keep_alive_pattern = 0;
}
static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab)
{
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
u32 val;
/* Each hash entry uses three bits to map to a particular ring. */
u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
HAL_HASH_ROUTING_RING_SW2 << 3 |
HAL_HASH_ROUTING_RING_SW3 << 6 |
HAL_HASH_ROUTING_RING_SW4 << 9 |
HAL_HASH_ROUTING_RING_SW1 << 12 |
HAL_HASH_ROUTING_RING_SW2 << 15 |
HAL_HASH_ROUTING_RING_SW3 << 18 |
HAL_HASH_ROUTING_RING_SW4 << 21;
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
HAL_SRNG_RING_ID_REO2SW1) |
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
ring_hash_map));
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
ring_hash_map));
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
ring_hash_map));
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
ring_hash_map));
}
static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
struct target_resource_config *config)
{
@ -489,6 +543,228 @@ static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
return &desc->u.qcn9074.msdu_payload[0];
}
static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855,
__le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
}
static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855,
__le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
}
static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
__le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
}
static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
{
return desc->u.wcn6855.hdr_status;
}
static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
{
return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
}
static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
}
static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
__le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
}
static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
__le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
}
static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
}
static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
{
return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
}
static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
}
static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
__le32_to_cpu(desc->u.wcn6855.msdu_start.info1));
}
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_SGI,
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
}
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
}
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
}
static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
{
return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data);
}
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
}
static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
__le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
}
static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
{
return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855,
__le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
}
static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
{
return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id);
}
static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
struct hal_rx_desc *ldesc)
{
memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end,
sizeof(struct rx_msdu_end_wcn6855));
memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention,
sizeof(struct rx_attention));
memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end,
sizeof(struct rx_mpdu_end));
}
static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
{
return FIELD_GET(HAL_TLV_HDR_TAG,
__le32_to_cpu(desc->u.wcn6855.mpdu_start_tag));
}
static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
{
return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id);
}
static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
{
u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1);
info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info);
}
static
struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc)
{
return &desc->u.wcn6855.attention;
}
static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
{
return &desc->u.wcn6855.msdu_payload[0];
}
static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
{
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
u32 val;
/* Each hash entry uses four bits to map to a particular ring. */
u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
HAL_HASH_ROUTING_RING_SW2 << 4 |
HAL_HASH_ROUTING_RING_SW3 << 8 |
HAL_HASH_ROUTING_RING_SW4 << 12 |
HAL_HASH_ROUTING_RING_SW1 << 16 |
HAL_HASH_ROUTING_RING_SW2 << 20 |
HAL_HASH_ROUTING_RING_SW3 << 24 |
HAL_HASH_ROUTING_RING_SW4 << 28;
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL);
val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1);
ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
HAL_DEFAULT_REO_TIMEOUT_USEC);
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
ring_hash_map);
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
ring_hash_map);
}
static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data)
{
u16 peer_id = 0;
struct hal_rx_mpdu_info *mpdu_info =
(struct hal_rx_mpdu_info *)tlv_data;
peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
__le32_to_cpu(mpdu_info->info0));
return peer_id;
}
static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data)
{
u16 peer_id = 0;
struct hal_rx_mpdu_info_wcn6855 *mpdu_info =
(struct hal_rx_mpdu_info_wcn6855 *)tlv_data;
peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855,
__le32_to_cpu(mpdu_info->info0));
return peer_id;
}
const struct ath11k_hw_ops ipq8074_ops = {
.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
.wmi_init_config = ath11k_init_wmi_config_ipq8074,
@ -521,6 +797,8 @@ const struct ath11k_hw_ops ipq8074_ops = {
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
.reo_setup = ath11k_hw_ipq8074_reo_setup,
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
};
const struct ath11k_hw_ops ipq6018_ops = {
@ -555,6 +833,8 @@ const struct ath11k_hw_ops ipq6018_ops = {
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
.reo_setup = ath11k_hw_ipq8074_reo_setup,
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
};
const struct ath11k_hw_ops qca6390_ops = {
@ -589,6 +869,8 @@ const struct ath11k_hw_ops qca6390_ops = {
.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
.reo_setup = ath11k_hw_ipq8074_reo_setup,
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
};
const struct ath11k_hw_ops qcn9074_ops = {
@ -623,6 +905,44 @@ const struct ath11k_hw_ops qcn9074_ops = {
.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
.reo_setup = ath11k_hw_ipq8074_reo_setup,
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
};
const struct ath11k_hw_ops wcn6855_ops = {
.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
.wmi_init_config = ath11k_init_wmi_config_qca6390,
.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
.tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable,
.rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu,
.rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu,
.rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes,
.rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status,
.rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid,
.rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type,
.rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type,
.rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl,
.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld,
.rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid,
.rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no,
.rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len,
.rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi,
.rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs,
.rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw,
.rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq,
.rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type,
.rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss,
.rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid,
.rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id,
.rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end,
.rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag,
.rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id,
.rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len,
.rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
.rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
.reo_setup = ath11k_hw_wcn6855_reo_setup,
.mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid,
};
#define ATH11K_TX_RING_MASK_0 0x1
@ -1688,3 +2008,74 @@ const struct ath11k_hw_regs qcn9074_regs = {
.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
};
const struct ath11k_hw_regs wcn6855_regs = {
/* SW2TCL(x) R0 ring configuration address */
.hal_tcl1_ring_base_lsb = 0x00000690,
.hal_tcl1_ring_base_msb = 0x00000694,
.hal_tcl1_ring_id = 0x00000698,
.hal_tcl1_ring_misc = 0x000006a0,
.hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
.hal_tcl1_ring_tp_addr_msb = 0x000006b0,
.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
.hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
.hal_tcl1_ring_msi1_base_msb = 0x000006dc,
.hal_tcl1_ring_msi1_data = 0x000006e0,
.hal_tcl2_ring_base_lsb = 0x000006e8,
.hal_tcl_ring_base_lsb = 0x00000798,
/* TCL STATUS ring address */
.hal_tcl_status_ring_base_lsb = 0x000008a0,
/* REO2SW(x) R0 ring configuration address */
.hal_reo1_ring_base_lsb = 0x00000244,
.hal_reo1_ring_base_msb = 0x00000248,
.hal_reo1_ring_id = 0x0000024c,
.hal_reo1_ring_misc = 0x00000254,
.hal_reo1_ring_hp_addr_lsb = 0x00000258,
.hal_reo1_ring_hp_addr_msb = 0x0000025c,
.hal_reo1_ring_producer_int_setup = 0x00000268,
.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
.hal_reo1_ring_msi1_base_msb = 0x00000290,
.hal_reo1_ring_msi1_data = 0x00000294,
.hal_reo2_ring_base_lsb = 0x0000029c,
.hal_reo1_aging_thresh_ix_0 = 0x000005bc,
.hal_reo1_aging_thresh_ix_1 = 0x000005c0,
.hal_reo1_aging_thresh_ix_2 = 0x000005c4,
.hal_reo1_aging_thresh_ix_3 = 0x000005c8,
/* REO2SW(x) R2 ring pointers (head/tail) address */
.hal_reo1_ring_hp = 0x00003030,
.hal_reo1_ring_tp = 0x00003034,
.hal_reo2_ring_hp = 0x00003038,
/* REO2TCL R0 ring configuration address */
.hal_reo_tcl_ring_base_lsb = 0x00000454,
.hal_reo_tcl_ring_hp = 0x00003060,
/* REO status address */
.hal_reo_status_ring_base_lsb = 0x0000055c,
.hal_reo_status_hp = 0x00003078,
/* WCSS relative address */
.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
.hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
.hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
/* WBM Idle address */
.hal_wbm_idle_link_ring_base_lsb = 0x00000870,
.hal_wbm_idle_link_ring_misc = 0x00000880,
/* SW2WBM release address */
.hal_wbm_release_ring_base_lsb = 0x000001e8,
/* WBM2SW release address */
.hal_wbm0_release_ring_base_lsb = 0x00000920,
.hal_wbm1_release_ring_base_lsb = 0x00000978,
/* PCIe base address */
.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
};

5
drivers/net/wireless/ath/ath11k/hw.h
View File

@ -162,6 +162,7 @@ struct ath11k_hw_params {
bool cold_boot_calib;
bool supports_suspend;
u32 hal_desc_sz;
bool fix_l1ss;
};
struct ath11k_hw_ops {
@ -199,12 +200,15 @@ struct ath11k_hw_ops {
void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
void (*reo_setup)(struct ath11k_base *ab);
u16 (*mpdu_info_get_peerid)(u8 *tlv_data);
};
extern const struct ath11k_hw_ops ipq8074_ops;
extern const struct ath11k_hw_ops ipq6018_ops;
extern const struct ath11k_hw_ops qca6390_ops;
extern const struct ath11k_hw_ops qcn9074_ops;
extern const struct ath11k_hw_ops wcn6855_ops;
extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
@ -318,5 +322,6 @@ struct ath11k_hw_regs {
extern const struct ath11k_hw_regs ipq8074_regs;
extern const struct ath11k_hw_regs qca6390_regs;
extern const struct ath11k_hw_regs qcn9074_regs;
extern const struct ath11k_hw_regs wcn6855_regs;
#endif

10
drivers/net/wireless/ath/ath11k/mac.c
View File

@ -5379,11 +5379,6 @@ ath11k_mac_update_vif_chan(struct ath11k *ar,
if (WARN_ON(!arvif->is_up))
continue;
ret = ath11k_mac_setup_bcn_tmpl(arvif);
if (ret)
ath11k_warn(ab, "failed to update bcn tmpl during csa: %d\n",
ret);
ret = ath11k_mac_vdev_restart(arvif, &vifs[i].new_ctx->def);
if (ret) {
ath11k_warn(ab, "failed to restart vdev %d: %d\n",
@ -5391,6 +5386,11 @@ ath11k_mac_update_vif_chan(struct ath11k *ar,
continue;
}
ret = ath11k_mac_setup_bcn_tmpl(arvif);
if (ret)
ath11k_warn(ab, "failed to update bcn tmpl during csa: %d\n",
ret);
ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid,
arvif->bssid);
if (ret) {

1
drivers/net/wireless/ath/ath11k/mhi.c
View File

@ -354,6 +354,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
break;
case ATH11K_HW_QCA6390_HW20:
case ATH11K_HW_WCN6855_HW20:
ath11k_mhi_config = &ath11k_mhi_config_qca6390;
break;
default:

47
drivers/net/wireless/ath/ath11k/pci.c
View File

@ -36,9 +36,11 @@
#define QCA6390_DEVICE_ID 0x1101
#define QCN9074_DEVICE_ID 0x1104
#define WCN6855_DEVICE_ID 0x1103
static const struct pci_device_id ath11k_pci_id_table[] = {
{ PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
{ PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
/* TODO: add QCN9074_DEVICE_ID) once firmware issues are resolved */
{0}
};
@ -432,7 +434,8 @@ static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
ath11k_pci_enable_ltssm(ab);
ath11k_pci_clear_all_intrs(ab);
ath11k_pci_set_wlaon_pwr_ctrl(ab);
ath11k_pci_fix_l1ss(ab);
if (ab->hw_params.fix_l1ss)
ath11k_pci_fix_l1ss(ab);
}
ath11k_mhi_clear_vector(ab);
@ -1176,12 +1179,26 @@ static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
.get_ce_msi_idx = ath11k_pci_get_ce_msi_idx,
};
static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
{
u32 soc_hw_version;
soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION);
*major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
soc_hw_version);
*minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
soc_hw_version);
ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
*major, *minor);
}
static int ath11k_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_dev)
{
struct ath11k_base *ab;
struct ath11k_pci *ab_pci;
u32 soc_hw_version, soc_hw_version_major, soc_hw_version_minor;
u32 soc_hw_version_major, soc_hw_version_minor;
int ret;
ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI,
@ -1209,15 +1226,8 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
switch (pci_dev->device) {
case QCA6390_DEVICE_ID:
soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION);
soc_hw_version_major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
soc_hw_version);
soc_hw_version_minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
soc_hw_version);
ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
soc_hw_version_major, soc_hw_version_minor);
ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
&soc_hw_version_minor);
switch (soc_hw_version_major) {
case 2:
ab->hw_rev = ATH11K_HW_QCA6390_HW20;
@ -1235,6 +1245,21 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
ab->bus_params.static_window_map = true;
ab->hw_rev = ATH11K_HW_QCN9074_HW10;
break;
case WCN6855_DEVICE_ID:
ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
&soc_hw_version_minor);
switch (soc_hw_version_major) {
case 2:
ab->hw_rev = ATH11K_HW_WCN6855_HW20;
break;
default:
dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
soc_hw_version_major, soc_hw_version_minor);
ret = -EOPNOTSUPP;
goto err_pci_free_region;
}
ab_pci->msi_config = &ath11k_msi_config[0];
break;
default:
dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
pci_dev->device);

87
drivers/net/wireless/ath/ath11k/rx_desc.h
View File

@ -368,6 +368,7 @@ struct rx_attention {
#define RX_MPDU_START_INFO2_BSSID_HIT BIT(9)
#define RX_MPDU_START_INFO2_BSSID_NUM GENMASK(13, 10)
#define RX_MPDU_START_INFO2_TID GENMASK(17, 14)
#define RX_MPDU_START_INFO2_TID_WCN6855 GENMASK(18, 15)
#define RX_MPDU_START_INFO3_REO_DEST_IND GENMASK(4, 0)
#define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ BIT(7)
@ -546,6 +547,31 @@ struct rx_mpdu_start_qcn9074 {
__le32 ht_ctrl;
} __packed;
struct rx_mpdu_start_wcn6855 {
__le32 info3;
__le32 reo_queue_desc_lo;
__le32 info4;
__le32 pn[4];
__le32 info2;
__le32 peer_meta_data;
__le16 info0;
__le16 phy_ppdu_id;
__le16 ast_index;
__le16 sw_peer_id;
__le32 info1;
__le32 info5;
__le32 info6;
__le16 frame_ctrl;
__le16 duration;
u8 addr1[ETH_ALEN];
u8 addr2[ETH_ALEN];
u8 addr3[ETH_ALEN];
__le16 seq_ctrl;
u8 addr4[ETH_ALEN];
__le16 qos_ctrl;
__le32 ht_ctrl;
} __packed;
/* rx_mpdu_start
*
* rxpcu_mpdu_filter_in_category
@ -804,6 +830,20 @@ struct rx_msdu_start_qcn9074 {
__le16 vlan_stag_c1;
} __packed;
struct rx_msdu_start_wcn6855 {
__le16 info0;
__le16 phy_ppdu_id;
__le32 info1;
__le32 info2;
__le32 toeplitz_hash;
__le32 flow_id_toeplitz;
__le32 info3;
__le32 ppdu_start_timestamp;
__le32 phy_meta_data;
__le16 vlan_ctag_ci;
__le16 vlan_stag_ci;
} __packed;
/* rx_msdu_start
*
* rxpcu_mpdu_filter_in_category
@ -988,7 +1028,9 @@ struct rx_msdu_start_qcn9074 {
#define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN GENMASK(13, 0)
#define RX_MSDU_END_INFO2_FIRST_MSDU BIT(14)
#define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855 BIT(28)
#define RX_MSDU_END_INFO2_LAST_MSDU BIT(15)
#define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855 BIT(29)
#define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT BIT(16)
#define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT BIT(17)
#define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR BIT(18)
@ -1037,6 +1079,31 @@ struct rx_msdu_end_ipq8074 {
__le16 sa_sw_peer_id;
} __packed;
struct rx_msdu_end_wcn6855 {
__le16 info0;
__le16 phy_ppdu_id;
__le16 ip_hdr_cksum;
__le16 reported_mpdu_len;
__le32 info1;
__le32 ext_wapi_pn[2];
__le32 info4;
__le32 ipv6_options_crc;
__le32 tcp_seq_num;
__le32 tcp_ack_num;
__le16 info3;
__le16 window_size;
__le32 info2;
__le16 sa_idx;
__le16 da_idx;
__le32 info5;
__le32 fse_metadata;
__le16 cce_metadata;
__le16 sa_sw_peer_id;
__le32 rule_indication[2];
__le32 info6;
__le32 info7;
} __packed;
#define RX_MSDU_END_MPDU_LENGTH_INFO GENMASK(13, 0)
#define RX_MSDU_END_INFO2_DA_OFFSET GENMASK(5, 0)
@ -1400,10 +1467,30 @@ struct hal_rx_desc_qcn9074 {
u8 msdu_payload[0];
} __packed;
struct hal_rx_desc_wcn6855 {
__le32 msdu_end_tag;
struct rx_msdu_end_wcn6855 msdu_end;
__le32 rx_attn_tag;
struct rx_attention attention;
__le32 msdu_start_tag;
struct rx_msdu_start_wcn6855 msdu_start;
u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
__le32 mpdu_start_tag;
struct rx_mpdu_start_wcn6855 mpdu_start;
__le32 mpdu_end_tag;
struct rx_mpdu_end mpdu_end;
u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
__le32 hdr_status_tag;
__le32 phy_ppdu_id;
u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
u8 msdu_payload[0];
} __packed;
struct hal_rx_desc {
union {
struct hal_rx_desc_ipq8074 ipq8074;
struct hal_rx_desc_qcn9074 qcn9074;
struct hal_rx_desc_wcn6855 wcn6855;
} u;
} __packed;

2
drivers/net/wireless/ath/ath5k/pcu.c
View File

@ -855,7 +855,7 @@ ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
}
/**
* at5k_hw_stop_rx_pcu() - Stop RX engine
* ath5k_hw_stop_rx_pcu() - Stop RX engine
* @ah: The &struct ath5k_hw
*
* Stops RX engine on PCU

4
drivers/net/wireless/ath/ath6kl/cfg80211.c
View File

@ -3303,8 +3303,8 @@ static int ath6kl_cfg80211_sscan_start(struct wiphy *wiphy,
if (ret < 0)
return ret;
} else {
ret = ath6kl_wmi_bssfilter_cmd(ar->wmi, vif->fw_vif_idx,
MATCHED_SSID_FILTER, 0);
ret = ath6kl_wmi_bssfilter_cmd(ar->wmi, vif->fw_vif_idx,
MATCHED_SSID_FILTER, 0);
if (ret < 0)
return ret;
}

5
drivers/net/wireless/ath/ath9k/main.c
View File

@ -307,6 +307,11 @@ static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
hchan = ah->curchan;
}
if (!hchan) {
fastcc = false;
hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
}
if (!ath_prepare_reset(sc))
fastcc = false;

8
drivers/net/wireless/ath/carl9170/Kconfig
View File

@ -16,13 +16,11 @@ config CARL9170
config CARL9170_LEDS
bool "SoftLED Support"
depends on CARL9170
select MAC80211_LEDS
select LEDS_CLASS
select NEW_LEDS
default y
depends on CARL9170
depends on MAC80211_LEDS
help
This option is necessary, if you want your device' LEDs to blink
This option is necessary, if you want your device's LEDs to blink.
Say Y, unless you need the LEDs for firmware debugging.

2
drivers/net/wireless/ath/hw.c
View File

@ -24,7 +24,7 @@
#define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
/**
* ath_hw_set_bssid_mask - filter out bssids we listen
* ath_hw_setbssidmask - filter out bssids we listen
*
* @common: the ath_common struct for the device.
*

2
drivers/net/wireless/ath/wcn36xx/dxe.c
View File

@ -800,7 +800,7 @@ int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
(char *)ctl_skb->skb->data, ctl_skb->skb->len);
/* Move the head of the ring to the next empty descriptor */
ch->head_blk_ctl = ctl_skb->next;
ch->head_blk_ctl = ctl_skb->next;
/* Commit all previous writes and set descriptors to VALID */
wmb();

20
drivers/net/wireless/ath/wcn36xx/hal.h
View File

@ -3464,8 +3464,12 @@ struct wcn36xx_hal_rem_bcn_filter_req {
#define WCN36XX_HAL_OFFLOAD_DISABLE 0
#define WCN36XX_HAL_OFFLOAD_ENABLE 1
#define WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE 0x2
#define WCN36XX_HAL_OFFLOAD_MCAST_FILTER_ENABLE 0x4
#define WCN36XX_HAL_OFFLOAD_NS_AND_MCAST_FILTER_ENABLE \
(WCN36XX_HAL_OFFLOAD_ENABLE | WCN36XX_HAL_OFFLOAD_MCAST_FILTER_ENABLE)
#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE \
(HAL_OFFLOAD_ENABLE|HAL_OFFLOAD_BCAST_FILTER_ENABLE)
(WCN36XX_HAL_OFFLOAD_ENABLE | WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE)
#define WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX 0x02
struct wcn36xx_hal_ns_offload_params {
u8 src_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
@ -3487,10 +3491,10 @@ struct wcn36xx_hal_ns_offload_params {
/* slot index for this offload */
u32 slot_index;
u8 bss_index;
};
} __packed;
struct wcn36xx_hal_host_offload_req {
u8 offload_Type;
u8 offload_type;
/* enable or disable */
u8 enable;
@ -3499,13 +3503,13 @@ struct wcn36xx_hal_host_offload_req {
u8 host_ipv4_addr[4];
u8 host_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
} u;
};
} __packed;
struct wcn36xx_hal_host_offload_req_msg {
struct wcn36xx_hal_msg_header header;
struct wcn36xx_hal_host_offload_req host_offload_params;
struct wcn36xx_hal_ns_offload_params ns_offload_params;
};
} __packed;
/* Packet Types. */
#define WCN36XX_HAL_KEEP_ALIVE_NULL_PKT 1
@ -4901,7 +4905,7 @@ struct wcn36xx_hal_gtk_offload_req_msg {
u64 key_replay_counter;
u8 bss_index;
};
} __packed;
struct wcn36xx_hal_gtk_offload_rsp_msg {
struct wcn36xx_hal_msg_header header;
@ -4915,7 +4919,7 @@ struct wcn36xx_hal_gtk_offload_rsp_msg {
struct wcn36xx_hal_gtk_offload_get_info_req_msg {
struct wcn36xx_hal_msg_header header;
u8 bss_index;
};
} __packed;
struct wcn36xx_hal_gtk_offload_get_info_rsp_msg {
struct wcn36xx_hal_msg_header header;
@ -4939,7 +4943,7 @@ struct wcn36xx_hal_gtk_offload_get_info_rsp_msg {
u32 igtk_rekey_count;
u8 bss_index;
};
} __packed;
struct dhcp_info {
/* Indicates the device mode which indicates about the DHCP activity */

131
drivers/net/wireless/ath/wcn36xx/main.c
View File

@ -25,6 +25,7 @@
#include <linux/rpmsg.h>
#include <linux/soc/qcom/smem_state.h>
#include <linux/soc/qcom/wcnss_ctrl.h>
#include <net/ipv6.h>
#include "wcn36xx.h"
#include "testmode.h"
@ -172,7 +173,9 @@ static struct ieee80211_supported_band wcn_band_5ghz = {
#ifdef CONFIG_PM
static const struct wiphy_wowlan_support wowlan_support = {
.flags = WIPHY_WOWLAN_ANY
.flags = WIPHY_WOWLAN_ANY |
WIPHY_WOWLAN_MAGIC_PKT |
WIPHY_WOWLAN_SUPPORTS_GTK_REKEY
};
#endif
@ -293,23 +296,16 @@ static int wcn36xx_start(struct ieee80211_hw *hw)
goto out_free_dxe_pool;
}
wcn->hal_buf = kmalloc(WCN36XX_HAL_BUF_SIZE, GFP_KERNEL);
if (!wcn->hal_buf) {
wcn36xx_err("Failed to allocate smd buf\n");
ret = -ENOMEM;
goto out_free_dxe_ctl;
}
ret = wcn36xx_smd_load_nv(wcn);
if (ret) {
wcn36xx_err("Failed to push NV to chip\n");
goto out_free_smd_buf;
goto out_free_dxe_ctl;
}
ret = wcn36xx_smd_start(wcn);
if (ret) {
wcn36xx_err("Failed to start chip\n");
goto out_free_smd_buf;
goto out_free_dxe_ctl;
}
if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24)) {
@ -336,8 +332,6 @@ static int wcn36xx_start(struct ieee80211_hw *hw)
out_smd_stop:
wcn36xx_smd_stop(wcn);
out_free_smd_buf:
kfree(wcn->hal_buf);
out_free_dxe_ctl:
wcn36xx_dxe_free_ctl_blks(wcn);
out_free_dxe_pool:
@ -372,8 +366,6 @@ static void wcn36xx_stop(struct ieee80211_hw *hw)
wcn36xx_dxe_free_mem_pools(wcn);
wcn36xx_dxe_free_ctl_blks(wcn);
kfree(wcn->hal_buf);
}
static void wcn36xx_change_ps(struct wcn36xx *wcn, bool enable)
@ -1088,28 +1080,91 @@ static int wcn36xx_sta_remove(struct ieee80211_hw *hw,
#ifdef CONFIG_PM
static struct ieee80211_vif *wcn36xx_get_first_assoc_vif(struct wcn36xx *wcn)
{
struct wcn36xx_vif *vif_priv = NULL;
struct ieee80211_vif *vif = NULL;
list_for_each_entry(vif_priv, &wcn->vif_list, list) {
if (vif_priv->sta_assoc) {
vif = wcn36xx_priv_to_vif(vif_priv);
break;
}
}
return vif;
}
static int wcn36xx_suspend(struct ieee80211_hw *hw, struct cfg80211_wowlan *wow)
{
struct wcn36xx *wcn = hw->priv;
struct ieee80211_vif *vif = NULL;
int ret = 0;
wcn36xx_dbg(WCN36XX_DBG_MAC, "mac suspend\n");
flush_workqueue(wcn->hal_ind_wq);
wcn36xx_smd_set_power_params(wcn, true);
return 0;
mutex_lock(&wcn->conf_mutex);
vif = wcn36xx_get_first_assoc_vif(wcn);
if (vif) {
ret = wcn36xx_smd_arp_offload(wcn, vif, true);
if (ret)
goto out;
ret = wcn36xx_smd_ipv6_ns_offload(wcn, vif, true);
if (ret)
goto out;
ret = wcn36xx_smd_gtk_offload(wcn, vif, true);
if (ret)
goto out;
ret = wcn36xx_smd_set_power_params(wcn, true);
if (ret)
goto out;
ret = wcn36xx_smd_wlan_host_suspend_ind(wcn);
}
out:
mutex_unlock(&wcn->conf_mutex);
return ret;
}
static int wcn36xx_resume(struct ieee80211_hw *hw)
{
struct wcn36xx *wcn = hw->priv;
struct ieee80211_vif *vif = NULL;
wcn36xx_dbg(WCN36XX_DBG_MAC, "mac resume\n");
flush_workqueue(wcn->hal_ind_wq);
wcn36xx_smd_set_power_params(wcn, false);
mutex_lock(&wcn->conf_mutex);
vif = wcn36xx_get_first_assoc_vif(wcn);
if (vif) {
wcn36xx_smd_host_resume(wcn);
wcn36xx_smd_set_power_params(wcn, false);
wcn36xx_smd_gtk_offload_get_info(wcn, vif);
wcn36xx_smd_gtk_offload(wcn, vif, false);
wcn36xx_smd_ipv6_ns_offload(wcn, vif, false);
wcn36xx_smd_arp_offload(wcn, vif, false);
}
mutex_unlock(&wcn->conf_mutex);
return 0;
}
static void wcn36xx_set_rekey_data(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct cfg80211_gtk_rekey_data *data)
{
struct wcn36xx *wcn = hw->priv;
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
mutex_lock(&wcn->conf_mutex);
memcpy(vif_priv->rekey_data.kek, data->kek, NL80211_KEK_LEN);
memcpy(vif_priv->rekey_data.kck, data->kck, NL80211_KCK_LEN);
vif_priv->rekey_data.replay_ctr =
cpu_to_le64(be64_to_cpup((__be64 *)data->replay_ctr));
vif_priv->rekey_data.valid = true;
mutex_unlock(&wcn->conf_mutex);
}
#endif
static int wcn36xx_ampdu_action(struct ieee80211_hw *hw,
@ -1176,6 +1231,34 @@ static int wcn36xx_ampdu_action(struct ieee80211_hw *hw,
return ret;
}
#if IS_ENABLED(CONFIG_IPV6)
static void wcn36xx_ipv6_addr_change(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct inet6_dev *idev)
{
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
struct inet6_ifaddr *ifa;
int idx = 0;
memset(vif_priv->tentative_addrs, 0, sizeof(vif_priv->tentative_addrs));
read_lock_bh(&idev->lock);
list_for_each_entry(ifa, &idev->addr_list, if_list) {
vif_priv->target_ipv6_addrs[idx] = ifa->addr;
if (ifa->flags & IFA_F_TENTATIVE)
__set_bit(idx, vif_priv->tentative_addrs);
idx++;
if (idx >= WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX)
break;
wcn36xx_dbg(WCN36XX_DBG_MAC, "%pI6 %s\n", &ifa->addr,
(ifa->flags & IFA_F_TENTATIVE) ? "tentative" : NULL);
}
read_unlock_bh(&idev->lock);
vif_priv->num_target_ipv6_addrs = idx;
}
#endif
static const struct ieee80211_ops wcn36xx_ops = {
.start = wcn36xx_start,
.stop = wcn36xx_stop,
@ -1184,6 +1267,7 @@ static const struct ieee80211_ops wcn36xx_ops = {
#ifdef CONFIG_PM
.suspend = wcn36xx_suspend,
.resume = wcn36xx_resume,
.set_rekey_data = wcn36xx_set_rekey_data,
#endif
.config = wcn36xx_config,
.prepare_multicast = wcn36xx_prepare_multicast,
@ -1199,6 +1283,9 @@ static const struct ieee80211_ops wcn36xx_ops = {
.sta_add = wcn36xx_sta_add,
.sta_remove = wcn36xx_sta_remove,
.ampdu_action = wcn36xx_ampdu_action,
#if IS_ENABLED(CONFIG_IPV6)
.ipv6_addr_change = wcn36xx_ipv6_addr_change,
#endif
CFG80211_TESTMODE_CMD(wcn36xx_tm_cmd)
};
@ -1401,6 +1488,12 @@ static int wcn36xx_probe(struct platform_device *pdev)
mutex_init(&wcn->hal_mutex);
mutex_init(&wcn->scan_lock);
wcn->hal_buf = devm_kmalloc(wcn->dev, WCN36XX_HAL_BUF_SIZE, GFP_KERNEL);
if (!wcn->hal_buf) {
ret = -ENOMEM;
goto out_wq;
}
ret = dma_set_mask_and_coherent(wcn->dev, DMA_BIT_MASK(32));
if (ret < 0) {
wcn36xx_err("failed to set DMA mask: %d\n", ret);

267
drivers/net/wireless/ath/wcn36xx/smd.c
View File

@ -2756,6 +2756,269 @@ out:
return ret;
}
int wcn36xx_smd_arp_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
bool enable)
{
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
struct wcn36xx_hal_host_offload_req_msg msg_body;
int ret;
mutex_lock(&wcn->hal_mutex);
INIT_HAL_MSG(msg_body, WCN36XX_HAL_HOST_OFFLOAD_REQ);
msg_body.host_offload_params.offload_type =
WCN36XX_HAL_IPV4_ARP_REPLY_OFFLOAD;
if (enable) {
msg_body.host_offload_params.enable =
WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE;
memcpy(&msg_body.host_offload_params.u,
&vif->bss_conf.arp_addr_list[0], sizeof(__be32));
}
msg_body.ns_offload_params.bss_index = vif_priv->bss_index;
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
if (ret) {
wcn36xx_err("Sending host_offload_arp failed\n");
goto out;
}
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
if (ret) {
wcn36xx_err("host_offload_arp failed err=%d\n", ret);
goto out;
}
out:
mutex_unlock(&wcn->hal_mutex);
return ret;
}
#if IS_ENABLED(CONFIG_IPV6)
int wcn36xx_smd_ipv6_ns_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
bool enable)
{
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
struct wcn36xx_hal_host_offload_req_msg msg_body;
struct wcn36xx_hal_ns_offload_params *ns_params;
struct wcn36xx_hal_host_offload_req *ho_params;
int ret;
mutex_lock(&wcn->hal_mutex);
INIT_HAL_MSG(msg_body, WCN36XX_HAL_HOST_OFFLOAD_REQ);
ho_params = &msg_body.host_offload_params;
ns_params = &msg_body.ns_offload_params;
ho_params->offload_type = WCN36XX_HAL_IPV6_NS_OFFLOAD;
if (enable) {
ho_params->enable =
WCN36XX_HAL_OFFLOAD_NS_AND_MCAST_FILTER_ENABLE;
if (vif_priv->num_target_ipv6_addrs) {
memcpy(&ho_params->u,
&vif_priv->target_ipv6_addrs[0].in6_u,
sizeof(struct in6_addr));
memcpy(&ns_params->target_ipv6_addr1,
&vif_priv->target_ipv6_addrs[0].in6_u,
sizeof(struct in6_addr));
ns_params->target_ipv6_addr1_valid = 1;
}
if (vif_priv->num_target_ipv6_addrs > 1) {
memcpy(&ns_params->target_ipv6_addr2,
&vif_priv->target_ipv6_addrs[1].in6_u,
sizeof(struct in6_addr));
ns_params->target_ipv6_addr2_valid = 1;
}
}
memcpy(&ns_params->self_addr, vif->addr, ETH_ALEN);
ns_params->bss_index = vif_priv->bss_index;
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
if (ret) {
wcn36xx_err("Sending host_offload_arp failed\n");
goto out;
}
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
if (ret) {
wcn36xx_err("host_offload_arp failed err=%d\n", ret);
goto out;
}
out:
mutex_unlock(&wcn->hal_mutex);
return ret;
}
#else
int wcn36xx_smd_ipv6_ns_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
bool enable)
{
return 0;
}
#endif
int wcn36xx_smd_gtk_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
bool enable)
{
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
struct wcn36xx_hal_gtk_offload_req_msg msg_body;
int ret;
mutex_lock(&wcn->hal_mutex);
INIT_HAL_MSG(msg_body, WCN36XX_HAL_GTK_OFFLOAD_REQ);
if (enable) {
memcpy(&msg_body.kek, vif_priv->rekey_data.kek, NL80211_KEK_LEN);
memcpy(&msg_body.kck, vif_priv->rekey_data.kck, NL80211_KCK_LEN);
msg_body.key_replay_counter =
le64_to_cpu(vif_priv->rekey_data.replay_ctr);
msg_body.bss_index = vif_priv->bss_index;
} else {
msg_body.flags = WCN36XX_HAL_GTK_OFFLOAD_FLAGS_DISABLE;
}
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
if (ret) {
wcn36xx_err("Sending host_offload_arp failed\n");
goto out;
}
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
if (ret) {
wcn36xx_err("host_offload_arp failed err=%d\n", ret);
goto out;
}
out:
mutex_unlock(&wcn->hal_mutex);
return ret;
}
static int wcn36xx_smd_gtk_offload_get_info_rsp(struct wcn36xx *wcn,
struct ieee80211_vif *vif)
{
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
struct wcn36xx_hal_gtk_offload_get_info_rsp_msg *rsp;
__be64 replay_ctr;
if (wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len))
return -EIO;
rsp = (struct wcn36xx_hal_gtk_offload_get_info_rsp_msg *)wcn->hal_buf;
if (rsp->bss_index != vif_priv->bss_index) {
wcn36xx_err("gtk_offload_info invalid response bss index %d\n",
rsp->bss_index);
return -ENOENT;
}
if (vif_priv->rekey_data.replay_ctr != cpu_to_le64(rsp->key_replay_counter)) {
replay_ctr = cpu_to_be64(rsp->key_replay_counter);
vif_priv->rekey_data.replay_ctr =
cpu_to_le64(rsp->key_replay_counter);
ieee80211_gtk_rekey_notify(vif, vif->bss_conf.bssid,
(void *)&replay_ctr, GFP_KERNEL);
wcn36xx_dbg(WCN36XX_DBG_HAL,
"GTK replay counter increment %llu\n",
rsp->key_replay_counter);
}
wcn36xx_dbg(WCN36XX_DBG_HAL,
"gtk offload info status %d last_rekey_status %d "
"replay_counter %llu total_rekey_count %d gtk_rekey_count %d "
"igtk_rekey_count %d bss_index %d\n",
rsp->status, rsp->last_rekey_status,
rsp->key_replay_counter, rsp->total_rekey_count,
rsp->gtk_rekey_count, rsp->igtk_rekey_count,
rsp->bss_index);
return 0;
}
int wcn36xx_smd_gtk_offload_get_info(struct wcn36xx *wcn,
struct ieee80211_vif *vif)
{
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
struct wcn36xx_hal_gtk_offload_get_info_req_msg msg_body;
int ret;
mutex_lock(&wcn->hal_mutex);
INIT_HAL_MSG(msg_body, WCN36XX_HAL_GTK_OFFLOAD_GETINFO_REQ);
msg_body.bss_index = vif_priv->bss_index;
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
if (ret) {
wcn36xx_err("Sending gtk_offload_get_info failed\n");
goto out;
}
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
if (ret) {
wcn36xx_err("gtk_offload_get_info failed err=%d\n", ret);
goto out;
}
ret = wcn36xx_smd_gtk_offload_get_info_rsp(wcn, vif);
out:
mutex_unlock(&wcn->hal_mutex);
return ret;
}
int wcn36xx_smd_wlan_host_suspend_ind(struct wcn36xx *wcn)
{
struct wcn36xx_hal_wlan_host_suspend_ind_msg msg_body;
int ret;
mutex_lock(&wcn->hal_mutex);
INIT_HAL_MSG(msg_body, WCN36XX_HAL_HOST_SUSPEND_IND);
msg_body.configured_mcst_bcst_filter_setting = 0;
msg_body.active_session_count = 1;
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
ret = rpmsg_send(wcn->smd_channel, wcn->hal_buf, msg_body.header.len);
mutex_unlock(&wcn->hal_mutex);
return ret;
}
int wcn36xx_smd_host_resume(struct wcn36xx *wcn)
{
struct wcn36xx_hal_wlan_host_resume_req_msg msg_body;
struct wcn36xx_hal_host_resume_rsp_msg *rsp;
int ret;
mutex_lock(&wcn->hal_mutex);
INIT_HAL_MSG(msg_body, WCN36XX_HAL_HOST_RESUME_REQ);
msg_body.configured_mcst_bcst_filter_setting = 0;
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
ret = wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
if (ret) {
wcn36xx_err("Sending wlan_host_resume failed\n");
goto out;
}
ret = wcn36xx_smd_rsp_status_check(wcn->hal_buf, wcn->hal_rsp_len);
if (ret) {
wcn36xx_err("wlan_host_resume err=%d\n", ret);
goto out;
}
rsp = (struct wcn36xx_hal_host_resume_rsp_msg *)wcn->hal_buf;
if (rsp->status)
wcn36xx_warn("wlan_host_resume status=%d\n", rsp->status);
out:
mutex_unlock(&wcn->hal_mutex);
return ret;
}
int wcn36xx_smd_rsp_process(struct rpmsg_device *rpdev,
void *buf, int len, void *priv, u32 addr)
{
@ -2804,6 +3067,10 @@ int wcn36xx_smd_rsp_process(struct rpmsg_device *rpdev,
case WCN36XX_HAL_8023_MULTICAST_LIST_RSP:
case WCN36XX_HAL_START_SCAN_OFFLOAD_RSP:
case WCN36XX_HAL_STOP_SCAN_OFFLOAD_RSP:
case WCN36XX_HAL_HOST_OFFLOAD_RSP:
case WCN36XX_HAL_GTK_OFFLOAD_RSP:
case WCN36XX_HAL_GTK_OFFLOAD_GETINFO_RSP:
case WCN36XX_HAL_HOST_RESUME_RSP:
memcpy(wcn->hal_buf, buf, len);
wcn->hal_rsp_len = len;
complete(&wcn->hal_rsp_compl);

17
drivers/net/wireless/ath/wcn36xx/smd.h
View File

@ -146,4 +146,21 @@ int wcn36xx_smd_rsp_process(struct rpmsg_device *rpdev,
int wcn36xx_smd_set_mc_list(struct wcn36xx *wcn,
struct ieee80211_vif *vif,
struct wcn36xx_hal_rcv_flt_mc_addr_list_type *fp);
int wcn36xx_smd_arp_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
bool enable);
int wcn36xx_smd_ipv6_ns_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
bool enable);
int wcn36xx_smd_gtk_offload(struct wcn36xx *wcn, struct ieee80211_vif *vif,
bool enable);
int wcn36xx_smd_gtk_offload_get_info(struct wcn36xx *wcn,
struct ieee80211_vif *vif);
int wcn36xx_smd_wlan_host_suspend_ind(struct wcn36xx *wcn);
int wcn36xx_smd_host_resume(struct wcn36xx *wcn);
#endif /* _SMD_H_ */

14
drivers/net/wireless/ath/wcn36xx/wcn36xx.h
View File

@ -18,6 +18,7 @@
#define _WCN36XX_H_
#include <linux/completion.h>
#include <linux/in6.h>
#include <linux/printk.h>
#include <linux/spinlock.h>
#include <net/mac80211.h>
@ -136,6 +137,19 @@ struct wcn36xx_vif {
u8 self_dpu_desc_index;
u8 self_ucast_dpu_sign;
#if IS_ENABLED(CONFIG_IPV6)
/* IPv6 addresses for WoWLAN */
struct in6_addr target_ipv6_addrs[WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX];
unsigned long tentative_addrs[BITS_TO_LONGS(WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX)];
int num_target_ipv6_addrs;
#endif
/* WoWLAN GTK rekey data */
struct {
u8 kck[NL80211_KCK_LEN], kek[NL80211_KEK_LEN];
__le64 replay_ctr;
bool valid;
} rekey_data;
struct list_head sta_list;
};

2
drivers/net/wireless/ath/wil6210/cfg80211.c
View File

@ -2842,9 +2842,7 @@ void wil_p2p_wdev_free(struct wil6210_priv *wil)
wil->radio_wdev = wil->main_ndev->ieee80211_ptr;
mutex_unlock(&wil->vif_mutex);
if (p2p_wdev) {
wiphy_lock(wil->wiphy);
cfg80211_unregister_wdev(p2p_wdev);
wiphy_unlock(wil->wiphy);
kfree(p2p_wdev);
}
}

2
drivers/net/wireless/ath/wil6210/interrupt.c
View File

@ -9,7 +9,7 @@
#include "wil6210.h"
#include "trace.h"
/**
/*
* Theory of operation:
*
* There is ISR pseudo-cause register,

6
drivers/net/wireless/ath/wil6210/wmi.c
View File

@ -224,7 +224,7 @@ struct auth_no_hdr {
u8 led_polarity = LED_POLARITY_LOW_ACTIVE;
/**
* return AHB address for given firmware internal (linker) address
* wmi_addr_remap - return AHB address for given firmware internal (linker) address
* @x: internal address
* If address have no valid AHB mapping, return 0
*/
@ -242,7 +242,7 @@ static u32 wmi_addr_remap(u32 x)
}
/**
* find fw_mapping entry by section name
* wil_find_fw_mapping - find fw_mapping entry by section name
* @section: section name
*
* Return pointer to section or NULL if not found
@ -260,7 +260,7 @@ struct fw_map *wil_find_fw_mapping(const char *section)
}
/**
* Check address validity for WMI buffer; remap if needed
* wmi_buffer_block - Check address validity for WMI buffer; remap if needed
* @wil: driver data
* @ptr_: internal (linker) fw/ucode address
* @size: if non zero, validate the block does not