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drm/msm/dpu: Add SC8180x to hw catalog
Add SC8180x to the hardware catalog, for initial support for the platform. Due to limitations in the DP driver only one of the four DP interfaces is left enabled. The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this is flagged appropriately to ensure widebus is disabled - for now. Signed-off-by: Rob Clark <robdclark@chromium.org> [bjorn: Reworked intf and irq definitions] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Rob Clark
Dmitry Baryshkov
parent
148e852f29
commit
f3af2d6ee9
4 changed files with 132 additions and 0 deletions
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@ -103,6 +103,17 @@
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BIT(MDP_INTF3_INTR) | \
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BIT(MDP_INTF4_INTR))
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#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
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BIT(MDP_SSPP_TOP0_INTR2) | \
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BIT(MDP_SSPP_TOP0_HIST_INTR) | \
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BIT(MDP_INTF0_INTR) | \
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BIT(MDP_INTF1_INTR) | \
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BIT(MDP_INTF2_INTR) | \
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BIT(MDP_INTF3_INTR) | \
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BIT(MDP_INTF4_INTR) | \
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BIT(MDP_INTF5_INTR) | \
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BIT(MDP_AD4_0_INTR) | \
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BIT(MDP_AD4_1_INTR))
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#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
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#define DEFAULT_DPU_LINE_WIDTH 2048
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@ -254,6 +265,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_caps sc8180x_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.qseed_type = DPU_SSPP_SCALER_QSEED3,
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.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
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.ubwc_version = DPU_HW_UBWC_VER_30,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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.max_hdeci_exp = MAX_HORZ_DECIMATION,
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_caps sm8250_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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@ -351,6 +378,31 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg sc8180x_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x45C,
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.features = 0,
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.highest_bank_bit = 0x3,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
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.reg_off = 0x2B4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
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.reg_off = 0x2BC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
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.reg_off = 0x2C4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
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.reg_off = 0x2BC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
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.reg_off = 0x2C4, .bit_off = 8},
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},
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};
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static const struct dpu_mdp_cfg sm8250_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -1027,6 +1079,16 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
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INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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static const struct dpu_intf_cfg sc8180x_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
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/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
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INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
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INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
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INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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/*************************************************************
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* VBIF sub blocks config
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*************************************************************/
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@ -1168,6 +1230,10 @@ static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
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{.fl = 0, .lut = 0x0011222222223357 },
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};
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static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = {
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{.fl = 4, .lut = 0x0000000000000357 },
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};
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static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
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{.fl = 10, .lut = 0x344556677},
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{.fl = 11, .lut = 0x3344556677},
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@ -1181,6 +1247,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
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{.fl = 0, .lut = 0x0011223344556677},
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};
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static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
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{.fl = 10, .lut = 0x0000000344556677},
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};
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static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = {
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{.fl = 0, .lut = 0x0},
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};
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@ -1322,6 +1392,33 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg sc8180x_perf_data = {
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.max_bw_low = 9600000,
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.max_bw_high = 9600000,
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.min_core_ib = 2400000,
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.min_llcc_ib = 800000,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc8180x_qos_linear),
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.entries = sc8180x_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc8180x_qos_macrotile),
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.entries = sc8180x_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg sm8250_perf_data = {
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.max_bw_low = 13700000,
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.max_bw_high = 16600000,
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@ -1504,6 +1601,37 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
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};
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}
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/*
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* sc8180x_cfg_init(): populate sc8180 dpu sub-blocks reg offsets
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* and instance counts.
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*/
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static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
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{
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*dpu_cfg = (struct dpu_mdss_cfg){
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.caps = &sc8180x_dpu_caps,
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.mdp_count = ARRAY_SIZE(sc8180x_mdp),
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.mdp = sc8180x_mdp,
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.ctl_count = ARRAY_SIZE(sm8150_ctl),
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.ctl = sm8150_ctl,
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.sspp_count = ARRAY_SIZE(sdm845_sspp),
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.sspp = sdm845_sspp,
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.mixer_count = ARRAY_SIZE(sm8150_lm),
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.mixer = sm8150_lm,
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.pingpong_count = ARRAY_SIZE(sm8150_pp),
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.pingpong = sm8150_pp,
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.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
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.merge_3d = sm8150_merge_3d,
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.intf_count = ARRAY_SIZE(sc8180x_intf),
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.intf = sc8180x_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.reg_dma_count = 1,
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.dma_cfg = sm8150_regdma,
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.perf = sc8180x_perf_data,
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.mdss_irqs = IRQ_SC8180X_MASK,
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};
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}
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/*
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* sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets
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* and instance counts.
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@ -1567,6 +1695,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
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{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
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{ .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
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{ .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
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{ .hw_rev = DPU_HW_VER_510, .cfg_init = sc8180x_cfg_init},
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{ .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},
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{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
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{ .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init},
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@ -39,6 +39,7 @@
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#define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
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#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */
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#define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */
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#define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */
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#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
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#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
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#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
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@ -1352,6 +1352,7 @@ const struct of_device_id dpu_dt_match[] = {
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{ .compatible = "qcom,sdm845-dpu", },
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{ .compatible = "qcom,sc7180-dpu", },
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{ .compatible = "qcom,sc7280-dpu", },
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{ .compatible = "qcom,sc8180x-dpu", },
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{ .compatible = "qcom,sm8150-dpu", },
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{ .compatible = "qcom,sm8250-dpu", },
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{}
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@ -1439,6 +1439,7 @@ static const struct of_device_id dt_match[] = {
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{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
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{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
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{ .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
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{ .compatible = "qcom,sc8180x-mdss", .data = (void *)KMS_DPU },
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{ .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
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{ .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
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{}
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