mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
Merge branch 'sti_drivers'
Peter Griffin says: ==================== Fix sti drivers whcih mix reg address spaces A V2 of this old series incorporating Arnd and Lees Feedback form v1. Following on from Arnds comments about the picophy driver here https://lkml.org/lkml/2014/11/13/161, this series fixes the remaining upstreamed drivers for STI, which are mixing address spaces in the reg property. We do this in a way similar to the keystone and bcm7445 platforms, by having sysconfig phandle/ offset pair (where only one register is required). Or phandle / integer array where multiple offsets in the same bank are needed). This series breaks DT compatability! But the platform support is WIP and only being used by the few developers who are upstreaming support for it. I've made each change to the driver / dt doc / dt file as a single atomic commit so the kernel will remain bisectable. This series then also enables the picophy driver, and adds back in the ehci/ohci dt nodes for stih410 which make use of the picophy. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
f3cd7a264b
11 changed files with 143 additions and 77 deletions
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@ -9,14 +9,10 @@ The device node has following properties.
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Required properties:
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- compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
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"st,stih407-dwmac", "st,stid127-dwmac".
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- reg : Offset of the glue configuration register map in system
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configuration regmap pointed by st,syscon property and size.
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- st,syscon : Should be phandle to system configuration node which
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encompases this glue registers.
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- st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
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encompases the glue register, and the offset of the control register.
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- st,gmac_en: this is to enable the gmac into a dedicated sysctl control
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register available on STiH407 SoC.
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- sti-ethconf: this is the gmac glue logic register to enable the GMAC,
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select among the different modes and program the clk retiming.
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- pinctrl-0: pin-control for all the MII mode supported.
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Optional properties:
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@ -40,10 +36,10 @@ ethernet0: dwmac@9630000 {
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device_type = "network";
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status = "disabled";
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compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
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reg = <0x9630000 0x8000>, <0x80 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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reg = <0x9630000 0x8000>;
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reg-names = "stmmaceth";
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st,syscon = <&syscfg_sbc_reg>;
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st,syscon = <&syscfg_sbc_reg 0x80>;
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st,gmac_en;
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resets = <&softreset STIH407_ETH1_SOFTRESET>;
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reset-names = "stmmaceth";
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@ -6,8 +6,10 @@ for SATA and PCIe.
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Required properties (controller (parent) node):
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- compatible : Should be "st,miphy365x-phy"
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- st,syscfg : Should be a phandle of the system configuration register group
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which contain the SATA, PCIe mode setting bits
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- st,syscfg : Phandle / integer array property. Phandle of sysconfig group
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containing the miphy registers and integer array should contain
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an entry for each port sub-node, specifying the control
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register offset inside the sysconfig group.
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Required nodes : A sub-node is required for each channel the controller
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provides. Address range information including the usual
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@ -26,7 +28,6 @@ Required properties (port (child) node):
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registers filled in "reg":
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- sata: For SATA devices
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- pcie: For PCIe devices
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- syscfg: To specify the syscfg based config register
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Optional properties (port (child) node):
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- st,sata-gen : Generation of locally attached SATA IP. Expected values
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@ -39,20 +40,20 @@ Example:
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miphy365x_phy: miphy365x@fe382000 {
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compatible = "st,miphy365x-phy";
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st,syscfg = <&syscfg_rear>;
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st,syscfg = <&syscfg_rear 0x824 0x828>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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phy_port0: port@fe382000 {
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reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
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reg-names = "sata", "pcie", "syscfg";
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reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
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reg-names = "sata", "pcie";
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#phy-cells = <1>;
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st,sata-gen = <3>;
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};
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phy_port1: port@fe38a000 {
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reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
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reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
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reg-names = "sata", "pcie", "syscfg";
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#phy-cells = <1>;
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st,pcie-tx-pol-inv;
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@ -5,10 +5,7 @@ host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC fa
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Required properties:
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- compatible : should be "st,stih407-usb2-phy"
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- reg : contain the offset and length of the system configuration registers
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used as glue logic to control & parameter phy
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- reg-names : the names of the system configuration registers in "reg", should be "param" and "reg"
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- st,syscfg : sysconfig register to manage phy parameter at driver level
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- st,syscfg : phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets
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- resets : list of phandle and reset specifier pairs. There should be two entries, one
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for the whole phy and one for the port
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- reset-names : list of reset signal names. Should be "global" and "port"
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@ -19,11 +16,8 @@ Example:
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usb2_picophy0: usbpicophy@f8 {
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compatible = "st,stih407-usb2-phy";
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reg = <0xf8 0x04>, /* syscfg 5062 */
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<0xf4 0x04>; /* syscfg 5061 */
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reg-names = "param", "ctrl";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core>;
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st,syscfg = <&syscfg_core 0x100 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY0_RESET>;
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reset-names = "global", "port";
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@ -274,5 +274,14 @@ i2c@9541000 {
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status = "disabled";
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};
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usb2_picophy0: phy1 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0x100 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY0_RESET>;
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reset-names = "global", "port";
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};
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};
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};
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@ -10,5 +10,75 @@
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#include "stih407-family.dtsi"
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#include "stih410-pinctrl.dtsi"
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/ {
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soc {
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usb2_picophy1: phy2 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xf8 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY0_RESET>;
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reset-names = "global", "port";
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};
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usb2_picophy2: phy3 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xfc 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY1_RESET>;
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reset-names = "global", "port";
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};
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ohci0: usb@9a03c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a03c00 0x100>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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};
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ehci0: usb@9a03e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a03e00 0x100>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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};
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ohci1: usb@9a83c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a83c00 0x100>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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};
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ehci1: usb@9a83e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a83e00 0x100>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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};
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};
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};
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@ -153,8 +153,8 @@ ethernet0: dwmac@fe810000 {
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compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
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status = "disabled";
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reg = <0xfe810000 0x8000>, <0x148 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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reg = <0xfe810000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <0 147 0>, <0 148 0>, <0 149 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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@ -165,7 +165,7 @@ ethernet0: dwmac@fe810000 {
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snps,mixed-burst;
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snps,force_sf_dma_mode;
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st,syscon = <&syscfg_rear>;
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st,syscon = <&syscfg_rear 0x148>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mii0>;
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@ -177,8 +177,8 @@ ethernet1: dwmac@fef08000 {
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device_type = "network";
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compatible = "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
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status = "disabled";
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reg = <0xfef08000 0x8000>, <0x74 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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reg = <0xfef08000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <0 150 0>, <0 151 0>, <0 152 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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@ -186,7 +186,7 @@ ethernet1: dwmac@fef08000 {
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snps,mixed-burst;
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snps,force_sf_dma_mode;
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st,syscon = <&syscfg_sbc>;
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st,syscon = <&syscfg_sbc 0x74>;
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resets = <&softreset STIH415_ETH1_SOFTRESET>;
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reset-names = "stmmaceth";
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@ -163,8 +163,8 @@ ethernet0: dwmac@fe810000 {
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device_type = "network";
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compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
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status = "disabled";
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reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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reg = <0xfe810000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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@ -172,7 +172,7 @@ ethernet0: dwmac@fe810000 {
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snps,pbl = <32>;
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snps,mixed-burst;
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st,syscon = <&syscfg_rear>;
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st,syscon = <&syscfg_rear 0x8bc>;
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resets = <&softreset STIH416_ETH0_SOFTRESET>;
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reset-names = "stmmaceth";
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pinctrl-names = "default";
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@ -185,15 +185,15 @@ ethernet1: dwmac@fef08000 {
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device_type = "network";
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compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
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status = "disabled";
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reg = <0xfef08000 0x8000>, <0x7f0 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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reg = <0xfef08000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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snps,pbl = <32>;
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snps,mixed-burst;
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st,syscon = <&syscfg_sbc>;
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st,syscon = <&syscfg_sbc 0x7f0>;
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resets = <&softreset STIH416_ETH1_SOFTRESET>;
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reset-names = "stmmaceth";
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@ -283,21 +283,21 @@ mmc1: sdhci@fe81f000 {
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miphy365x_phy: phy@fe382000 {
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compatible = "st,miphy365x-phy";
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st,syscfg = <&syscfg_rear>;
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st,syscfg = <&syscfg_rear 0x824 0x828>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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phy_port0: port@fe382000 {
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#phy-cells = <1>;
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reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
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reg-names = "sata", "pcie", "syscfg";
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reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
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reg-names = "sata", "pcie";
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};
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phy_port1: port@fe38a000 {
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#phy-cells = <1>;
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reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
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reg-names = "sata", "pcie", "syscfg";
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reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
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reg-names = "sata", "pcie";
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};
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};
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@ -456,6 +456,7 @@ CONFIG_OMAP_USB2=y
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CONFIG_TI_PIPE3=y
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CONFIG_PHY_MIPHY365X=y
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CONFIG_PHY_STIH41X_USB=y
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CONFIG_PHY_STIH407_USB=y
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CONFIG_PHY_SUN4I_USB=y
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CONFIG_EXT4_FS=y
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CONFIG_AUTOFS4_FS=y
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@ -122,7 +122,7 @@ struct sti_dwmac {
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bool ext_phyclk; /* Clock from external PHY */
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u32 tx_retime_src; /* TXCLK Retiming*/
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struct clk *clk; /* PHY clock */
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int ctrl_reg; /* GMAC glue-logic control register */
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u32 ctrl_reg; /* GMAC glue-logic control register */
|
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int clk_sel_reg; /* GMAC ext clk selection register */
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struct device *dev;
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struct regmap *regmap;
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@ -285,11 +285,6 @@ static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
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if (!np)
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return -EINVAL;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-ethconf");
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if (!res)
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return -ENODATA;
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dwmac->ctrl_reg = res->start;
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/* clk selection from extra syscfg register */
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dwmac->clk_sel_reg = -ENXIO;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf");
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@ -300,6 +295,12 @@ static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg);
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if (err) {
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dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err);
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return err;
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}
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dwmac->dev = dev;
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dwmac->interface = of_get_phy_mode(np);
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dwmac->regmap = regmap;
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|
|
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@ -141,7 +141,7 @@ struct miphy365x_phy {
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|||
bool pcie_tx_pol_inv;
|
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bool sata_tx_pol_inv;
|
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u32 sata_gen;
|
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u64 ctrlreg;
|
||||
u32 ctrlreg;
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u8 type;
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};
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@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
|
|||
bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
|
||||
|
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return regmap_update_bits(miphy_dev->regmap,
|
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(unsigned int)miphy_phy->ctrlreg,
|
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miphy_phy->ctrlreg,
|
||||
SYSCFG_SELECT_SATA_MASK,
|
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sata << SYSCFG_SELECT_SATA_POS);
|
||||
}
|
||||
|
|
@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
|
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{
|
||||
struct device_node *phynode = miphy_phy->phy->dev.of_node;
|
||||
const char *name;
|
||||
const __be32 *taddr;
|
||||
int type = miphy_phy->type;
|
||||
int ret;
|
||||
|
||||
|
|
@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
|
|||
return ret;
|
||||
}
|
||||
|
||||
if (!strncmp(name, "syscfg", 6)) {
|
||||
taddr = of_get_address(phynode, index, NULL, NULL);
|
||||
if (!taddr) {
|
||||
dev_err(dev, "failed to fetch syscfg address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
|
||||
if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
|
||||
dev_err(dev, "failed to translate syscfg address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
|
||||
(!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
|
||||
return 0;
|
||||
|
|
@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
|
||||
phy_set_drvdata(phy, miphy_dev->phys[port]);
|
||||
|
||||
port++;
|
||||
/* sysconfig offsets are indexed from 1 */
|
||||
ret = of_property_read_u32_index(np, "st,syscfg", port,
|
||||
&miphy_phy->ctrlreg);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "No sysconfig offset found\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
|
||||
|
|
|
|||
|
|
@ -22,6 +22,9 @@
|
|||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/phy/phy.h>
|
||||
|
||||
#define PHYPARAM_REG 1
|
||||
#define PHYCTRL_REG 2
|
||||
|
||||
/* Default PHY_SEL and REFCLKSEL configuration */
|
||||
#define STIH407_USB_PICOPHY_CTRL_PORT_CONF 0x6
|
||||
#define STIH407_USB_PICOPHY_CTRL_PORT_MASK 0x1f
|
||||
|
|
@ -93,7 +96,7 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
|
|||
struct device_node *np = dev->of_node;
|
||||
struct phy_provider *phy_provider;
|
||||
struct phy *phy;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
|
||||
if (!phy_dev)
|
||||
|
|
@ -123,19 +126,19 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(phy_dev->regmap);
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
|
||||
if (!res) {
|
||||
dev_err(dev, "No ctrl reg found\n");
|
||||
return -ENXIO;
|
||||
ret = of_property_read_u32_index(np, "st,syscfg", PHYPARAM_REG,
|
||||
&phy_dev->param);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't get phyparam offset (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
phy_dev->ctrl = res->start;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "param");
|
||||
if (!res) {
|
||||
dev_err(dev, "No param reg found\n");
|
||||
return -ENXIO;
|
||||
ret = of_property_read_u32_index(np, "st,syscfg", PHYCTRL_REG,
|
||||
&phy_dev->ctrl);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't get phyctrl offset (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
phy_dev->param = res->start;
|
||||
|
||||
phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data);
|
||||
if (IS_ERR(phy)) {
|
||||
|
|
|
|||
Loading…
Reference in a new issue