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drm/amd/include: Add MP 13.0.8 register headers
Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
64b14a184e
commit
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2 changed files with 1013 additions and 0 deletions
410
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_offset.h
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410
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_offset.h
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _mp_13_0_8_OFFSET_HEADER
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#define _mp_13_0_8_OFFSET_HEADER
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// addressBlock: mp_SmuMp0_SmnDec
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// base address: 0x0
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#define regMP0_SMN_C2PMSG_32 0x0060
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#define regMP0_SMN_C2PMSG_32_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_33 0x0061
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#define regMP0_SMN_C2PMSG_33_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_34 0x0062
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#define regMP0_SMN_C2PMSG_34_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_35 0x0063
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#define regMP0_SMN_C2PMSG_35_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_36 0x0064
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#define regMP0_SMN_C2PMSG_36_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_37 0x0065
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#define regMP0_SMN_C2PMSG_37_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_38 0x0066
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#define regMP0_SMN_C2PMSG_38_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_39 0x0067
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#define regMP0_SMN_C2PMSG_39_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_40 0x0068
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#define regMP0_SMN_C2PMSG_40_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_41 0x0069
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#define regMP0_SMN_C2PMSG_41_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_42 0x006a
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#define regMP0_SMN_C2PMSG_42_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_43 0x006b
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#define regMP0_SMN_C2PMSG_43_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_44 0x006c
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#define regMP0_SMN_C2PMSG_44_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_45 0x006d
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#define regMP0_SMN_C2PMSG_45_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_46 0x006e
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#define regMP0_SMN_C2PMSG_46_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_47 0x006f
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#define regMP0_SMN_C2PMSG_47_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_48 0x0070
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#define regMP0_SMN_C2PMSG_48_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_49 0x0071
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#define regMP0_SMN_C2PMSG_49_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_50 0x0072
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#define regMP0_SMN_C2PMSG_50_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_51 0x0073
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#define regMP0_SMN_C2PMSG_51_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_52 0x0074
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#define regMP0_SMN_C2PMSG_52_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_53 0x0075
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#define regMP0_SMN_C2PMSG_53_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_54 0x0076
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#define regMP0_SMN_C2PMSG_54_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_55 0x0077
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#define regMP0_SMN_C2PMSG_55_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_56 0x0078
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#define regMP0_SMN_C2PMSG_56_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_57 0x0079
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#define regMP0_SMN_C2PMSG_57_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_58 0x007a
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#define regMP0_SMN_C2PMSG_58_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_59 0x007b
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#define regMP0_SMN_C2PMSG_59_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_60 0x007c
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#define regMP0_SMN_C2PMSG_60_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_61 0x007d
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#define regMP0_SMN_C2PMSG_61_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_62 0x007e
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#define regMP0_SMN_C2PMSG_62_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_63 0x007f
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#define regMP0_SMN_C2PMSG_63_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_64 0x0080
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#define regMP0_SMN_C2PMSG_64_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_65 0x0081
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#define regMP0_SMN_C2PMSG_65_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_66 0x0082
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#define regMP0_SMN_C2PMSG_66_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_67 0x0083
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#define regMP0_SMN_C2PMSG_67_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_68 0x0084
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#define regMP0_SMN_C2PMSG_68_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_69 0x0085
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#define regMP0_SMN_C2PMSG_69_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_70 0x0086
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#define regMP0_SMN_C2PMSG_70_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_71 0x0087
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#define regMP0_SMN_C2PMSG_71_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_72 0x0088
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#define regMP0_SMN_C2PMSG_72_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_73 0x0089
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#define regMP0_SMN_C2PMSG_73_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_74 0x008a
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#define regMP0_SMN_C2PMSG_74_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_75 0x008b
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#define regMP0_SMN_C2PMSG_75_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_76 0x008c
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#define regMP0_SMN_C2PMSG_76_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_77 0x008d
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#define regMP0_SMN_C2PMSG_77_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_78 0x008e
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#define regMP0_SMN_C2PMSG_78_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_79 0x008f
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#define regMP0_SMN_C2PMSG_79_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_80 0x0090
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#define regMP0_SMN_C2PMSG_80_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_81 0x0091
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#define regMP0_SMN_C2PMSG_81_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_82 0x0092
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#define regMP0_SMN_C2PMSG_82_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_83 0x0093
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#define regMP0_SMN_C2PMSG_83_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_84 0x0094
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#define regMP0_SMN_C2PMSG_84_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_85 0x0095
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#define regMP0_SMN_C2PMSG_85_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_86 0x0096
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#define regMP0_SMN_C2PMSG_86_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_87 0x0097
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#define regMP0_SMN_C2PMSG_87_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_88 0x0098
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#define regMP0_SMN_C2PMSG_88_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_89 0x0099
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#define regMP0_SMN_C2PMSG_89_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_90 0x009a
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#define regMP0_SMN_C2PMSG_90_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_91 0x009b
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#define regMP0_SMN_C2PMSG_91_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_92 0x009c
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#define regMP0_SMN_C2PMSG_92_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_93 0x009d
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#define regMP0_SMN_C2PMSG_93_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_94 0x009e
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#define regMP0_SMN_C2PMSG_94_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_95 0x009f
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#define regMP0_SMN_C2PMSG_95_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_96 0x00a0
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#define regMP0_SMN_C2PMSG_96_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_97 0x00a1
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#define regMP0_SMN_C2PMSG_97_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_98 0x00a2
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#define regMP0_SMN_C2PMSG_98_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_99 0x00a3
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#define regMP0_SMN_C2PMSG_99_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_100 0x00a4
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#define regMP0_SMN_C2PMSG_100_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_101 0x00a5
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#define regMP0_SMN_C2PMSG_101_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_102 0x00a6
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#define regMP0_SMN_C2PMSG_102_BASE_IDX 0
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#define regMP0_SMN_C2PMSG_103 0x00a7
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#define regMP0_SMN_C2PMSG_103_BASE_IDX 0
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#define regMP0_SMN_IH_CREDIT 0x00c1
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#define regMP0_SMN_IH_CREDIT_BASE_IDX 0
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#define regMP0_SMN_IH_SW_INT 0x00c2
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#define regMP0_SMN_IH_SW_INT_BASE_IDX 0
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#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3
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#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0
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// addressBlock: mp_SmuMp1_SmnDec
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// base address: 0x0
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#define regMP1_SMN_C2PMSG_32 0x0260
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#define regMP1_SMN_C2PMSG_32_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_33 0x0261
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#define regMP1_SMN_C2PMSG_33_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_34 0x0262
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#define regMP1_SMN_C2PMSG_34_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_35 0x0263
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#define regMP1_SMN_C2PMSG_35_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_36 0x0264
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#define regMP1_SMN_C2PMSG_36_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_37 0x0265
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#define regMP1_SMN_C2PMSG_37_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_38 0x0266
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#define regMP1_SMN_C2PMSG_38_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_39 0x0267
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#define regMP1_SMN_C2PMSG_39_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_40 0x0268
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#define regMP1_SMN_C2PMSG_40_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_41 0x0269
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#define regMP1_SMN_C2PMSG_41_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_42 0x026a
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#define regMP1_SMN_C2PMSG_42_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_43 0x026b
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#define regMP1_SMN_C2PMSG_43_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_44 0x026c
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#define regMP1_SMN_C2PMSG_44_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_45 0x026d
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#define regMP1_SMN_C2PMSG_45_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_46 0x026e
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#define regMP1_SMN_C2PMSG_46_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_47 0x026f
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#define regMP1_SMN_C2PMSG_47_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_48 0x0270
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#define regMP1_SMN_C2PMSG_48_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_49 0x0271
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#define regMP1_SMN_C2PMSG_49_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_50 0x0272
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#define regMP1_SMN_C2PMSG_50_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_51 0x0273
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#define regMP1_SMN_C2PMSG_51_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_52 0x0274
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#define regMP1_SMN_C2PMSG_52_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_53 0x0275
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#define regMP1_SMN_C2PMSG_53_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_54 0x0276
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#define regMP1_SMN_C2PMSG_54_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_55 0x0277
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#define regMP1_SMN_C2PMSG_55_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_56 0x0278
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#define regMP1_SMN_C2PMSG_56_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_57 0x0279
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#define regMP1_SMN_C2PMSG_57_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_58 0x027a
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#define regMP1_SMN_C2PMSG_58_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_59 0x027b
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#define regMP1_SMN_C2PMSG_59_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_60 0x027c
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#define regMP1_SMN_C2PMSG_60_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_61 0x027d
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#define regMP1_SMN_C2PMSG_61_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_62 0x027e
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#define regMP1_SMN_C2PMSG_62_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_63 0x027f
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#define regMP1_SMN_C2PMSG_63_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_64 0x0280
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#define regMP1_SMN_C2PMSG_64_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_65 0x0281
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#define regMP1_SMN_C2PMSG_65_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_66 0x0282
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#define regMP1_SMN_C2PMSG_66_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_67 0x0283
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#define regMP1_SMN_C2PMSG_67_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_68 0x0284
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#define regMP1_SMN_C2PMSG_68_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_69 0x0285
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#define regMP1_SMN_C2PMSG_69_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_70 0x0286
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#define regMP1_SMN_C2PMSG_70_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_71 0x0287
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#define regMP1_SMN_C2PMSG_71_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_72 0x0288
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#define regMP1_SMN_C2PMSG_72_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_73 0x0289
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#define regMP1_SMN_C2PMSG_73_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_74 0x028a
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#define regMP1_SMN_C2PMSG_74_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_75 0x028b
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#define regMP1_SMN_C2PMSG_75_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_76 0x028c
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#define regMP1_SMN_C2PMSG_76_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_77 0x028d
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#define regMP1_SMN_C2PMSG_77_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_78 0x028e
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#define regMP1_SMN_C2PMSG_78_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_79 0x028f
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#define regMP1_SMN_C2PMSG_79_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_80 0x0290
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#define regMP1_SMN_C2PMSG_80_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_81 0x0291
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#define regMP1_SMN_C2PMSG_81_BASE_IDX 0
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#define regMP1_SMN_C2PMSG_82 0x0292
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#define regMP1_SMN_C2PMSG_82_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_83 0x0293
|
||||
#define regMP1_SMN_C2PMSG_83_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_84 0x0294
|
||||
#define regMP1_SMN_C2PMSG_84_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_85 0x0295
|
||||
#define regMP1_SMN_C2PMSG_85_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_86 0x0296
|
||||
#define regMP1_SMN_C2PMSG_86_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_87 0x0297
|
||||
#define regMP1_SMN_C2PMSG_87_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_88 0x0298
|
||||
#define regMP1_SMN_C2PMSG_88_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_89 0x0299
|
||||
#define regMP1_SMN_C2PMSG_89_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_90 0x029a
|
||||
#define regMP1_SMN_C2PMSG_90_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_91 0x029b
|
||||
#define regMP1_SMN_C2PMSG_91_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_92 0x029c
|
||||
#define regMP1_SMN_C2PMSG_92_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_93 0x029d
|
||||
#define regMP1_SMN_C2PMSG_93_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_94 0x029e
|
||||
#define regMP1_SMN_C2PMSG_94_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_95 0x029f
|
||||
#define regMP1_SMN_C2PMSG_95_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_96 0x02a0
|
||||
#define regMP1_SMN_C2PMSG_96_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_97 0x02a1
|
||||
#define regMP1_SMN_C2PMSG_97_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_98 0x02a2
|
||||
#define regMP1_SMN_C2PMSG_98_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_99 0x02a3
|
||||
#define regMP1_SMN_C2PMSG_99_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_100 0x02a4
|
||||
#define regMP1_SMN_C2PMSG_100_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_101 0x02a5
|
||||
#define regMP1_SMN_C2PMSG_101_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_102 0x02a6
|
||||
#define regMP1_SMN_C2PMSG_102_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_103 0x02a7
|
||||
#define regMP1_SMN_C2PMSG_103_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_104 0x02a8
|
||||
#define regMP1_SMN_C2PMSG_104_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_105 0x02a9
|
||||
#define regMP1_SMN_C2PMSG_105_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_106 0x02aa
|
||||
#define regMP1_SMN_C2PMSG_106_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_107 0x02ab
|
||||
#define regMP1_SMN_C2PMSG_107_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_108 0x02ac
|
||||
#define regMP1_SMN_C2PMSG_108_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_109 0x02ad
|
||||
#define regMP1_SMN_C2PMSG_109_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_110 0x02ae
|
||||
#define regMP1_SMN_C2PMSG_110_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_111 0x02af
|
||||
#define regMP1_SMN_C2PMSG_111_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_112 0x02b0
|
||||
#define regMP1_SMN_C2PMSG_112_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_113 0x02b1
|
||||
#define regMP1_SMN_C2PMSG_113_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_114 0x02b2
|
||||
#define regMP1_SMN_C2PMSG_114_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_115 0x02b3
|
||||
#define regMP1_SMN_C2PMSG_115_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_116 0x02b4
|
||||
#define regMP1_SMN_C2PMSG_116_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_117 0x02b5
|
||||
#define regMP1_SMN_C2PMSG_117_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_118 0x02b6
|
||||
#define regMP1_SMN_C2PMSG_118_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_119 0x02b7
|
||||
#define regMP1_SMN_C2PMSG_119_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_120 0x02b8
|
||||
#define regMP1_SMN_C2PMSG_120_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_121 0x02b9
|
||||
#define regMP1_SMN_C2PMSG_121_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_122 0x02ba
|
||||
#define regMP1_SMN_C2PMSG_122_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_123 0x02bb
|
||||
#define regMP1_SMN_C2PMSG_123_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_124 0x02bc
|
||||
#define regMP1_SMN_C2PMSG_124_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_125 0x02bd
|
||||
#define regMP1_SMN_C2PMSG_125_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_126 0x02be
|
||||
#define regMP1_SMN_C2PMSG_126_BASE_IDX 0
|
||||
#define regMP1_SMN_C2PMSG_127 0x02bf
|
||||
#define regMP1_SMN_C2PMSG_127_BASE_IDX 0
|
||||
#define regMP1_SMN_IH_CREDIT 0x02c1
|
||||
#define regMP1_SMN_IH_CREDIT_BASE_IDX 0
|
||||
#define regMP1_SMN_IH_SW_INT 0x02c2
|
||||
#define regMP1_SMN_IH_SW_INT_BASE_IDX 0
|
||||
#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3
|
||||
#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
|
||||
#define regMP1_SMN_FPS_CNT 0x02c4
|
||||
#define regMP1_SMN_FPS_CNT_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH0 0x0340
|
||||
#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH1 0x0341
|
||||
#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH2 0x0342
|
||||
#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH3 0x0343
|
||||
#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH4 0x0344
|
||||
#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH5 0x0345
|
||||
#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH6 0x0346
|
||||
#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
|
||||
#define regMP1_SMN_EXT_SCRATCH7 0x0347
|
||||
#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMp1Pub_CruDec
|
||||
// base address: 0x0
|
||||
#define regMP1_FIRMWARE_FLAGS 0xbee009
|
||||
#define regMP1_FIRMWARE_FLAGS_BASE_IDX 0
|
||||
|
||||
|
||||
#endif
|
603
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_sh_mask.h
Normal file
603
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_8_sh_mask.h
Normal file
|
@ -0,0 +1,603 @@
|
|||
/*
|
||||
* Copyright 2022 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _mp_13_0_8_SH_MASK_HEADER
|
||||
#define _mp_13_0_8_SH_MASK_HEADER
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMp0_SmnDec
|
||||
//MP0_SMN_C2PMSG_32
|
||||
#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_33
|
||||
#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_34
|
||||
#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_35
|
||||
#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_36
|
||||
#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_37
|
||||
#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_38
|
||||
#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_39
|
||||
#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_40
|
||||
#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_41
|
||||
#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_42
|
||||
#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_43
|
||||
#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_44
|
||||
#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_45
|
||||
#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_46
|
||||
#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_47
|
||||
#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_48
|
||||
#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_49
|
||||
#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_50
|
||||
#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_51
|
||||
#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_52
|
||||
#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_53
|
||||
#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_54
|
||||
#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_55
|
||||
#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_56
|
||||
#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_57
|
||||
#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_58
|
||||
#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_59
|
||||
#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_60
|
||||
#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_61
|
||||
#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_62
|
||||
#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_63
|
||||
#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_64
|
||||
#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_65
|
||||
#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_66
|
||||
#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_67
|
||||
#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_68
|
||||
#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_69
|
||||
#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_70
|
||||
#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_71
|
||||
#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_72
|
||||
#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_73
|
||||
#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_74
|
||||
#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_75
|
||||
#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_76
|
||||
#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_77
|
||||
#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_78
|
||||
#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_79
|
||||
#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_80
|
||||
#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_81
|
||||
#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_82
|
||||
#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_83
|
||||
#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_84
|
||||
#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_85
|
||||
#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_86
|
||||
#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_87
|
||||
#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_88
|
||||
#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_89
|
||||
#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_90
|
||||
#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_91
|
||||
#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_92
|
||||
#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_93
|
||||
#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_94
|
||||
#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_95
|
||||
#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_96
|
||||
#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_97
|
||||
#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_98
|
||||
#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_99
|
||||
#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_100
|
||||
#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_101
|
||||
#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_102
|
||||
#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_C2PMSG_103
|
||||
#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
|
||||
#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP0_SMN_IH_CREDIT
|
||||
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
|
||||
#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
|
||||
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
|
||||
#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
|
||||
//MP0_SMN_IH_SW_INT
|
||||
#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0
|
||||
#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8
|
||||
#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL
|
||||
#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L
|
||||
//MP0_SMN_IH_SW_INT_CTRL
|
||||
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
|
||||
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
|
||||
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
|
||||
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMp1_SmnDec
|
||||
//MP1_SMN_C2PMSG_32
|
||||
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_33
|
||||
#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_34
|
||||
#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_35
|
||||
#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_36
|
||||
#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_37
|
||||
#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_38
|
||||
#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_39
|
||||
#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_40
|
||||
#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_41
|
||||
#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_42
|
||||
#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_43
|
||||
#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_44
|
||||
#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_45
|
||||
#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_46
|
||||
#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_47
|
||||
#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_48
|
||||
#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_49
|
||||
#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_50
|
||||
#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_51
|
||||
#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_52
|
||||
#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_53
|
||||
#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_54
|
||||
#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_55
|
||||
#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_56
|
||||
#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_57
|
||||
#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_58
|
||||
#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_59
|
||||
#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_60
|
||||
#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_61
|
||||
#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_62
|
||||
#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_63
|
||||
#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_64
|
||||
#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_65
|
||||
#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_66
|
||||
#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_67
|
||||
#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_68
|
||||
#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_69
|
||||
#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_70
|
||||
#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_71
|
||||
#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_72
|
||||
#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_73
|
||||
#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_74
|
||||
#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_75
|
||||
#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_76
|
||||
#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_77
|
||||
#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_78
|
||||
#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_79
|
||||
#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_80
|
||||
#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_81
|
||||
#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_82
|
||||
#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_83
|
||||
#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_84
|
||||
#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_85
|
||||
#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_86
|
||||
#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_87
|
||||
#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_88
|
||||
#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_89
|
||||
#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_90
|
||||
#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_91
|
||||
#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_92
|
||||
#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_93
|
||||
#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_94
|
||||
#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_95
|
||||
#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_96
|
||||
#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_97
|
||||
#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_98
|
||||
#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_99
|
||||
#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_100
|
||||
#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_101
|
||||
#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_102
|
||||
#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_103
|
||||
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_104
|
||||
#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_105
|
||||
#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_106
|
||||
#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_107
|
||||
#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_108
|
||||
#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_109
|
||||
#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_110
|
||||
#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_111
|
||||
#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_112
|
||||
#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_113
|
||||
#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_114
|
||||
#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_115
|
||||
#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_116
|
||||
#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_117
|
||||
#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_118
|
||||
#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_119
|
||||
#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_120
|
||||
#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_121
|
||||
#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_122
|
||||
#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_123
|
||||
#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_124
|
||||
#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_125
|
||||
#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_126
|
||||
#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_C2PMSG_127
|
||||
#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
|
||||
#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_IH_CREDIT
|
||||
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
|
||||
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
|
||||
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
|
||||
#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
|
||||
//MP1_SMN_IH_SW_INT
|
||||
#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
|
||||
#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
|
||||
#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
|
||||
#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
|
||||
//MP1_SMN_IH_SW_INT_CTRL
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
|
||||
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
|
||||
//MP1_SMN_FPS_CNT
|
||||
#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
|
||||
#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH0
|
||||
#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH1
|
||||
#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH2
|
||||
#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH3
|
||||
#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH4
|
||||
#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH5
|
||||
#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH6
|
||||
#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
|
||||
//MP1_SMN_EXT_SCRATCH7
|
||||
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
|
||||
#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
|
||||
|
||||
|
||||
// addressBlock: mp_SmuMp1Pub_CruDec
|
||||
//MP1_FIRMWARE_FLAGS
|
||||
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
|
||||
#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
|
||||
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
|
||||
#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
|
||||
|
||||
|
||||
#endif
|
Loading…
Reference in a new issue