mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 01:10:04 +00:00
Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into devel
This commit is contained in:
commit
f412b09f4e
10 changed files with 87 additions and 27 deletions
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@ -717,6 +717,9 @@ __armv7_mmu_cache_off:
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bl __armv7_mmu_cache_flush
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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mov pc, r12
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__arm6_mmu_cache_off:
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@ -778,12 +781,13 @@ __armv6_mmu_cache_flush:
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__armv7_mmu_cache_flush:
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mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
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tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
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beq hierarchical
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mov r10, #0
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beq hierarchical
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mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
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b iflush
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hierarchical:
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stmfd sp!, {r0-r5, r7, r9-r11}
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mcr p15, 0, r10, c7, c10, 5 @ DMB
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stmfd sp!, {r0-r5, r7, r9, r11}
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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@ -820,12 +824,14 @@ skip:
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cmp r3, r10
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bgt loop1
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finished:
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ldmfd sp!, {r0-r5, r7, r9, r11}
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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ldmfd sp!, {r0-r5, r7, r9-r11}
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iflush:
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mcr p15, 0, r10, c7, c10, 4 @ DSB
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mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
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mcr p15, 0, r10, c7, c10, 4 @ drain WB
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mcr p15, 0, r10, c7, c10, 4 @ DSB
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mcr p15, 0, r10, c7, c5, 4 @ ISB
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mov pc, lr
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__armv5tej_mmu_cache_flush:
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@ -15,6 +15,7 @@
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#include <asm/glue.h>
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#include <asm/shmparam.h>
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#include <asm/cachetype.h>
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#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
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@ -295,16 +296,6 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
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#endif
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/*
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* flush_cache_vmap() is used when creating mappings (eg, via vmap,
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* vmalloc, ioremap etc) in kernel space for pages. Since the
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* direct-mappings of these pages may contain cached data, we need
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* to do a full cache flush to ensure that writebacks don't corrupt
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* data placed into these pages via the new mappings.
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*/
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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@ -444,4 +435,29 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
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dmac_inv_range(start, start + size);
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}
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/*
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* flush_cache_vmap() is used when creating mappings (eg, via vmap,
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* vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
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* caches, since the direct-mappings of these pages may contain cached
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* data, we need to do a full cache flush to ensure that writebacks
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* don't corrupt data placed into these pages via the new mappings.
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*/
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static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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{
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if (!cache_is_vipt_nonaliasing())
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flush_cache_all();
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else
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/*
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* set_pte_at() called from vmap_pte_range() does not
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* have a DSB after cleaning the cache line.
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*/
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dsb();
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}
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static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
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{
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if (!cache_is_vipt_nonaliasing())
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flush_cache_all();
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}
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#endif
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@ -16,6 +16,7 @@
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#define HWCAP_IWMMXT 512
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#define HWCAP_CRUNCH 1024
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#define HWCAP_THUMBEE 2048
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#define HWCAP_NEON 4096
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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/*
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@ -772,6 +772,8 @@ static const char *hwcap_str[] = {
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"java",
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"iwmmxt",
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"crunch",
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"thumbee",
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"neon",
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NULL
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};
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@ -25,7 +25,7 @@
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/*
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* Access to the ThumbEE Handler Base register
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*/
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static inline unsigned long teehbr_read()
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static inline unsigned long teehbr_read(void)
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{
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unsigned long v;
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asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v));
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@ -26,6 +26,7 @@
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* - mm - mm_struct describing address space
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*/
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ENTRY(v7_flush_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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@ -64,6 +65,7 @@ skip:
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_flush_dcache_all)
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@ -71,6 +71,8 @@ ENTRY(cpu_v6_reset)
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v6_do_idle)
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mov r1, #0
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mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
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mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
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mov pc, lr
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@ -20,9 +20,17 @@
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#define TTB_C (1 << 0)
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#define TTB_S (1 << 1)
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#define TTB_RGN_NC (0 << 3)
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#define TTB_RGN_OC_WBWA (1 << 3)
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#define TTB_RGN_OC_WT (2 << 3)
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#define TTB_RGN_OC_WB (3 << 3)
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#ifndef CONFIG_SMP
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#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB
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#else
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#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA
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#endif
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ENTRY(cpu_v7_proc_init)
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mov pc, lr
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ENDPROC(cpu_v7_proc_init)
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@ -55,6 +63,7 @@ ENDPROC(cpu_v7_reset)
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v7_do_idle)
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dsb @ WFI may enter a low-power mode
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wfi
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mov pc, lr
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ENDPROC(cpu_v7_do_idle)
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@ -85,7 +94,7 @@ ENTRY(cpu_v7_switch_mm)
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#ifdef CONFIG_MMU
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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orr r0, r0, #TTB_FLAGS
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mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
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isb
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1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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@ -162,6 +171,11 @@ cpu_v7_name:
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* - cache type register is implemented
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*/
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__v7_setup:
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#ifdef CONFIG_SMP
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mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
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orr r0, r0, #(0x1 << 6)
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mcr p15, 0, r0, c1, c0, 1
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#endif
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adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, r7, r9, r11, lr}
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bl v7_flush_dcache_all
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@ -174,8 +188,7 @@ __v7_setup:
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#ifdef CONFIG_MMU
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r10, c2, c0, 2 @ TTB control register
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orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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mcr p15, 0, r4, c2, c0, 0 @ load TTB0
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orr r4, r4, #TTB_FLAGS
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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@ -101,9 +101,12 @@ ENTRY(vfp_support_entry)
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VFPFSTMIA r4, r5 @ save the working registers
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VFPFMRX r5, FPSCR @ current status
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tst r1, #FPEXC_EX @ is there additional state to save?
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VFPFMRX r6, FPINST, NE @ FPINST (only if FPEXC.EX is set)
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tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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VFPFMRX r8, FPINST2, NE @ FPINST2 if needed (and present)
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beq 1f
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VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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beq 1f
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VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
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1:
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stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
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@ and point r4 at the word at the
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@ start of the register dump
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@ -117,9 +120,12 @@ no_old_VFP_process:
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@ FPEXC is in a safe state
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ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
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tst r1, #FPEXC_EX @ is there additional state to restore?
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VFPFMXR FPINST, r6, NE @ restore FPINST (only if FPEXC.EX is set)
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tstne r1, #FPEXC_FP2V @ is there an FPINST2 to write?
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VFPFMXR FPINST2, r8, NE @ FPINST2 if needed (and present)
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beq 1f
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VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
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beq 1f
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VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
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1:
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VFPFMXR FPSCR, r5 @ restore status
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check_for_exception:
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@ -175,9 +181,12 @@ ENTRY(vfp_save_state)
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VFPFSTMIA r0, r2 @ save the working registers
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VFPFMRX r2, FPSCR @ current status
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tst r1, #FPEXC_EX @ is there additional state to save?
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VFPFMRX r3, FPINST, NE @ FPINST (only if FPEXC.EX is set)
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tstne r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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VFPFMRX r12, FPINST2, NE @ FPINST2 if needed (and present)
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beq 1f
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VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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beq 1f
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VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
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1:
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stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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mov pc, lr
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ENDPROC(vfp_save_state)
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@ -371,6 +371,15 @@ static int __init vfp_init(void)
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* in place; report VFP support to userspace.
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*/
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elf_hwcap |= HWCAP_VFP;
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#ifdef CONFIG_NEON
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/*
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* Check for the presence of the Advanced SIMD
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* load/store instructions, integer and single
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* precision floating point operations.
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*/
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if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
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elf_hwcap |= HWCAP_NEON;
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#endif
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}
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return 0;
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}
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