mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-05 08:26:59 +00:00
Qualcomm ARM64 Devicetree fixes for v6.3
This correct SIM card selection on the two newly introduced MSM8916-based USB modems. The firmware-name for the first CDSP is corrected on the SA8540P Ride board. The PCIe controller in SC7280 is marked cache-coherent, which resolves seen data corruption issues. Labels are added to the vadc channel nodes on SC8280XP, as the Linux driver was updated to not include the unit address when generating device names and collisions thereby prevented registration of the channels. Audio clocks and routing is corrected and a few regulators are marked always-on for the Lenovo Thinkpad X13s, as their clients are not fully described at this point. SPI5 was accidentally enabled by default on SM6115, and is disabled again. CDSP on SM6375 is provided its power-domains, to appropriately vote for during power up for the DSP. The iommu mask for the PCIe controllers in SM8150 is updated, to match what the hypervisor expects. Th Venus firmware path is corrected on Xiaomi Mi Pad 5 Pro. The UFS controller is marked cache coherent on SM8350 and SM8450. The clocks for the second WSA macro on SM8450 is corrected, and given its own clocks. The bias-pull-up value for I2C pins are corrected on SM8550, to trigger the selection of the strong pull. CPU compatibles and the base address of the LPASS TLMM block are corrected. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmQcXyAVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FHkcP/1akX9y9zL+WafnVBz4hxDXvlo2G mlBincInfXXvpY7XqQ0ahjJKWCGBTkeOspkxHgH1vWJPWYlpAaJTVdI5ghLRmGJ2 VAb1NJskwxgyc0pCNvrpKHumIp+ZqU7kWhepKJVwNa/AYshYJ9nvBc3jO9FmR02I s/sTktzU9HK5C5o2r4ZbNcskxdQ7OD91YDLKVw8Tn+ubZiNhjyeRI5v9vPszac+n 29Zz+NJVj4SUjywN9K/j/nKjmfkuJ5wRbRIqWifB6qXRo25pp/u7fUN3l6YF+w3X BMZhJyzFrSn6ICiw5Io1QjLceUWmJNtLyDFkKpgwS0ZLU4iW0SQ0h1IHuOKq1EOu bS3nYi4uFqp91b7Ay8rh9zri0RCE617bcCoN1edPJH/MZA0Ndg20x8ZMee5klXTo vC+UjLCdUkS+e3SnvRlOa8wghwTDnJ/yELdDyMh2++wypqELcFRSRvjiW1d+nqXr F0M5Jm5o9fGgPTEtdUCPVMT29RGzns51eUcp4MW5D9mxL8j4ozhYcIFQf+IF9U8l A8g9hzuK68DN5rwlBbJlW/UWUrUl0ZTlmstoyg5sMgAJ/Z73tV13J8D7GAKRgzVI Xf618k6El4NlHBcEzXtc5QBN/UNosZXu2aSsnECMi314bn3QmfVyQ/wlfCYmp/R4 /Ekp1Dxy3Gv1rB8j =9sTC -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmQd2HEACgkQmmx57+YA GNkVcg/8Do+X6UUaMF1F8l/P+PNJpyh7bk8MRuKyJ1ei5rUhv/sXWoCBXISg5rOD tU8A+lYXfyEAiUf1wx5kqrkkd9Uz4vFEC6lSbLwCZSOYBgkptXSrwcW+29Cnbcn7 SitGyZUJJGhbxPCEzYB/qtMnpwg0deL/Wc5Va2I2EmO+/GenZtlEXKiOd6yLwKp8 KDCe8DuXLoMQ+IAk/U/F66QJh7xZVc2xnMJx48JLmveWsyBeVWrqmuG7zd/8h1IW P5r9nop3WvaIC2PjXZ5DeLVan4OBAwdC7s2GcrrSIuM+NP5q1/cxeTzGLPQJqAXc iPwu0/8a5PL0aTJHgMPQWii2hJqm+twbr42OuqG6tjMgAVuHQjRwOlcpDMiP5Z4X K03I36w/KgURftqlHkCnEAd8MT75+HSJzU14WLHbtipHLcUfan6raE+J+TPFIaZ2 s6T+um8Unfgt9jR1OMIXXxOk9151BsCW5nO+5PL9UZVobC4oe/XLspVmA8LSwn8J w3C+pAFr9s8GMYzB34aIMdj79BgYCgP7dk6H7Jxu4EQ7zY90U2qCWxCNX7EGGylR IJdJkm/clc8zMYaDzWCgck4XM0UtthpEJqLM+KzN/01MoRnoWBQaqjC2ui29ryeA o4XdMnqBpqG5m4Sx/QYvZdZ5E4XCFBBz5urMXhs7Z9uGznOGc8A= =fCbE -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-fixes-for-6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/fixes Qualcomm ARM64 Devicetree fixes for v6.3 This correct SIM card selection on the two newly introduced MSM8916-based USB modems. The firmware-name for the first CDSP is corrected on the SA8540P Ride board. The PCIe controller in SC7280 is marked cache-coherent, which resolves seen data corruption issues. Labels are added to the vadc channel nodes on SC8280XP, as the Linux driver was updated to not include the unit address when generating device names and collisions thereby prevented registration of the channels. Audio clocks and routing is corrected and a few regulators are marked always-on for the Lenovo Thinkpad X13s, as their clients are not fully described at this point. SPI5 was accidentally enabled by default on SM6115, and is disabled again. CDSP on SM6375 is provided its power-domains, to appropriately vote for during power up for the DSP. The iommu mask for the PCIe controllers in SM8150 is updated, to match what the hypervisor expects. Th Venus firmware path is corrected on Xiaomi Mi Pad 5 Pro. The UFS controller is marked cache coherent on SM8350 and SM8450. The clocks for the second WSA macro on SM8450 is corrected, and given its own clocks. The bias-pull-up value for I2C pins are corrected on SM8550, to trigger the selection of the strong pull. CPU compatibles and the base address of the LPASS TLMM block are corrected. * tag 'qcom-arm64-fixes-for-6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits) arm64: dts: qcom: sc8280xp-x13s: mark bob regulator as always-on arm64: dts: qcom: sc8280xp-x13s: mark s12b regulator as always-on arm64: dts: qcom: sc8280xp-x13s: mark s10b regulator as always-on arm64: dts: qcom: sc8280xp-x13s: mark s11b regulator as always-on arm64: dts: qcom: sm8550: Mark UFS controller as cache coherent arm64: dts: qcom: sa8540p-ride: correct name of remoteproc_nsp0 firmware arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base address arm64: dts: qcom: sc8280xp-x13s: fix va dmic dai links and routing arm64: dts: qcom: sc8280xp-x13s: fix dmic sample rate arm64: dts: qcom: sc8280xp: fix lpass tx macro clocks arm64: dts: qcom: sc8280xp: fix rx frame shapping info arm64: dts: qcom: sm8450: correct WSA2 assigned clocks arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent arm64: dts: qcom: msm8916-ufi: Fix sim card selection pinctrl arm64: dts: qcom: sm8250-xiaomi-elish: Correct venus firmware path arm64: dts: qcom: sm8550: Use correct CPU compatibles arm64: dts: qcom: sm8550: Add bias pull up value to tlmm i2c data clk states arm64: dts: qcom: sm6375: Add missing power-domain-named to CDSP ... Link: https://lore.kernel.org/r/20230323141642.1085684-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
f42ee7c457
14 changed files with 94 additions and 60 deletions
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@ -33,7 +33,3 @@ &button_default {
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&gpio_leds_default {
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pins = "gpio81", "gpio82", "gpio83";
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};
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&sim_ctrl_default {
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pins = "gpio1", "gpio2";
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};
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@ -25,6 +25,11 @@ &led_b {
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gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
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};
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&mpss {
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pinctrl-0 = <&sim_ctrl_default>;
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pinctrl-names = "default";
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};
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&button_default {
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pins = "gpio37";
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bias-pull-down;
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@ -34,6 +39,25 @@ &gpio_leds_default {
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pins = "gpio20", "gpio21", "gpio22";
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};
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&sim_ctrl_default {
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pins = "gpio1", "gpio2";
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/* This selects the external SIM card slot by default */
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&msmgpio {
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sim_ctrl_default: sim-ctrl-default-state {
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esim-sel-pins {
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pins = "gpio0", "gpio3";
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bias-disable;
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output-low;
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};
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sim-en-pins {
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pins = "gpio1";
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bias-disable;
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output-low;
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};
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sim-sel-pins {
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pins = "gpio2";
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bias-disable;
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output-high;
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};
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};
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};
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@ -92,9 +92,6 @@ &gcc {
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};
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&mpss {
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pinctrl-0 = <&sim_ctrl_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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@ -240,11 +237,4 @@ gpio_leds_default: gpio-leds-default-state {
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drive-strength = <2>;
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bias-disable;
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};
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sim_ctrl_default: sim-ctrl-default-state {
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function = "gpio";
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drive-strength = <2>;
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bias-disable;
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output-low;
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};
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};
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@ -241,7 +241,7 @@ &qup2 {
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};
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&remoteproc_nsp0 {
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firmware-name = "qcom/sa8540p/cdsp.mbn";
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firmware-name = "qcom/sa8540p/cdsp0.mbn";
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status = "okay";
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};
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@ -2131,6 +2131,8 @@ pcie1: pci@1c08000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_clkreq_n>;
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dma-coherent;
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iommus = <&apps_smmu 0x1c80 0x1>;
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iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
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@ -370,6 +370,7 @@ vreg_s10b: smps10 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-always-on;
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};
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vreg_s11b: smps11 {
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@ -377,6 +378,7 @@ vreg_s11b: smps11 {
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regulator-min-microvolt = <1272000>;
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regulator-max-microvolt = <1272000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-always-on;
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};
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vreg_s12b: smps12 {
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@ -384,6 +386,7 @@ vreg_s12b: smps12 {
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regulator-min-microvolt = <984000>;
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regulator-max-microvolt = <984000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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regulator-always-on;
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};
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vreg_l3b: ldo3 {
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@ -441,6 +444,7 @@ vreg_bob: bob {
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regulator-min-microvolt = <3008000>;
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regulator-max-microvolt = <3960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
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regulator-always-on;
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};
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};
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@ -772,75 +776,88 @@ &pmk8280_vadc {
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pmic-die-temp@3 {
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reg = <PMK8350_ADC7_DIE_TEMP>;
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qcom,pre-scaling = <1 1>;
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label = "pmk8350_die_temp";
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};
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xo-therm@44 {
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reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "pmk8350_xo_therm";
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};
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pmic-die-temp@103 {
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reg = <PM8350_ADC7_DIE_TEMP(1)>;
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qcom,pre-scaling = <1 1>;
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label = "pmc8280_1_die_temp";
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};
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sys-therm@144 {
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reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "sys_therm1";
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};
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sys-therm@145 {
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reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "sys_therm2";
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};
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sys-therm@146 {
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reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "sys_therm3";
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};
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sys-therm@147 {
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reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "sys_therm4";
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};
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pmic-die-temp@303 {
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reg = <PM8350_ADC7_DIE_TEMP(3)>;
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qcom,pre-scaling = <1 1>;
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label = "pmc8280_2_die_temp";
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};
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sys-therm@344 {
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reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "sys_therm5";
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};
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sys-therm@345 {
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reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "sys_therm6";
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};
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sys-therm@346 {
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reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "sys_therm7";
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};
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sys-therm@347 {
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reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
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qcom,hw-settle-time = <200>;
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qcom,ratiometric;
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label = "sys_therm8";
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};
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pmic-die-temp@403 {
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reg = <PMR735A_ADC7_DIE_TEMP>;
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qcom,pre-scaling = <1 1>;
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label = "pmr735a_die_temp";
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};
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};
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@ -884,9 +901,9 @@ &sound {
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"VA DMIC0", "MIC BIAS1",
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"VA DMIC1", "MIC BIAS1",
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"VA DMIC2", "MIC BIAS3",
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"TX DMIC0", "MIC BIAS1",
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"TX DMIC1", "MIC BIAS2",
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"TX DMIC2", "MIC BIAS3",
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"VA DMIC0", "VA MIC BIAS1",
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"VA DMIC1", "VA MIC BIAS1",
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"VA DMIC2", "VA MIC BIAS3",
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"TX SWR_ADC1", "ADC2_OUTPUT";
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wcd-playback-dai-link {
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@ -937,7 +954,7 @@ platform {
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va-dai-link {
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link-name = "VA Capture";
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cpu {
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sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
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sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
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};
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platform {
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@ -1062,7 +1079,7 @@ &vamacro {
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vdd-micb-supply = <&vreg_s10b>;
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qcom,dmic-sample-rate = <600000>;
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qcom,dmic-sample-rate = <4800000>;
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status = "okay";
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};
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@ -2504,12 +2504,12 @@ swr1: soundwire-controller@3210000 {
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qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
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qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
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qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
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qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
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qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
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qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
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qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
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qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
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qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
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qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
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qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
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qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
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qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
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#sound-dai-cells = <1>;
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#address-cells = <2>;
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@ -2600,7 +2600,7 @@ swr2: soundwire-controller@3330000 {
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<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "core", "wake";
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clocks = <&vamacro>;
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clocks = <&txmacro>;
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clock-names = "iface";
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label = "TX";
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#sound-dai-cells = <1>;
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@ -2609,15 +2609,15 @@ swr2: soundwire-controller@3330000 {
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qcom,din-ports = <4>;
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qcom,dout-ports = <0>;
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qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>;
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qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>;
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qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
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qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
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qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
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qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>;
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qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
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qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>;
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qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
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status = "disabled";
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};
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@ -1078,6 +1078,7 @@ spi5: spi@4a94000 {
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dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1209,6 +1209,7 @@ remoteproc_cdsp: remoteproc@b000000 {
|
|||
clock-names = "xo";
|
||||
|
||||
power-domains = <&rpmpd SM6375_VDDCX>;
|
||||
power-domain-names = "cx";
|
||||
|
||||
memory-region = <&pil_cdsp_mem>;
|
||||
|
||||
|
|
|
|||
|
|
@ -1826,7 +1826,7 @@ pcie0: pci@1c00000 {
|
|||
"slave_q2a",
|
||||
"tbu";
|
||||
|
||||
iommus = <&apps_smmu 0x1d80 0x7f>;
|
||||
iommus = <&apps_smmu 0x1d80 0x3f>;
|
||||
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
|
||||
<0x100 &apps_smmu 0x1d81 0x1>;
|
||||
|
||||
|
|
@ -1925,7 +1925,7 @@ pcie1: pci@1c08000 {
|
|||
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
iommus = <&apps_smmu 0x1e00 0x7f>;
|
||||
iommus = <&apps_smmu 0x1e00 0x3f>;
|
||||
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
|
||||
<0x100 &apps_smmu 0x1e01 0x1>;
|
||||
|
||||
|
|
|
|||
|
|
@ -625,6 +625,6 @@ &ufs_mem_phy {
|
|||
};
|
||||
|
||||
&venus {
|
||||
firmware-name = "qcom/sm8250/elish/venus.mbn";
|
||||
firmware-name = "qcom/sm8250/xiaomi/elish/venus.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1664,6 +1664,7 @@ ufs_mem_hc: ufshc@1d84000 {
|
|||
power-domains = <&gcc UFS_PHY_GDSC>;
|
||||
|
||||
iommus = <&apps_smmu 0xe0 0x0>;
|
||||
dma-coherent;
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
|
|
|
|||
|
|
@ -2143,8 +2143,8 @@ wsa2macro: codec@31e0000 {
|
|||
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&vamacro>;
|
||||
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
|
||||
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
assigned-clock-rates = <19200000>, <19200000>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -4003,6 +4003,7 @@ ufs_mem_hc: ufshc@1d84000 {
|
|||
power-domains = <&gcc UFS_PHY_GDSC>;
|
||||
|
||||
iommus = <&apps_smmu 0xe0 0x0>;
|
||||
dma-coherent;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ cpus {
|
|||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
compatible = "arm,cortex-a510";
|
||||
reg = <0 0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
|
|
@ -89,7 +89,7 @@ L3_0: l3-cache {
|
|||
|
||||
CPU1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
compatible = "arm,cortex-a510";
|
||||
reg = <0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
|
|
@ -108,7 +108,7 @@ L2_100: l2-cache {
|
|||
|
||||
CPU2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
compatible = "arm,cortex-a510";
|
||||
reg = <0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
|
|
@ -127,7 +127,7 @@ L2_200: l2-cache {
|
|||
|
||||
CPU3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
compatible = "arm,cortex-a715";
|
||||
reg = <0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
|
|
@ -146,7 +146,7 @@ L2_300: l2-cache {
|
|||
|
||||
CPU4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
compatible = "arm,cortex-a715";
|
||||
reg = <0 0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
|
|
@ -165,7 +165,7 @@ L2_400: l2-cache {
|
|||
|
||||
CPU5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
compatible = "arm,cortex-a710";
|
||||
reg = <0 0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
|
|
@ -184,7 +184,7 @@ L2_500: l2-cache {
|
|||
|
||||
CPU6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
compatible = "arm,cortex-a710";
|
||||
reg = <0 0x600>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
|
|
@ -203,7 +203,7 @@ L2_600: l2-cache {
|
|||
|
||||
CPU7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
compatible = "arm,cortex-x3";
|
||||
reg = <0 0x700>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
|
|
@ -1905,6 +1905,7 @@ ufs_mem_hc: ufs@1d84000 {
|
|||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
iommus = <&apps_smmu 0x60 0x0>;
|
||||
dma-coherent;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
|
||||
|
|
@ -1997,7 +1998,7 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
|
|||
lpass_tlmm: pinctrl@6e80000 {
|
||||
compatible = "qcom,sm8550-lpass-lpi-pinctrl";
|
||||
reg = <0 0x06e80000 0 0x20000>,
|
||||
<0 0x0725a000 0 0x10000>;
|
||||
<0 0x07250000 0 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpass_tlmm 0 0 23>;
|
||||
|
|
@ -2691,7 +2692,7 @@ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
|
|||
pins = "gpio28", "gpio29";
|
||||
function = "qup1_se0";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
|
||||
|
|
@ -2699,7 +2700,7 @@ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
|
|||
pins = "gpio32", "gpio33";
|
||||
function = "qup1_se1";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
|
||||
|
|
@ -2707,7 +2708,7 @@ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
|
|||
pins = "gpio36", "gpio37";
|
||||
function = "qup1_se2";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
|
||||
|
|
@ -2715,7 +2716,7 @@ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
|
|||
pins = "gpio40", "gpio41";
|
||||
function = "qup1_se3";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
|
||||
|
|
@ -2723,7 +2724,7 @@ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
|
|||
pins = "gpio44", "gpio45";
|
||||
function = "qup1_se4";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
|
||||
|
|
@ -2731,7 +2732,7 @@ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
|
|||
pins = "gpio52", "gpio53";
|
||||
function = "qup1_se5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
|
||||
|
|
@ -2739,7 +2740,7 @@ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
|
|||
pins = "gpio48", "gpio49";
|
||||
function = "qup1_se6";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
|
||||
|
|
@ -2747,14 +2748,14 @@ scl-pins {
|
|||
pins = "gpio57";
|
||||
function = "qup2_se0_l1_mira";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
sda-pins {
|
||||
pins = "gpio56";
|
||||
function = "qup2_se0_l0_mira";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -2763,7 +2764,7 @@ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
|
|||
pins = "gpio60", "gpio61";
|
||||
function = "qup2_se1";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c10_data_clk: qup-i2c10-data-clk-state {
|
||||
|
|
@ -2771,7 +2772,7 @@ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
|
|||
pins = "gpio64", "gpio65";
|
||||
function = "qup2_se2";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c11_data_clk: qup-i2c11-data-clk-state {
|
||||
|
|
@ -2779,7 +2780,7 @@ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
|
|||
pins = "gpio68", "gpio69";
|
||||
function = "qup2_se3";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c12_data_clk: qup-i2c12-data-clk-state {
|
||||
|
|
@ -2787,7 +2788,7 @@ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
|
|||
pins = "gpio2", "gpio3";
|
||||
function = "qup2_se4";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c13_data_clk: qup-i2c13-data-clk-state {
|
||||
|
|
@ -2795,7 +2796,7 @@ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
|
|||
pins = "gpio80", "gpio81";
|
||||
function = "qup2_se5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_i2c15_data_clk: qup-i2c15-data-clk-state {
|
||||
|
|
@ -2803,7 +2804,7 @@ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
|
|||
pins = "gpio72", "gpio106";
|
||||
function = "qup2_se7";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
qup_spi0_cs: qup-spi0-cs-state {
|
||||
|
|
|
|||
Loading…
Reference in a new issue