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synced 2024-10-04 08:08:54 +00:00
ARM: S5PV210: Add support for VPLL
This patch adds the following. 1. Adds 'clk_sclk_hdmi27m' clock to represent the HDMI 27MHz clock. 2. Adds 'clk_vpllsrc; clock of type clksrc_clk to represent the input clock for VPLL. 3. Adds 'clk_sclk_vpll' clock of type clksrc_clk to represent the output of the MUX_VPLL mux. 4. Add clk_sclk_hdmi27m, clk_vpllsrc and clk_sclk_vpll to the list of clocks to be registered. 5. Adds boot time print of 'clk_sclk_vpll' clock rate. 6. Adds 'clk_fout_vpll' clock to plat-s5p such that it is reusable on other s5p platforms. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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f44cf78b6b
commit
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3 changed files with 70 additions and 2 deletions
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@ -173,6 +173,57 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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}
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}
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static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
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}
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static struct clk clk_sclk_hdmi27m = {
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.name = "sclk_hdmi27m",
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.id = -1,
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.rate = 27000000,
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};
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static struct clk *clkset_vpllsrc_list[] = {
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[0] = &clk_fin_vpll,
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[1] = &clk_sclk_hdmi27m,
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};
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static struct clksrc_sources clkset_vpllsrc = {
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.sources = clkset_vpllsrc_list,
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.nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
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};
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static struct clksrc_clk clk_vpllsrc = {
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.clk = {
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.name = "vpll_src",
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.id = -1,
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.enable = s5pv210_clk_mask0_ctrl,
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.ctrlbit = (1 << 7),
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},
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.sources = &clkset_vpllsrc,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
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};
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static struct clk *clkset_sclk_vpll_list[] = {
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[0] = &clk_vpllsrc.clk,
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[1] = &clk_fout_vpll,
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};
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static struct clksrc_sources clkset_sclk_vpll = {
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.sources = clkset_sclk_vpll_list,
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.nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
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};
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static struct clksrc_clk clk_sclk_vpll = {
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.clk = {
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.name = "sclk_vpll",
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.id = -1,
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},
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.sources = &clkset_sclk_vpll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
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};
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static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
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static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
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{
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{
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return clk_get_rate(clk->parent) / 2;
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return clk_get_rate(clk->parent) / 2;
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@ -402,12 +453,15 @@ static struct clksrc_clk *sysclks[] = {
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&clk_pclk_msys,
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&clk_pclk_msys,
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&clk_pclk_dsys,
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&clk_pclk_dsys,
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&clk_pclk_psys,
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&clk_pclk_psys,
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&clk_vpllsrc,
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&clk_sclk_vpll,
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};
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};
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void __init_or_cpufreq s5pv210_setup_clocks(void)
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void __init_or_cpufreq s5pv210_setup_clocks(void)
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{
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{
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struct clk *xtal_clk;
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struct clk *xtal_clk;
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unsigned long xtal;
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unsigned long xtal;
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unsigned long vpllsrc;
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unsigned long armclk;
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unsigned long armclk;
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unsigned long hclk_msys;
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unsigned long hclk_msys;
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unsigned long hclk_dsys;
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unsigned long hclk_dsys;
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@ -418,6 +472,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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unsigned long apll;
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unsigned long apll;
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unsigned long mpll;
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unsigned long mpll;
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unsigned long epll;
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unsigned long epll;
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unsigned long vpll;
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unsigned int ptr;
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unsigned int ptr;
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u32 clkdiv0, clkdiv1;
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u32 clkdiv0, clkdiv1;
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@ -440,13 +495,16 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
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apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
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mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
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mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
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epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
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epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
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vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
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vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
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clk_fout_apll.rate = apll;
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clk_fout_apll.rate = apll;
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clk_fout_mpll.rate = mpll;
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clk_fout_mpll.rate = mpll;
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clk_fout_epll.rate = epll;
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clk_fout_epll.rate = epll;
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clk_fout_vpll.rate = vpll;
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printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
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printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
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apll, mpll, epll);
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apll, mpll, epll, vpll);
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armclk = clk_get_rate(&clk_armclk.clk);
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armclk = clk_get_rate(&clk_armclk.clk);
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hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
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hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
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@ -470,6 +528,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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}
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}
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static struct clk *clks[] __initdata = {
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static struct clk *clks[] __initdata = {
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&clk_sclk_hdmi27m,
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};
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};
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void __init s5pv210_register_clocks(void)
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void __init s5pv210_register_clocks(void)
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@ -69,6 +69,13 @@ struct clk clk_fout_epll = {
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.ctrlbit = (1 << 31),
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.ctrlbit = (1 << 31),
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};
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};
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/* VPLL clock output */
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struct clk clk_fout_vpll = {
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.name = "fout_vpll",
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.id = -1,
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.ctrlbit = (1 << 31),
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};
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/* ARM clock */
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/* ARM clock */
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struct clk clk_arm = {
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struct clk clk_arm = {
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.name = "armclk",
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.name = "armclk",
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@ -133,6 +140,7 @@ static struct clk *s5p_clks[] __initdata = {
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&clk_fout_apll,
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&clk_fout_apll,
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&clk_fout_mpll,
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&clk_fout_mpll,
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&clk_fout_epll,
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&clk_fout_epll,
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&clk_fout_vpll,
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&clk_arm,
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&clk_arm,
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&clk_vpll,
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&clk_vpll,
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};
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};
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@ -27,6 +27,7 @@ extern struct clk clk_48m;
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extern struct clk clk_fout_apll;
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extern struct clk clk_fout_apll;
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extern struct clk clk_fout_mpll;
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extern struct clk clk_fout_mpll;
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extern struct clk clk_fout_epll;
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extern struct clk clk_fout_epll;
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extern struct clk clk_fout_vpll;
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extern struct clk clk_arm;
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extern struct clk clk_arm;
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extern struct clk clk_vpll;
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extern struct clk clk_vpll;
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