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arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodes 

Fillup the OSTM{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220227203744.18355-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2022-02-27 20:37:39 +00:00 committed by Geert Uytterhoeven
parent 8d3da65c4c
commit f458b7707c
1 changed files with 21 additions and 3 deletions
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24
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
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@ -629,18 +629,36 @@
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
ostm1: timer@12801400 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
ostm2: timer@12801800 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
};