mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
bus: mhi: Ensure correct ring update ordering with memory barrier
The ring element data, though being part of coherent memory, still need to be performed before updating the ring context to point to this new element. That can be guaranteed with a memory barrier (dma_wmb). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
parent
ec751369d6
commit
f49b6aeb5c
1 changed files with 7 additions and 0 deletions
|
@ -111,7 +111,14 @@ void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
|
|||
dma_addr_t db;
|
||||
|
||||
db = ring->iommu_base + (ring->wp - ring->base);
|
||||
|
||||
/*
|
||||
* Writes to the new ring element must be visible to the hardware
|
||||
* before letting h/w know there is new element to fetch.
|
||||
*/
|
||||
dma_wmb();
|
||||
*ring->ctxt_wp = db;
|
||||
|
||||
mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg,
|
||||
ring->db_addr, db);
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue