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drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)
v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
629b8ede8b
commit
f4caf58426
47 changed files with 204 additions and 204 deletions
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@ -736,7 +736,7 @@ int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
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for (i = 0; i < adev->num_vmhubs; i++)
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amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
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} else {
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amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
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amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0);
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}
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return 0;
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@ -315,7 +315,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
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ring->use_doorbell = true;
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ring->doorbell_index = adev->doorbell_index.kiq;
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ring->xcc_id = xcc_id;
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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if (xcc_id >= 1)
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ring->doorbell_index = adev->doorbell_index.xcc1_kiq_start +
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xcc_id - 1;
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@ -670,7 +670,7 @@ void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
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for (i = 0; i < 16; i++) {
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reg = hub->vm_context0_cntl + hub->ctx_distance * i;
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tmp = (hub_type == AMDGPU_GFXHUB_0) ?
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tmp = (hub_type == AMDGPU_GFXHUB(0)) ?
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RREG32_SOC15_IP(GC, reg) :
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RREG32_SOC15_IP(MMHUB, reg);
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@ -679,7 +679,7 @@ void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
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else
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tmp &= ~hub->vm_cntx_cntl_vm_fault;
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(hub_type == AMDGPU_GFXHUB_0) ?
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(hub_type == AMDGPU_GFXHUB(0)) ?
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WREG32_SOC15_IP(GC, reg, tmp) :
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WREG32_SOC15_IP(MMHUB, reg, tmp);
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}
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@ -2374,12 +2374,12 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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case AMDGPU_VM_OP_RESERVE_VMID:
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/* We only have requirement to reserve vmid from gfxhub */
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r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
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AMDGPU_GFXHUB_0);
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AMDGPU_GFXHUB(0));
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if (r)
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return r;
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break;
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case AMDGPU_VM_OP_UNRESERVE_VMID:
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amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
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amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB(0));
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break;
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default:
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return -EINVAL;
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@ -111,11 +111,14 @@ struct amdgpu_mem_stats;
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/* Reserve 4MB VRAM for page tables */
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#define AMDGPU_VM_RESERVED_VRAM (8ULL << 20)
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/* max number of VMHUB */
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#define AMDGPU_MAX_VMHUBS 3
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#define AMDGPU_GFXHUB_0 0
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#define AMDGPU_MMHUB_0 1
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#define AMDGPU_MMHUB_1 2
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/*
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* max number of VMHUB
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* layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1
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*/
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#define AMDGPU_MAX_VMHUBS 13
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#define AMDGPU_GFXHUB(x) (x)
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#define AMDGPU_MMHUB0(x) (8 + x)
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#define AMDGPU_MMHUB1(x) (8 + 4 + x)
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/* Reserve 2MB at top/bottom of address space for kernel use */
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#define AMDGPU_VA_RESERVED_SIZE (2ULL << 20)
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@ -4461,7 +4461,7 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
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ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
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else
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ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
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irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
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@ -4490,7 +4490,7 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
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ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
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ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
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+ (ring_id * GFX10_MEC_HPD_SIZE);
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
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irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
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@ -4978,7 +4978,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
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/* XXX SH_MEM regs */
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/* where to put LDS, scratch, GPUVM in FSA64 space */
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mutex_lock(&adev->srbm_mutex);
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for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
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for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
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nv_grbm_select(adev, 0, 0, 0, i);
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/* CP and shaders */
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WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
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@ -906,7 +906,7 @@ static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
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ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
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else
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ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
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irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
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@ -937,7 +937,7 @@ static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
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ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
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ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
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+ (ring_id * GFX11_MEC_HPD_SIZE);
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
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irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
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@ -1707,7 +1707,7 @@ static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
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/* XXX SH_MEM regs */
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/* where to put LDS, scratch, GPUVM in FSA64 space */
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mutex_lock(&adev->srbm_mutex);
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for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
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for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
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soc21_grbm_select(adev, 0, 0, 0, i);
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/* CP and shaders */
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WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
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@ -4190,7 +4190,7 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
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false : true;
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adev->gfxhub.funcs->set_fault_enable_default(adev, value);
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amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
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amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
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return 0;
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}
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@ -2005,7 +2005,7 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
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ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
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ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
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+ (ring_id * GFX9_MEC_HPD_SIZE);
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
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irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
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@ -2105,7 +2105,7 @@ static int gfx_v9_0_sw_init(void *handle)
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/* disable scheduler on the real ring */
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ring->no_scheduler = true;
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
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AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
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AMDGPU_RING_PRIO_DEFAULT, NULL);
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@ -2123,7 +2123,7 @@ static int gfx_v9_0_sw_init(void *handle)
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ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
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ring->is_sw_ring = true;
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hw_prio = amdgpu_sw_ring_priority(i);
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
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AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, hw_prio,
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NULL);
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/* XXX SH_MEM regs */
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/* where to put LDS, scratch, GPUVM in FSA64 space */
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mutex_lock(&adev->srbm_mutex);
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for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
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for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
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soc15_grbm_select(adev, 0, 0, 0, i, 0);
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/* CP and shaders */
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if (i == 0) {
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@ -1935,7 +1935,7 @@ static bool gfx_v9_4_2_query_uctl2_poison_status(struct amdgpu_device *adev)
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u32 status = 0;
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struct amdgpu_vmhub *hub;
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hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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status = RREG32(hub->vm_l2_pro_fault_status);
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/* reset page fault status */
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WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
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@ -757,7 +757,7 @@ static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,
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(adev->doorbell_index.mec_ring0 + ring_id) << 1;
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ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
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+ (ring_id * GFX9_MEC_HPD_SIZE);
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ring->vm_hub = AMDGPU_GFXHUB_0;
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ring->vm_hub = AMDGPU_GFXHUB(0);
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sprintf(ring->name, "comp_%d.%d.%d.%d",
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ring->xcc_id, ring->me, ring->pipe, ring->queue);
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@ -996,7 +996,7 @@ static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
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/* XXX SH_MEM regs */
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/* where to put LDS, scratch, GPUVM in FSA64 space */
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mutex_lock(&adev->srbm_mutex);
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for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
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for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
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for (j = 0; j < adev->gfx.num_xcd; j++) {
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soc15_grbm_select(adev, 0, 0, 0, i, j);
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/* CP and shaders */
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@ -40,7 +40,7 @@ static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev,
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uint32_t vmid,
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uint64_t page_table_base)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
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hub->ctx_addr_distance * vmid,
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@ -247,7 +247,7 @@ static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
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static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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unsigned num_level, block_size;
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uint32_t tmp;
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int i;
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@ -307,7 +307,7 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
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static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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unsigned i;
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for (i = 0 ; i < 18; ++i) {
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@ -338,7 +338,7 @@ static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
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static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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u32 tmp;
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u32 i;
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@ -411,7 +411,7 @@ static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
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static void gfxhub_v1_0_init(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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hub->ctx0_ptb_addr_lo32 =
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SOC15_REG_OFFSET(GC, 0,
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@ -42,7 +42,7 @@ static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev,
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uint32_t vmid,
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uint64_t page_table_base)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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int i;
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for (i = 0; i < adev->gfx.num_xcd; i++) {
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@ -291,7 +291,7 @@ static void gfxhub_v1_2_disable_identity_aperture(struct amdgpu_device *adev)
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static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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unsigned num_level, block_size;
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uint32_t tmp;
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int i, j;
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@ -357,7 +357,7 @@ static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev)
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static void gfxhub_v1_2_program_invalidation(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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unsigned i, j;
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for (j = 0; j < adev->gfx.num_xcd; j++) {
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@ -406,7 +406,7 @@ static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev)
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static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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u32 tmp;
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u32 i, j;
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@ -483,7 +483,7 @@ static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev,
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static void gfxhub_v1_2_init(struct amdgpu_device *adev)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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hub->ctx0_ptb_addr_lo32 =
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SOC15_REG_OFFSET(GC, 0,
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@ -120,7 +120,7 @@ static u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
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static void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
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uint64_t page_table_base)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
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WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
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hub->ctx_addr_distance * vmid,
|
||||
|
@ -282,7 +282,7 @@ static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -331,7 +331,7 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0 ; i < 18; ++i) {
|
||||
|
@ -360,7 +360,7 @@ static int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -433,7 +433,7 @@ static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {
|
|||
|
||||
static void gfxhub_v2_0_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(GC, 0,
|
||||
|
|
|
@ -123,7 +123,7 @@ static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)
|
|||
static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid,
|
||||
|
@ -291,7 +291,7 @@ static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -340,7 +340,7 @@ static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0 ; i < 18; ++i) {
|
||||
|
@ -381,7 +381,7 @@ static int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -462,7 +462,7 @@ static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {
|
|||
|
||||
static void gfxhub_v2_1_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(GC, 0,
|
||||
|
@ -651,7 +651,7 @@ static void gfxhub_v2_1_restore_regs(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v2_1_halt(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
int time = 1000;
|
||||
|
|
|
@ -119,7 +119,7 @@ static u64 gfxhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)
|
|||
static void gfxhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid,
|
||||
|
@ -290,7 +290,7 @@ static void gfxhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -339,7 +339,7 @@ static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v3_0_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0 ; i < 18; ++i) {
|
||||
|
@ -380,7 +380,7 @@ static int gfxhub_v3_0_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v3_0_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -463,7 +463,7 @@ static const struct amdgpu_vmhub_funcs gfxhub_v3_0_vmhub_funcs = {
|
|||
|
||||
static void gfxhub_v3_0_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(GC, 0,
|
||||
|
|
|
@ -122,7 +122,7 @@ static u64 gfxhub_v3_0_3_get_mc_fb_offset(struct amdgpu_device *adev)
|
|||
static void gfxhub_v3_0_3_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid,
|
||||
|
@ -295,7 +295,7 @@ static void gfxhub_v3_0_3_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -344,7 +344,7 @@ static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v3_0_3_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0 ; i < 18; ++i) {
|
||||
|
@ -373,7 +373,7 @@ static int gfxhub_v3_0_3_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void gfxhub_v3_0_3_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -451,7 +451,7 @@ static const struct amdgpu_vmhub_funcs gfxhub_v3_0_3_vmhub_funcs = {
|
|||
|
||||
static void gfxhub_v3_0_3_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(GC, 0,
|
||||
|
|
|
@ -76,7 +76,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|||
switch (state) {
|
||||
case AMDGPU_IRQ_STATE_DISABLE:
|
||||
/* MM HUB */
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
|
||||
/* GFX HUB */
|
||||
/* This works because this interrupt is only
|
||||
* enabled at init/resume and disabled in
|
||||
|
@ -84,11 +84,11 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|||
* change over the course of suspend/resume.
|
||||
*/
|
||||
if (!adev->in_s0ix)
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
|
||||
break;
|
||||
case AMDGPU_IRQ_STATE_ENABLE:
|
||||
/* MM HUB */
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);
|
||||
/* GFX HUB */
|
||||
/* This works because this interrupt is only
|
||||
* enabled at init/resume and disabled in
|
||||
|
@ -96,7 +96,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|||
* change over the course of suspend/resume.
|
||||
*/
|
||||
if (!adev->in_s0ix)
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
@ -149,7 +149,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
|
|||
* be updated to avoid reading an incorrect value due to
|
||||
* the new fast GRBM interface.
|
||||
*/
|
||||
if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
|
||||
if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
|
||||
(adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
|
||||
RREG32(hub->vm_l2_pro_fault_status);
|
||||
|
||||
|
@ -212,8 +212,7 @@ static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
|
|||
static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
|
||||
uint32_t vmhub)
|
||||
{
|
||||
return ((vmhub == AMDGPU_MMHUB_0 ||
|
||||
vmhub == AMDGPU_MMHUB_1) &&
|
||||
return ((vmhub == AMDGPU_MMHUB0(0)) &&
|
||||
(!amdgpu_sriov_vf(adev)));
|
||||
}
|
||||
|
||||
|
@ -249,7 +248,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
|||
unsigned int i;
|
||||
unsigned char hub_ip = 0;
|
||||
|
||||
hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
|
||||
hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ?
|
||||
GC_HWIP : MMHUB_HWIP;
|
||||
|
||||
spin_lock(&adev->gmc.invalidate_lock);
|
||||
|
@ -284,7 +283,7 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
|||
* Issue a dummy read to wait for the ACK register to be cleared
|
||||
* to avoid a false ACK due to the new fast GRBM interface.
|
||||
*/
|
||||
if ((vmhub == AMDGPU_GFXHUB_0) &&
|
||||
if ((vmhub == AMDGPU_GFXHUB(0)) &&
|
||||
(adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
|
||||
RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
|
||||
hub->eng_distance * eng, hub_ip);
|
||||
|
@ -361,19 +360,19 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
|
|||
|
||||
mutex_lock(&adev->mman.gtt_window_lock);
|
||||
|
||||
if (vmhub == AMDGPU_MMHUB_0) {
|
||||
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
|
||||
if (vmhub == AMDGPU_MMHUB0(0)) {
|
||||
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB0(0), 0);
|
||||
mutex_unlock(&adev->mman.gtt_window_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
BUG_ON(vmhub != AMDGPU_GFXHUB_0);
|
||||
BUG_ON(vmhub != AMDGPU_GFXHUB(0));
|
||||
|
||||
if (!adev->mman.buffer_funcs_enabled ||
|
||||
!adev->ib_pool_ready ||
|
||||
amdgpu_in_reset(adev) ||
|
||||
ring->sched.ready == false) {
|
||||
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
|
||||
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB(0), 0);
|
||||
mutex_unlock(&adev->mman.gtt_window_lock);
|
||||
return;
|
||||
}
|
||||
|
@ -466,7 +465,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
|
|||
i, flush_type);
|
||||
} else {
|
||||
gmc_v10_0_flush_gpu_tlb(adev, vmid,
|
||||
AMDGPU_GFXHUB_0, flush_type);
|
||||
AMDGPU_GFXHUB(0), flush_type);
|
||||
}
|
||||
if (!adev->enable_mes)
|
||||
break;
|
||||
|
@ -534,7 +533,7 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid
|
|||
if (ring->is_mes_queue)
|
||||
return;
|
||||
|
||||
if (ring->vm_hub == AMDGPU_GFXHUB_0)
|
||||
if (ring->vm_hub == AMDGPU_GFXHUB(0))
|
||||
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
|
||||
else
|
||||
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
|
||||
|
@ -1075,9 +1074,9 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
|
|||
if (!adev->in_s0ix)
|
||||
adev->gfxhub.funcs->set_fault_enable_default(adev, value);
|
||||
adev->mmhub.funcs->set_fault_enable_default(adev, value);
|
||||
gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
|
||||
gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
|
||||
if (!adev->in_s0ix)
|
||||
gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
|
||||
gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
|
||||
|
||||
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
||||
(unsigned)(adev->gmc.gart_size >> 20),
|
||||
|
|
|
@ -64,7 +64,7 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|||
switch (state) {
|
||||
case AMDGPU_IRQ_STATE_DISABLE:
|
||||
/* MM HUB */
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
|
||||
/* GFX HUB */
|
||||
/* This works because this interrupt is only
|
||||
* enabled at init/resume and disabled in
|
||||
|
@ -72,11 +72,11 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|||
* change over the course of suspend/resume.
|
||||
*/
|
||||
if (!adev->in_s0ix)
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
|
||||
break;
|
||||
case AMDGPU_IRQ_STATE_ENABLE:
|
||||
/* MM HUB */
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);
|
||||
/* GFX HUB */
|
||||
/* This works because this interrupt is only
|
||||
* enabled at init/resume and disabled in
|
||||
|
@ -84,7 +84,7 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|||
* change over the course of suspend/resume.
|
||||
*/
|
||||
if (!adev->in_s0ix)
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
|
||||
amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
@ -110,7 +110,7 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,
|
|||
* be updated to avoid reading an incorrect value due to
|
||||
* the new fast GRBM interface.
|
||||
*/
|
||||
if (entry->vmid_src == AMDGPU_GFXHUB_0)
|
||||
if (entry->vmid_src == AMDGPU_GFXHUB(0))
|
||||
RREG32(hub->vm_l2_pro_fault_status);
|
||||
|
||||
status = RREG32(hub->vm_l2_pro_fault_status);
|
||||
|
@ -170,7 +170,7 @@ static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev)
|
|||
static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev,
|
||||
uint32_t vmhub)
|
||||
{
|
||||
return ((vmhub == AMDGPU_MMHUB_0) &&
|
||||
return ((vmhub == AMDGPU_MMHUB0(0)) &&
|
||||
(!amdgpu_sriov_vf(adev)));
|
||||
}
|
||||
|
||||
|
@ -202,7 +202,7 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
|||
unsigned int i;
|
||||
unsigned char hub_ip = 0;
|
||||
|
||||
hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
|
||||
hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ?
|
||||
GC_HWIP : MMHUB_HWIP;
|
||||
|
||||
spin_lock(&adev->gmc.invalidate_lock);
|
||||
|
@ -251,7 +251,7 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
|||
hub->eng_distance * eng, 0, hub_ip);
|
||||
|
||||
/* Issue additional private vm invalidation to MMHUB */
|
||||
if ((vmhub != AMDGPU_GFXHUB_0) &&
|
||||
if ((vmhub != AMDGPU_GFXHUB(0)) &&
|
||||
(hub->vm_l2_bank_select_reserved_cid2) &&
|
||||
!amdgpu_sriov_vf(adev)) {
|
||||
inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
|
||||
|
@ -284,7 +284,7 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
|||
static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint32_t vmhub, uint32_t flush_type)
|
||||
{
|
||||
if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
|
||||
if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron)
|
||||
return;
|
||||
|
||||
/* flush hdp cache */
|
||||
|
@ -369,7 +369,7 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
|
|||
i, flush_type);
|
||||
} else {
|
||||
gmc_v11_0_flush_gpu_tlb(adev, vmid,
|
||||
AMDGPU_GFXHUB_0, flush_type);
|
||||
AMDGPU_GFXHUB(0), flush_type);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -435,7 +435,7 @@ static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid
|
|||
if (ring->is_mes_queue)
|
||||
return;
|
||||
|
||||
if (ring->vm_hub == AMDGPU_GFXHUB_0)
|
||||
if (ring->vm_hub == AMDGPU_GFXHUB(0))
|
||||
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
|
||||
else
|
||||
reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
|
||||
|
@ -886,7 +886,7 @@ static int gmc_v11_0_sw_fini(void *handle)
|
|||
static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev)
|
||||
{
|
||||
if (amdgpu_sriov_vf(adev)) {
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32(hub->vm_contexts_disable, 0);
|
||||
return;
|
||||
|
@ -921,7 +921,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
|
|||
false : true;
|
||||
|
||||
adev->mmhub.funcs->set_fault_enable_default(adev, value);
|
||||
gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
|
||||
gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
|
||||
|
||||
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
||||
(unsigned)(adev->gmc.gart_size >> 20),
|
||||
|
|
|
@ -491,20 +491,20 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|||
* fini/suspend, so the overall state doesn't
|
||||
* change over the course of suspend/resume.
|
||||
*/
|
||||
if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
|
||||
if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
|
||||
continue;
|
||||
|
||||
if (j == AMDGPU_GFXHUB_0)
|
||||
tmp = RREG32_SOC15_IP(GC, reg);
|
||||
else
|
||||
if (j >= AMDGPU_MMHUB0(0))
|
||||
tmp = RREG32_SOC15_IP(MMHUB, reg);
|
||||
else
|
||||
tmp = RREG32_SOC15_IP(GC, reg);
|
||||
|
||||
tmp &= ~bits;
|
||||
|
||||
if (j == AMDGPU_GFXHUB_0)
|
||||
WREG32_SOC15_IP(GC, reg, tmp);
|
||||
else
|
||||
if (j >= AMDGPU_MMHUB0(0))
|
||||
WREG32_SOC15_IP(MMHUB, reg, tmp);
|
||||
else
|
||||
WREG32_SOC15_IP(GC, reg, tmp);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
@ -519,20 +519,20 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|||
* fini/suspend, so the overall state doesn't
|
||||
* change over the course of suspend/resume.
|
||||
*/
|
||||
if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
|
||||
if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
|
||||
continue;
|
||||
|
||||
if (j == AMDGPU_GFXHUB_0)
|
||||
tmp = RREG32_SOC15_IP(GC, reg);
|
||||
else
|
||||
if (j >= AMDGPU_MMHUB0(0))
|
||||
tmp = RREG32_SOC15_IP(MMHUB, reg);
|
||||
else
|
||||
tmp = RREG32_SOC15_IP(GC, reg);
|
||||
|
||||
tmp |= bits;
|
||||
|
||||
if (j == AMDGPU_GFXHUB_0)
|
||||
WREG32_SOC15_IP(GC, reg, tmp);
|
||||
else
|
||||
if (j >= AMDGPU_MMHUB0(0))
|
||||
WREG32_SOC15_IP(MMHUB, reg, tmp);
|
||||
else
|
||||
WREG32_SOC15_IP(GC, reg, tmp);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
@ -605,13 +605,13 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
|
|||
|
||||
if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
|
||||
hub_name = "mmhub0";
|
||||
hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
} else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
|
||||
hub_name = "mmhub1";
|
||||
hub = &adev->vmhub[AMDGPU_MMHUB_1];
|
||||
hub = &adev->vmhub[AMDGPU_MMHUB1(0)];
|
||||
} else {
|
||||
hub_name = "gfxhub0";
|
||||
hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
}
|
||||
|
||||
memset(&task_info, 0, sizeof(struct amdgpu_task_info));
|
||||
|
@ -636,7 +636,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
|
|||
* be updated to avoid reading an incorrect value due to
|
||||
* the new fast GRBM interface.
|
||||
*/
|
||||
if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
|
||||
if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
|
||||
(adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2)))
|
||||
RREG32(hub->vm_l2_pro_fault_status);
|
||||
|
||||
|
@ -649,7 +649,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
|
|||
dev_err(adev->dev,
|
||||
"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
|
||||
status);
|
||||
if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
|
||||
if (hub == &adev->vmhub[AMDGPU_GFXHUB(0)]) {
|
||||
dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
|
||||
cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
|
||||
gfxhub_client_ids[cid],
|
||||
|
@ -759,8 +759,8 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
|
|||
adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3))
|
||||
return false;
|
||||
|
||||
return ((vmhub == AMDGPU_MMHUB_0 ||
|
||||
vmhub == AMDGPU_MMHUB_1) &&
|
||||
return ((vmhub == AMDGPU_MMHUB0(0) ||
|
||||
vmhub == AMDGPU_MMHUB1(0)) &&
|
||||
(!amdgpu_sriov_vf(adev)) &&
|
||||
(!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
|
||||
(adev->apu_flags & AMD_APU_IS_PICASSO))));
|
||||
|
@ -849,11 +849,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
|
|||
if (use_semaphore) {
|
||||
for (j = 0; j < adev->usec_timeout; j++) {
|
||||
/* a read return value of 1 means semaphore acquire */
|
||||
if (vmhub == AMDGPU_GFXHUB_0)
|
||||
tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
|
||||
else
|
||||
if (vmhub >= AMDGPU_MMHUB0(0))
|
||||
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
|
||||
|
||||
else
|
||||
tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
|
||||
if (tmp & 0x1)
|
||||
break;
|
||||
udelay(1);
|
||||
|
@ -864,27 +863,26 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
|
|||
}
|
||||
|
||||
do {
|
||||
if (vmhub == AMDGPU_GFXHUB_0)
|
||||
WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
|
||||
else
|
||||
if (vmhub >= AMDGPU_MMHUB0(0))
|
||||
WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
|
||||
else
|
||||
WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
|
||||
|
||||
/*
|
||||
* Issue a dummy read to wait for the ACK register to
|
||||
* be cleared to avoid a false ACK due to the new fast
|
||||
* GRBM interface.
|
||||
*/
|
||||
if ((vmhub == AMDGPU_GFXHUB_0) &&
|
||||
if ((vmhub == AMDGPU_GFXHUB(0)) &&
|
||||
(adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2)))
|
||||
RREG32_NO_KIQ(hub->vm_inv_eng0_req +
|
||||
hub->eng_distance * eng);
|
||||
|
||||
for (j = 0; j < adev->usec_timeout; j++) {
|
||||
if (vmhub == AMDGPU_GFXHUB_0)
|
||||
tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
|
||||
else
|
||||
if (vmhub >= AMDGPU_MMHUB0(0))
|
||||
tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
|
||||
|
||||
else
|
||||
tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
|
||||
if (tmp & (1 << vmid))
|
||||
break;
|
||||
udelay(1);
|
||||
|
@ -900,10 +898,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
|
|||
* add semaphore release after invalidation,
|
||||
* write with 0 means semaphore release
|
||||
*/
|
||||
if (vmhub == AMDGPU_GFXHUB_0)
|
||||
WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
|
||||
if (vmhub >= AMDGPU_MMHUB0(0))
|
||||
WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
|
||||
else
|
||||
WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
|
||||
WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
|
||||
}
|
||||
|
||||
spin_unlock(&adev->gmc.invalidate_lock);
|
||||
|
@ -994,7 +992,7 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
|
|||
i, flush_type);
|
||||
} else {
|
||||
gmc_v9_0_flush_gpu_tlb(adev, vmid,
|
||||
AMDGPU_GFXHUB_0, flush_type);
|
||||
AMDGPU_GFXHUB(0), flush_type);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
@ -1060,10 +1058,10 @@ static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
|
|||
uint32_t reg;
|
||||
|
||||
/* Do nothing because there's no lut register for mmhub1. */
|
||||
if (ring->vm_hub == AMDGPU_MMHUB_1)
|
||||
if (ring->vm_hub == AMDGPU_MMHUB1(0))
|
||||
return;
|
||||
|
||||
if (ring->vm_hub == AMDGPU_GFXHUB_0)
|
||||
if (ring->vm_hub == AMDGPU_GFXHUB(0))
|
||||
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
|
||||
else
|
||||
reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
|
||||
|
@ -1947,7 +1945,7 @@ static int gmc_v9_0_hw_init(void *handle)
|
|||
adev->mmhub.funcs->set_fault_enable_default(adev, value);
|
||||
}
|
||||
for (i = 0; i < adev->num_vmhubs; ++i) {
|
||||
if (adev->in_s0ix && (i == AMDGPU_GFXHUB_0))
|
||||
if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0)))
|
||||
continue;
|
||||
gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
|
||||
}
|
||||
|
|
|
@ -485,7 +485,7 @@ int jpeg_v1_0_sw_init(void *handle)
|
|||
return r;
|
||||
|
||||
ring = &adev->jpeg.inst->ring_dec;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "jpeg_dec");
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
|
||||
0, AMDGPU_RING_PRIO_DEFAULT, NULL);
|
||||
|
|
|
@ -86,7 +86,7 @@ static int jpeg_v2_0_sw_init(void *handle)
|
|||
ring = &adev->jpeg.inst->ring_dec;
|
||||
ring->use_doorbell = true;
|
||||
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "jpeg_dec");
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
|
||||
0, AMDGPU_RING_PRIO_DEFAULT, NULL);
|
||||
|
|
|
@ -128,9 +128,9 @@ static int jpeg_v2_5_sw_init(void *handle)
|
|||
ring = &adev->jpeg.inst[i].ring_dec;
|
||||
ring->use_doorbell = true;
|
||||
if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
|
||||
ring->vm_hub = AMDGPU_MMHUB_1;
|
||||
ring->vm_hub = AMDGPU_MMHUB1(0);
|
||||
else
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
|
||||
sprintf(ring->name, "jpeg_dec_%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,
|
||||
|
|
|
@ -101,7 +101,7 @@ static int jpeg_v3_0_sw_init(void *handle)
|
|||
ring = &adev->jpeg.inst->ring_dec;
|
||||
ring->use_doorbell = true;
|
||||
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "jpeg_dec");
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
|
||||
AMDGPU_RING_PRIO_DEFAULT, NULL);
|
||||
|
|
|
@ -108,7 +108,7 @@ static int jpeg_v4_0_sw_init(void *handle)
|
|||
ring = &adev->jpeg.inst->ring_dec;
|
||||
ring->use_doorbell = true;
|
||||
ring->doorbell_index = amdgpu_sriov_vf(adev) ? (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4) : ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1);
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
|
||||
sprintf(ring->name, "jpeg_dec");
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
|
||||
|
|
|
@ -149,7 +149,7 @@ static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
|
|||
{
|
||||
struct amdgpu_device *adev = mes->adev;
|
||||
union MESAPI__ADD_QUEUE mes_add_queue_pkt;
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
|
||||
|
||||
memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
|
||||
|
|
|
@ -164,7 +164,7 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
|
|||
{
|
||||
struct amdgpu_device *adev = mes->adev;
|
||||
union MESAPI__ADD_QUEUE mes_add_queue_pkt;
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
|
||||
uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
|
||||
|
||||
memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
|
||||
|
|
|
@ -54,7 +54,7 @@ static u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
|
|||
static void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid,
|
||||
|
@ -229,7 +229,7 @@ static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned num_level, block_size;
|
||||
uint32_t tmp;
|
||||
int i;
|
||||
|
@ -285,7 +285,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -338,7 +338,7 @@ static int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -415,7 +415,7 @@ static void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool
|
|||
|
||||
static void mmhub_v1_0_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
|
|
|
@ -54,7 +54,7 @@ static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)
|
|||
static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
|
||||
|
@ -261,7 +261,7 @@ static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned num_level, block_size;
|
||||
uint32_t tmp;
|
||||
int i;
|
||||
|
@ -319,7 +319,7 @@ static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -348,7 +348,7 @@ static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -425,7 +425,7 @@ static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool
|
|||
|
||||
static void mmhub_v1_7_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
|
|
|
@ -53,7 +53,7 @@ static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev)
|
|||
static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
|
||||
|
@ -253,7 +253,7 @@ static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned num_level, block_size;
|
||||
uint32_t tmp;
|
||||
int i;
|
||||
|
@ -311,7 +311,7 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -352,7 +352,7 @@ static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -426,7 +426,7 @@ static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool
|
|||
|
||||
static void mmhub_v1_8_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
|
|
|
@ -187,7 +187,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
|
|||
static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid,
|
||||
|
@ -362,7 +362,7 @@ static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -412,7 +412,7 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -441,7 +441,7 @@ static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -520,7 +520,7 @@ static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
|
|||
|
||||
static void mmhub_v2_0_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
|
|
|
@ -121,7 +121,7 @@ static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev,
|
|||
uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
|
||||
|
@ -280,7 +280,7 @@ static void mmhub_v2_3_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -330,7 +330,7 @@ static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -373,7 +373,7 @@ static int mmhub_v2_3_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -446,7 +446,7 @@ static const struct amdgpu_vmhub_funcs mmhub_v2_3_vmhub_funcs = {
|
|||
|
||||
static void mmhub_v2_3_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
|
|
|
@ -136,7 +136,7 @@ mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
|
|||
static void mmhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid,
|
||||
|
@ -319,7 +319,7 @@ static void mmhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -369,7 +369,7 @@ static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -398,7 +398,7 @@ static int mmhub_v3_0_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -477,7 +477,7 @@ static const struct amdgpu_vmhub_funcs mmhub_v3_0_vmhub_funcs = {
|
|||
|
||||
static void mmhub_v3_0_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
|
|
|
@ -138,7 +138,7 @@ static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev,
|
|||
uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid,
|
||||
|
@ -306,7 +306,7 @@ static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -356,7 +356,7 @@ static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -385,7 +385,7 @@ static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -459,7 +459,7 @@ static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = {
|
|||
|
||||
static void mmhub_v3_0_1_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
|
|
|
@ -129,7 +129,7 @@ mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev,
|
|||
static void mmhub_v3_0_2_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
||||
uint64_t page_table_base)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
hub->ctx_addr_distance * vmid,
|
||||
|
@ -311,7 +311,7 @@ static void mmhub_v3_0_2_disable_identity_aperture(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
int i;
|
||||
uint32_t tmp;
|
||||
|
||||
|
@ -361,7 +361,7 @@ static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_2_program_invalidation(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -390,7 +390,7 @@ static int mmhub_v3_0_2_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v3_0_2_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i;
|
||||
|
||||
|
@ -469,7 +469,7 @@ static const struct amdgpu_vmhub_funcs mmhub_v3_0_2_vmhub_funcs = {
|
|||
|
||||
static void mmhub_v3_0_2_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
hub->ctx0_ptb_addr_lo32 =
|
||||
SOC15_REG_OFFSET(MMHUB, 0,
|
||||
|
|
|
@ -57,7 +57,7 @@ static u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
|
|||
static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
|
||||
uint32_t vmid, uint64_t value)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
|
||||
WREG32_SOC15_OFFSET(MMHUB, 0,
|
||||
mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
|
||||
|
@ -294,7 +294,7 @@ static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
|
|||
|
||||
static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned int num_level, block_size;
|
||||
uint32_t tmp;
|
||||
int i;
|
||||
|
@ -363,7 +363,7 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
|
|||
static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
|
||||
int hubid)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < 18; ++i) {
|
||||
|
@ -404,7 +404,7 @@ static int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
|
|||
|
||||
static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
|
||||
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
|
||||
u32 tmp;
|
||||
u32 i, j;
|
||||
|
||||
|
@ -507,8 +507,8 @@ static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool
|
|||
|
||||
static void mmhub_v9_4_init(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
|
||||
{&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
|
||||
struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] = {
|
||||
&adev->vmhub[AMDGPU_MMHUB0(0)], &adev->vmhub[AMDGPU_MMHUB1(0)]};
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
|
||||
|
|
|
@ -1825,12 +1825,12 @@ static int sdma_v4_0_sw_init(void *handle)
|
|||
|
||||
/*
|
||||
* On Arcturus, SDMA instance 5~7 has a different vmhub
|
||||
* type(AMDGPU_MMHUB_1).
|
||||
* type(AMDGPU_MMHUB1).
|
||||
*/
|
||||
if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
|
||||
ring->vm_hub = AMDGPU_MMHUB_1;
|
||||
ring->vm_hub = AMDGPU_MMHUB1(0);
|
||||
else
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
|
||||
sprintf(ring->name, "sdma%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
|
||||
|
@ -1851,9 +1851,9 @@ static int sdma_v4_0_sw_init(void *handle)
|
|||
ring->doorbell_index += 0x400;
|
||||
|
||||
if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
|
||||
ring->vm_hub = AMDGPU_MMHUB_1;
|
||||
ring->vm_hub = AMDGPU_MMHUB1(0);
|
||||
else
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
|
||||
sprintf(ring->name, "page%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 1024,
|
||||
|
|
|
@ -1309,7 +1309,7 @@ static int sdma_v4_4_2_sw_init(void *handle)
|
|||
|
||||
/* doorbell size is 2 dwords, get DWORD offset */
|
||||
ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
|
||||
sprintf(ring->name, "sdma%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
|
||||
|
@ -1328,7 +1328,7 @@ static int sdma_v4_4_2_sw_init(void *handle)
|
|||
*/
|
||||
ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
|
||||
ring->doorbell_index += 0x400;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
|
||||
sprintf(ring->name, "page%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 1024,
|
||||
|
|
|
@ -1389,7 +1389,7 @@ static int sdma_v5_0_sw_init(void *handle)
|
|||
(adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
|
||||
: (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
|
||||
|
||||
ring->vm_hub = AMDGPU_GFXHUB_0;
|
||||
ring->vm_hub = AMDGPU_GFXHUB(0);
|
||||
sprintf(ring->name, "sdma%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
|
||||
(i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
|
||||
|
|
|
@ -1253,7 +1253,7 @@ static int sdma_v5_2_sw_init(void *handle)
|
|||
ring->doorbell_index =
|
||||
(adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
|
||||
|
||||
ring->vm_hub = AMDGPU_GFXHUB_0;
|
||||
ring->vm_hub = AMDGPU_GFXHUB(0);
|
||||
sprintf(ring->name, "sdma%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
|
||||
AMDGPU_SDMA_IRQ_INSTANCE0 + i,
|
||||
|
|
|
@ -1298,7 +1298,7 @@ static int sdma_v6_0_sw_init(void *handle)
|
|||
ring->doorbell_index =
|
||||
(adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
|
||||
|
||||
ring->vm_hub = AMDGPU_GFXHUB_0;
|
||||
ring->vm_hub = AMDGPU_GFXHUB(0);
|
||||
sprintf(ring->name, "sdma%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 1024,
|
||||
&adev->sdma.trap_irq,
|
||||
|
|
|
@ -444,7 +444,7 @@ static int uvd_v7_0_sw_init(void *handle)
|
|||
continue;
|
||||
if (!amdgpu_sriov_vf(adev)) {
|
||||
ring = &adev->uvd.inst[j].ring;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "uvd_%d", ring->me);
|
||||
r = amdgpu_ring_init(adev, ring, 512,
|
||||
&adev->uvd.inst[j].irq, 0,
|
||||
|
@ -455,7 +455,7 @@ static int uvd_v7_0_sw_init(void *handle)
|
|||
|
||||
for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
|
||||
ring = &adev->uvd.inst[j].ring_enc[i];
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i);
|
||||
if (amdgpu_sriov_vf(adev)) {
|
||||
ring->use_doorbell = true;
|
||||
|
|
|
@ -466,7 +466,7 @@ static int vce_v4_0_sw_init(void *handle)
|
|||
enum amdgpu_ring_priority_level hw_prio = amdgpu_vce_get_ring_prio(i);
|
||||
|
||||
ring = &adev->vce.ring[i];
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "vce%d", i);
|
||||
if (amdgpu_sriov_vf(adev)) {
|
||||
/* DOORBELL only works under SRIOV */
|
||||
|
|
|
@ -120,7 +120,7 @@ static int vcn_v1_0_sw_init(void *handle)
|
|||
return r;
|
||||
|
||||
ring = &adev->vcn.inst->ring_dec;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "vcn_dec");
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
|
||||
AMDGPU_RING_PRIO_DEFAULT, NULL);
|
||||
|
@ -142,7 +142,7 @@ static int vcn_v1_0_sw_init(void *handle)
|
|||
enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
|
||||
|
||||
ring = &adev->vcn.inst->ring_enc[i];
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "vcn_enc%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
|
||||
hw_prio, NULL);
|
||||
|
|
|
@ -129,7 +129,7 @@ static int vcn_v2_0_sw_init(void *handle)
|
|||
|
||||
ring->use_doorbell = true;
|
||||
ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
|
||||
sprintf(ring->name, "vcn_dec");
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
|
||||
|
@ -160,7 +160,7 @@ static int vcn_v2_0_sw_init(void *handle)
|
|||
|
||||
ring = &adev->vcn.inst->ring_enc[i];
|
||||
ring->use_doorbell = true;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
if (!amdgpu_sriov_vf(adev))
|
||||
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
|
||||
else
|
||||
|
|
|
@ -188,9 +188,9 @@ static int vcn_v2_5_sw_init(void *handle)
|
|||
(amdgpu_sriov_vf(adev) ? 2*j : 8*j);
|
||||
|
||||
if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
|
||||
ring->vm_hub = AMDGPU_MMHUB_1;
|
||||
ring->vm_hub = AMDGPU_MMHUB1(0);
|
||||
else
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
|
||||
sprintf(ring->name, "vcn_dec_%d", j);
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
|
||||
|
@ -208,9 +208,9 @@ static int vcn_v2_5_sw_init(void *handle)
|
|||
(amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j));
|
||||
|
||||
if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
|
||||
ring->vm_hub = AMDGPU_MMHUB_1;
|
||||
ring->vm_hub = AMDGPU_MMHUB1(0);
|
||||
else
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
|
||||
sprintf(ring->name, "vcn_enc_%d.%d", j, i);
|
||||
r = amdgpu_ring_init(adev, ring, 512,
|
||||
|
|
|
@ -189,7 +189,7 @@ static int vcn_v3_0_sw_init(void *handle)
|
|||
} else {
|
||||
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
|
||||
}
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "vcn_dec_%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
|
||||
AMDGPU_RING_PRIO_DEFAULT,
|
||||
|
@ -213,7 +213,7 @@ static int vcn_v3_0_sw_init(void *handle)
|
|||
} else {
|
||||
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
|
||||
}
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "vcn_enc_%d.%d", i, j);
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
|
||||
hw_prio, &adev->vcn.inst[i].sched_score);
|
||||
|
|
|
@ -149,7 +149,7 @@ static int vcn_v4_0_sw_init(void *handle)
|
|||
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1;
|
||||
else
|
||||
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
|
||||
ring->vm_hub = AMDGPU_MMHUB_0;
|
||||
ring->vm_hub = AMDGPU_MMHUB0(0);
|
||||
sprintf(ring->name, "vcn_unified_%d", i);
|
||||
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
|
||||
|
|
Loading…
Reference in a new issue