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pinctrl: rockchip: fix RK3308 pinmux bits

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[ Upstream commit 1f3e25a068 ]

Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong,
pointing to non-existing registers.

Fix the entire table.

Also add a comment in front of each entry with the same string that appears
in the datasheet to make the table easier to compare with the docs.

This fix has been tested on real hardware for the gpio3b3_sel entry.

Fixes: 7825aeb7b2 ("pinctrl: rockchip: add rk3308 SoC support")
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220420142432.248565-1-luca.ceresoli@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Luca Ceresoli 2022-04-20 16:24:31 +02:00 committed by Greg Kroah-Hartman
parent 9ef33d23f8
commit f4dad5a48d
1 changed files with 30 additions and 15 deletions
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45
drivers/pinctrl/pinctrl-rockchip.c
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@ -663,95 +663,110 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
{
/* gpio1b6_sel */
.num = 1,
.pin = 14,
.reg = 0x28,
.bit = 12,
.mask = 0xf
}, {
/* gpio1b7_sel */
.num = 1,
.pin = 15,
.reg = 0x2c,
.bit = 0,
.mask = 0x3
}, {
/* gpio1c2_sel */
.num = 1,
.pin = 18,
.reg = 0x30,
.bit = 4,
.mask = 0xf
}, {
/* gpio1c3_sel */
.num = 1,
.pin = 19,
.reg = 0x30,
.bit = 8,
.mask = 0xf
}, {
/* gpio1c4_sel */
.num = 1,
.pin = 20,
.reg = 0x30,
.bit = 12,
.mask = 0xf
}, {
/* gpio1c5_sel */
.num = 1,
.pin = 21,
.reg = 0x34,
.bit = 0,
.mask = 0xf
}, {
/* gpio1c6_sel */
.num = 1,
.pin = 22,
.reg = 0x34,
.bit = 4,
.mask = 0xf
}, {
/* gpio1c7_sel */
.num = 1,
.pin = 23,
.reg = 0x34,
.bit = 8,
.mask = 0xf
}, {
/* gpio3b4_sel */
.num = 3,
.pin = 12,
.reg = 0x68,
.bit = 8,
.mask = 0xf
}, {
/* gpio3b5_sel */
.num = 3,
.pin = 13,
.reg = 0x68,
.bit = 12,
.mask = 0xf
}, {
/* gpio2a2_sel */
.num = 2,
.pin = 2,
.reg = 0x608,
.bit = 0,
.mask = 0x7
.reg = 0x40,
.bit = 4,
.mask = 0x3
}, {
/* gpio2a3_sel */
.num = 2,
.pin = 3,
.reg = 0x608,
.bit = 4,
.mask = 0x7
.reg = 0x40,
.bit = 6,
.mask = 0x3
}, {
/* gpio2c0_sel */
.num = 2,
.pin = 16,
.reg = 0x610,
.bit = 8,
.mask = 0x7
.reg = 0x50,
.bit = 0,
.mask = 0x3
}, {
/* gpio3b2_sel */
.num = 3,
.pin = 10,
.reg = 0x610,
.bit = 0,
.mask = 0x7
.reg = 0x68,
.bit = 4,
.mask = 0x3
}, {
/* gpio3b3_sel */
.num = 3,
.pin = 11,
.reg = 0x610,
.bit = 4,
.mask = 0x7
.reg = 0x68,
.bit = 6,
.mask = 0x3
},
};