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MIPS: asm: hazards: Add MIPSR6 definitions

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Add the MIPSR6 related definitions to MIPS hazards

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Markos Chandras 2014-11-13 11:52:22 +00:00
parent 34c56fc1c1
commit f52fca9713
1 changed files with 5 additions and 4 deletions
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9
arch/mips/include/asm/hazards.h
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@ -11,6 +11,7 @@
#define _ASM_HAZARDS_H
#include <linux/stringify.h>
#include <asm/compiler.h>
#define ___ssnop \
sll $0, $0, 1
@ -21,7 +22,7 @@
/*
* TLB hazards
*/
#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
/*
* MIPSR2 defines ehb for hazard avoidance
@ -58,7 +59,7 @@ do { \
unsigned long tmp; \
\
__asm__ __volatile__( \
" .set mips64r2 \n" \
" .set "MIPS_ISA_LEVEL" \n" \
" dla %0, 1f \n" \
" jr.hb %0 \n" \
" .set mips0 \n" \
@ -132,7 +133,7 @@ do { \
#define instruction_hazard() \
do { \
if (cpu_has_mips_r2) \
if (cpu_has_mips_r2_r6) \
__instruction_hazard(); \
} while (0)
@ -240,7 +241,7 @@ do { \
#define __disable_fpu_hazard
#elif defined(CONFIG_CPU_MIPSR2)
#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
#define __enable_fpu_hazard \
___ehb