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MIPS: asm: hazards: Add MIPSR6 definitions
Add the MIPSR6 related definitions to MIPS hazards Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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commit
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1 changed files with 5 additions and 4 deletions
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@ -11,6 +11,7 @@
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#define _ASM_HAZARDS_H
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#include <linux/stringify.h>
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#include <asm/compiler.h>
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#define ___ssnop \
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sll $0, $0, 1
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@ -21,7 +22,7 @@
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/*
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* TLB hazards
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*/
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#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
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/*
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* MIPSR2 defines ehb for hazard avoidance
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@ -58,7 +59,7 @@ do { \
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unsigned long tmp; \
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\
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__asm__ __volatile__( \
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" .set mips64r2 \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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" dla %0, 1f \n" \
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" jr.hb %0 \n" \
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" .set mips0 \n" \
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@ -132,7 +133,7 @@ do { \
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#define instruction_hazard() \
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do { \
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if (cpu_has_mips_r2) \
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if (cpu_has_mips_r2_r6) \
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__instruction_hazard(); \
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} while (0)
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@ -240,7 +241,7 @@ do { \
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#define __disable_fpu_hazard
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#elif defined(CONFIG_CPU_MIPSR2)
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#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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#define __enable_fpu_hazard \
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___ehb
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