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usb: dwc3: Add splitdisable quirk for Hisilicon Kirin Soc
SPLIT_BOUNDARY_DISABLE should be set for DesignWare USB3 DRD Core of Hisilicon Kirin Soc when dwc3 core act as host. [mchehab: dropped a dev_dbg() as only traces are now allowwed on this driver] Signed-off-by: Yu Chen <chenyu56@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Felipe Balbi <balbi@kernel.org>
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2a87445af2
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2 changed files with 32 additions and 0 deletions
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@ -119,6 +119,7 @@ static void __dwc3_set_mode(struct work_struct *work)
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struct dwc3 *dwc = work_to_dwc(work);
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unsigned long flags;
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int ret;
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u32 reg;
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pm_runtime_get_sync(dwc->dev);
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@ -169,6 +170,11 @@ static void __dwc3_set_mode(struct work_struct *work)
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otg_set_vbus(dwc->usb2_phy->otg, true);
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phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
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phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
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if (dwc->dis_split_quirk) {
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reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
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reg |= DWC3_GUCTL3_SPLITDISABLE;
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dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
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}
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}
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break;
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case DWC3_GCTL_PRTCAP_DEVICE:
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@ -1349,6 +1355,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
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dwc->dis_metastability_quirk = device_property_read_bool(dev,
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"snps,dis_metastability_quirk");
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dwc->dis_split_quirk = device_property_read_bool(dev,
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"snps,dis-split-quirk");
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dwc->lpm_nyet_threshold = lpm_nyet_threshold;
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dwc->tx_de_emphasis = tx_de_emphasis;
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@ -1886,10 +1895,26 @@ static int dwc3_resume(struct device *dev)
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return 0;
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}
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static void dwc3_complete(struct device *dev)
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{
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struct dwc3 *dwc = dev_get_drvdata(dev);
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u32 reg;
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if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
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dwc->dis_split_quirk) {
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reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
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reg |= DWC3_GUCTL3_SPLITDISABLE;
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dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
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}
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}
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#else
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#define dwc3_complete NULL
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#endif /* CONFIG_PM_SLEEP */
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static const struct dev_pm_ops dwc3_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
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.complete = dwc3_complete,
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SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
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dwc3_runtime_idle)
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};
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@ -138,6 +138,7 @@
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#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
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#define DWC3_GHWPARAMS8 0xc600
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#define DWC3_GUCTL3 0xc60c
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#define DWC3_GFLADJ 0xc630
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/* Device Registers */
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@ -380,6 +381,9 @@
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/* Global User Control Register 2 */
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#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
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/* Global User Control Register 3 */
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#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
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/* Device Configuration Register */
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#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
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#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
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@ -1053,6 +1057,7 @@ struct dwc3_scratchpad_array {
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* 2 - No de-emphasis
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* 3 - Reserved
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* @dis_metastability_quirk: set to disable metastability quirk.
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* @dis_split_quirk: set to disable split boundary.
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* @imod_interval: set the interrupt moderation interval in 250ns
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* increments or 0 to disable.
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*/
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@ -1246,6 +1251,8 @@ struct dwc3 {
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unsigned dis_metastability_quirk:1;
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unsigned dis_split_quirk:1;
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u16 imod_interval;
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};
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