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PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge
The default value of Class Code of this bridge corresponds to a Memory
controller, though. This is probably relict from the past when old
Marvell/Galileo PCI-based controllers were used as standalone PCI device
for connecting SDRAM or workaround for PCs with broken BIOS. Details are
in commit 36de23a4c5
("MIPS: Cobalt: Explain GT64111 early PCI fixup").
Change the Class Code to correspond to a PCI Bridge.
Add comment explaining this change.
Link: https://lore.kernel.org/r/20211125124605.25915-11-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This commit is contained in:
parent
df08ac0161
commit
f587775828
1 changed files with 27 additions and 1 deletions
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@ -214,7 +214,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
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static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
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{
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u32 ctrl, cmd, mask;
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u32 ctrl, cmd, dev_rev, mask;
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/* Setup PCIe controller to Root Complex mode. */
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ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
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@ -226,6 +226,32 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
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cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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mvebu_writel(port, cmd, PCIE_CMD_OFF);
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/*
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* Change Class Code of PCI Bridge device to PCI Bridge (0x6004)
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* because default value is Memory controller (0x5080).
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*
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* Note that this mvebu PCI Bridge does not have compliant Type 1
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* Configuration Space. Header Type is reported as Type 0 and it
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* has format of Type 0 config space.
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*
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* Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34)
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* have the same format in Marvell's specification as in PCIe
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* specification, but their meaning is totally different and they do
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* different things: they are aliased into internal mvebu registers
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* (e.g. PCIE_BAR_LO_OFF) and these should not be changed or
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* reconfigured by pci device drivers.
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*
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* Therefore driver uses emulation of PCI Bridge which emulates
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* access to configuration space via internal mvebu registers or
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* emulated configuration buffer. Driver access these PCI Bridge
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* directly for simplification, but these registers can be accessed
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* also via standard mvebu way for accessing PCI config space.
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*/
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dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF);
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dev_rev &= ~0xffffff00;
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dev_rev |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
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mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF);
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/* Point PCIe unit MBUS decode windows to DRAM space. */
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mvebu_pcie_setup_wins(port);
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