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drm/i915/dp: use actual link rate values in struct link_config_limits
The MST code uses actual link rates in the limits struct, while the DP code in general uses indexes to the ->common_rates[] array. Fix the confusion by using actual link rate values everywhere. This is a better abstraction than some obscure index. Rename the struct members while at it to ensure all the places are covered. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d70ab7261abacd367d3a6a47102575eb88a55cd4.1629735412.git.jani.nikula@intel.com
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c79b846f89
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3 changed files with 21 additions and 17 deletions
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@ -1044,7 +1044,8 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
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intel_dp->num_common_rates,
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intel_dp->compliance.test_link_rate);
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if (index >= 0)
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limits->min_clock = limits->max_clock = index;
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limits->min_rate = limits->max_rate =
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intel_dp->compliance.test_link_rate;
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limits->min_lane_count = limits->max_lane_count =
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intel_dp->compliance.test_lane_count;
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}
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@ -1058,8 +1059,8 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
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const struct link_config_limits *limits)
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{
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struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
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int bpp, clock, lane_count;
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int mode_rate, link_clock, link_avail;
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int bpp, i, lane_count;
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int mode_rate, link_rate, link_avail;
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for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
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int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
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@ -1067,18 +1068,22 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
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mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
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output_bpp);
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for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
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for (i = 0; i < intel_dp->num_common_rates; i++) {
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link_rate = intel_dp->common_rates[i];
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if (link_rate < limits->min_rate ||
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link_rate > limits->max_rate)
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continue;
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for (lane_count = limits->min_lane_count;
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lane_count <= limits->max_lane_count;
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lane_count <<= 1) {
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link_clock = intel_dp->common_rates[clock];
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link_avail = intel_dp_max_data_rate(link_clock,
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link_avail = intel_dp_max_data_rate(link_rate,
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lane_count);
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if (mode_rate <= link_avail) {
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pipe_config->lane_count = lane_count;
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pipe_config->pipe_bpp = bpp;
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pipe_config->port_clock = link_clock;
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pipe_config->port_clock = link_rate;
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return 0;
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}
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@ -1212,7 +1217,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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* with DSC enabled for the requested mode.
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*/
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pipe_config->pipe_bpp = pipe_bpp;
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pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
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pipe_config->port_clock = limits->max_rate;
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pipe_config->lane_count = limits->max_lane_count;
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if (intel_dp_is_edp(intel_dp)) {
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@ -1321,8 +1326,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
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/* No common link rates between source and sink */
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drm_WARN_ON(encoder->base.dev, common_len <= 0);
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limits.min_clock = 0;
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limits.max_clock = common_len - 1;
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limits.min_rate = intel_dp->common_rates[0];
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limits.max_rate = intel_dp->common_rates[common_len - 1];
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limits.min_lane_count = 1;
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limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
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@ -1340,15 +1345,14 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
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* values correspond to the native resolution of the panel.
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*/
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limits.min_lane_count = limits.max_lane_count;
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limits.min_clock = limits.max_clock;
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limits.min_rate = limits.max_rate;
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}
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intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
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drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
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"max rate %d max bpp %d pixel clock %iKHz\n",
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limits.max_lane_count,
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intel_dp->common_rates[limits.max_clock],
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limits.max_lane_count, limits.max_rate,
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limits.max_bpp, adjusted_mode->crtc_clock);
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if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
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@ -26,7 +26,7 @@ struct intel_dp;
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struct intel_encoder;
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struct link_config_limits {
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int min_clock, max_clock;
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int min_rate, max_rate;
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int min_lane_count, max_lane_count;
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int min_bpp, max_bpp;
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};
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@ -61,7 +61,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
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int bpp, slots = -EINVAL;
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crtc_state->lane_count = limits->max_lane_count;
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crtc_state->port_clock = limits->max_clock;
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crtc_state->port_clock = limits->max_rate;
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for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
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crtc_state->pipe_bpp = bpp;
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@ -131,8 +131,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
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* for MST we always configure max link bw - the spec doesn't
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* seem to suggest we should do otherwise.
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*/
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limits.min_clock =
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limits.max_clock = intel_dp_max_link_rate(intel_dp);
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limits.min_rate =
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limits.max_rate = intel_dp_max_link_rate(intel_dp);
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limits.min_lane_count =
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limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
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