mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-03 07:38:10 +00:00
Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next
- Remove clk_readl() and introduce BE versions of basic clk types
* clk-doc:
clk: Drop duplicate clk_register() documentation
clk: Document and simplify clk_core_get_rate_nolock()
clk: Remove 'flags' member of struct clk_fixed_rate
clk: nxp: Drop 'flags' on fixed_rate clk macro
clk: Document __clk_mux_determine_rate()
clk: Document CLK_MUX_READ_ONLY mux flag
clk: Document deprecated things
clk: Collapse gpio clk kerneldoc
* clk-more-critical:
clk: highbank: Convert to CLK_IS_CRITICAL
* clk-meson: (21 commits)
clk: meson: axg-audio: add g12a support
clk: meson: axg-audio: don't register inputs in the onecell data
clk: meson: axg_audio: replace prefix axg by aud
dt-bindings: clk: axg-audio: add g12a support
clk: meson: meson8b: add the video decoder clock trees
clk: meson: meson8b: add the VPU clock trees
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
clk: meson: meson8b: use a separate clock table for Meson8m2
dt-bindings: clock: meson8b: export the video decoder clocks
clk: meson-g12a: add video decoder clocks
dt-bindings: clock: meson8b: export the VPU clock
clk: meson-g12a: add PCIE PLL clocks
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
dt-bindings: clock: meson8b: drop the "ABP" clock definition
clk: meson: g12a: add cpu clocks
dt-bindings: clk: g12a-clkc: add VDEC clock IDs
dt-bindings: clock: axg-audio: unexpose controller inputs
dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
...
* clk-basic-be:
clk: core: replace clk_{readl,writel} with {readl,writel}
clk: core: remove powerpc special handling
powerpc/512x: mark clocks as big endian
clk: mux: add explicit big endian support
clk: multiplier: add explicit big endian support
clk: gate: add explicit big endian support
clk: fractional-divider: add explicit big endian support
clk: divider: add explicit big endian support
This commit is contained in:
Stephen Boyd
commit
f6111b9d79
36 changed files with 2399 additions and 685 deletions
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@ -6,7 +6,8 @@ devices.
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Required Properties:
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
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"amlogic,g12a-audio-clkc" for G12A.
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- reg : physical base address of the clock controller and length of
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memory mapped region.
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- clocks : a list of phandle + clock-specifier pairs for the clocks listed
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@ -239,6 +239,7 @@ static inline struct clk *mpc512x_clk_divider(
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const char *name, const char *parent_name, u8 clkflags,
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u32 __iomem *reg, u8 pos, u8 len, int divflags)
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{
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divflags |= CLK_DIVIDER_BIG_ENDIAN;
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return clk_register_divider(NULL, name, parent_name, clkflags,
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reg, pos, len, divflags, &clklock);
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}
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@ -250,7 +251,7 @@ static inline struct clk *mpc512x_clk_divtable(
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{
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u8 divflags;
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divflags = 0;
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divflags = CLK_DIVIDER_BIG_ENDIAN;
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return clk_register_divider_table(NULL, name, parent_name, 0,
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reg, pos, len, divflags,
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divtab, &clklock);
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@ -261,10 +262,12 @@ static inline struct clk *mpc512x_clk_gated(
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u32 __iomem *reg, u8 pos)
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{
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int clkflags;
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u8 gateflags;
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clkflags = CLK_SET_RATE_PARENT;
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gateflags = CLK_GATE_BIG_ENDIAN;
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return clk_register_gate(NULL, name, parent_name, clkflags,
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reg, pos, 0, &clklock);
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reg, pos, gateflags, &clklock);
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}
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static inline struct clk *mpc512x_clk_muxed(const char *name,
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@ -275,7 +278,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name,
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u8 muxflags;
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clkflags = CLK_SET_RATE_PARENT;
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muxflags = 0;
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muxflags = CLK_MUX_BIG_ENDIAN;
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return clk_register_mux(NULL, name,
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parent_names, parent_count, clkflags,
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reg, pos, len, muxflags, &clklock);
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@ -25,6 +25,22 @@
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* parent - fixed parent. No clk_set_parent support
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*/
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static inline u32 clk_div_readl(struct clk_divider *divider)
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{
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if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
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return ioread32be(divider->reg);
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return readl(divider->reg);
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}
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static inline void clk_div_writel(struct clk_divider *divider, u32 val)
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{
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if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
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iowrite32be(val, divider->reg);
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else
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writel(val, divider->reg);
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}
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static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
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u8 width)
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{
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@ -135,7 +151,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int val;
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val = clk_readl(divider->reg) >> divider->shift;
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val = clk_div_readl(divider) >> divider->shift;
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val &= clk_div_mask(divider->width);
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return divider_recalc_rate(hw, parent_rate, val, divider->table,
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@ -370,7 +386,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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if (divider->flags & CLK_DIVIDER_READ_ONLY) {
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u32 val;
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val = clk_readl(divider->reg) >> divider->shift;
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val = clk_div_readl(divider) >> divider->shift;
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val &= clk_div_mask(divider->width);
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return divider_ro_round_rate(hw, rate, prate, divider->table,
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@ -420,11 +436,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = clk_div_mask(divider->width) << (divider->shift + 16);
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} else {
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val = clk_readl(divider->reg);
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val = clk_div_readl(divider);
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val &= ~(clk_div_mask(divider->width) << divider->shift);
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}
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val |= (u32)value << divider->shift;
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clk_writel(val, divider->reg);
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clk_div_writel(divider, val);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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@ -13,6 +13,22 @@
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#include <linux/slab.h>
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#include <linux/rational.h>
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static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
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{
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if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
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return ioread32be(fd->reg);
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return readl(fd->reg);
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}
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static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
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{
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if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
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iowrite32be(val, fd->reg);
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else
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writel(val, fd->reg);
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}
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static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -27,7 +43,7 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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else
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__acquire(fd->lock);
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val = clk_readl(fd->reg);
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val = clk_fd_readl(fd);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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@ -115,10 +131,10 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
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else
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__acquire(fd->lock);
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val = clk_readl(fd->reg);
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val = clk_fd_readl(fd);
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val &= ~(fd->mmask | fd->nmask);
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val |= (m << fd->mshift) | (n << fd->nshift);
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clk_writel(val, fd->reg);
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clk_fd_writel(fd, val);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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@ -23,6 +23,22 @@
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* parent - fixed parent. No clk_set_parent support
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*/
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static inline u32 clk_gate_readl(struct clk_gate *gate)
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{
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if (gate->flags & CLK_GATE_BIG_ENDIAN)
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return ioread32be(gate->reg);
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return readl(gate->reg);
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}
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static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
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{
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if (gate->flags & CLK_GATE_BIG_ENDIAN)
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iowrite32be(val, gate->reg);
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else
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writel(val, gate->reg);
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}
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/*
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* It works on following logic:
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*
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@ -55,7 +71,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
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if (set)
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reg |= BIT(gate->bit_idx);
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} else {
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reg = clk_readl(gate->reg);
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reg = clk_gate_readl(gate);
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if (set)
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reg |= BIT(gate->bit_idx);
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@ -63,7 +79,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
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reg &= ~BIT(gate->bit_idx);
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}
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clk_writel(reg, gate->reg);
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clk_gate_writel(gate, reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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@ -88,7 +104,7 @@ int clk_gate_is_enabled(struct clk_hw *hw)
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u32 reg;
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struct clk_gate *gate = to_clk_gate(hw);
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reg = clk_readl(gate->reg);
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reg = clk_gate_readl(gate);
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/* if a set bit disables this clk, flip it before masking */
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if (gate->flags & CLK_GATE_SET_TO_DISABLE)
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@ -17,7 +17,6 @@
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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@ -272,7 +271,7 @@ static const struct clk_ops periclk_ops = {
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.set_rate = clk_periclk_set_rate,
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};
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static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
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static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags)
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{
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u32 reg;
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struct hb_clk *hb_clk;
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@ -284,11 +283,11 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk
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rc = of_property_read_u32(node, "reg", ®);
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if (WARN_ON(rc))
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return NULL;
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return;
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hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
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if (WARN_ON(!hb_clk))
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return NULL;
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return;
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/* Map system registers */
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srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
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@ -301,7 +300,7 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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init.flags = clkflags;
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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@ -311,33 +310,31 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk
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rc = clk_hw_register(NULL, &hb_clk->hw);
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if (WARN_ON(rc)) {
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kfree(hb_clk);
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return NULL;
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return;
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}
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rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
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return hb_clk->hw.clk;
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of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
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}
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static void __init hb_pll_init(struct device_node *node)
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{
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hb_clk_init(node, &clk_pll_ops);
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hb_clk_init(node, &clk_pll_ops, 0);
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}
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CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
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static void __init hb_a9periph_init(struct device_node *node)
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{
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hb_clk_init(node, &a9periphclk_ops);
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hb_clk_init(node, &a9periphclk_ops, 0);
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}
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CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
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static void __init hb_a9bus_init(struct device_node *node)
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{
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struct clk *clk = hb_clk_init(node, &a9bclk_ops);
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clk_prepare_enable(clk);
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hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL);
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}
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CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
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static void __init hb_emmc_init(struct device_node *node)
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{
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hb_clk_init(node, &periclk_ops);
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hb_clk_init(node, &periclk_ops, 0);
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}
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CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
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@ -11,6 +11,22 @@
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#include <linux/of.h>
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#include <linux/slab.h>
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static inline u32 clk_mult_readl(struct clk_multiplier *mult)
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{
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if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
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return ioread32be(mult->reg);
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return readl(mult->reg);
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}
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static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val)
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{
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if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
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iowrite32be(val, mult->reg);
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else
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writel(val, mult->reg);
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}
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static unsigned long __get_mult(struct clk_multiplier *mult,
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unsigned long rate,
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unsigned long parent_rate)
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|
|
@ -27,7 +43,7 @@ static unsigned long clk_multiplier_recalc_rate(struct clk_hw *hw,
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struct clk_multiplier *mult = to_clk_multiplier(hw);
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unsigned long val;
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val = clk_readl(mult->reg) >> mult->shift;
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val = clk_mult_readl(mult) >> mult->shift;
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val &= GENMASK(mult->width - 1, 0);
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|
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if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)
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|
|
@ -118,10 +134,10 @@ static int clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate,
|
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else
|
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__acquire(mult->lock);
|
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|
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val = clk_readl(mult->reg);
|
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val = clk_mult_readl(mult);
|
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val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift);
|
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val |= factor << mult->shift;
|
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clk_writel(val, mult->reg);
|
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clk_mult_writel(mult, val);
|
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|
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if (mult->lock)
|
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spin_unlock_irqrestore(mult->lock, flags);
|
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|
|
|
|||
|
|
@ -23,6 +23,22 @@
|
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* parent - parent is adjustable through clk_set_parent
|
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*/
|
||||
|
||||
static inline u32 clk_mux_readl(struct clk_mux *mux)
|
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{
|
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if (mux->flags & CLK_MUX_BIG_ENDIAN)
|
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return ioread32be(mux->reg);
|
||||
|
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return readl(mux->reg);
|
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}
|
||||
|
||||
static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
|
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{
|
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if (mux->flags & CLK_MUX_BIG_ENDIAN)
|
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iowrite32be(val, mux->reg);
|
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else
|
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writel(val, mux->reg);
|
||||
}
|
||||
|
||||
int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
|
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unsigned int val)
|
||||
{
|
||||
|
|
@ -73,7 +89,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
|
|||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
u32 val;
|
||||
|
||||
val = clk_readl(mux->reg) >> mux->shift;
|
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val = clk_mux_readl(mux) >> mux->shift;
|
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val &= mux->mask;
|
||||
|
||||
return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
|
||||
|
|
@ -94,12 +110,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
if (mux->flags & CLK_MUX_HIWORD_MASK) {
|
||||
reg = mux->mask << (mux->shift + 16);
|
||||
} else {
|
||||
reg = clk_readl(mux->reg);
|
||||
reg = clk_mux_readl(mux);
|
||||
reg &= ~(mux->mask << mux->shift);
|
||||
}
|
||||
val = val << mux->shift;
|
||||
reg |= val;
|
||||
clk_writel(reg, mux->reg);
|
||||
clk_mux_writel(mux, reg);
|
||||
|
||||
if (mux->lock)
|
||||
spin_unlock_irqrestore(mux->lock, flags);
|
||||
|
|
|
|||
|
|
@ -262,7 +262,7 @@ static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw,
|
|||
else
|
||||
__acquire(fd->lock);
|
||||
|
||||
val = clk_readl(fd->reg);
|
||||
val = readl(fd->reg);
|
||||
|
||||
if (fd->lock)
|
||||
spin_unlock_irqrestore(fd->lock, flags);
|
||||
|
|
@ -333,10 +333,10 @@ static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
else
|
||||
__acquire(fd->lock);
|
||||
|
||||
val = clk_readl(fd->reg);
|
||||
val = readl(fd->reg);
|
||||
val &= ~fd->mask;
|
||||
val |= (scale << fd->shift);
|
||||
clk_writel(val, fd->reg);
|
||||
writel(val, fd->reg);
|
||||
|
||||
if (fd->lock)
|
||||
spin_unlock_irqrestore(fd->lock, flags);
|
||||
|
|
|
|||
|
|
@ -347,23 +347,18 @@ unsigned int __clk_get_enable_count(struct clk *clk)
|
|||
|
||||
static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
|
||||
{
|
||||
unsigned long ret;
|
||||
if (!core)
|
||||
return 0;
|
||||
|
||||
if (!core) {
|
||||
ret = 0;
|
||||
goto out;
|
||||
}
|
||||
if (!core->num_parents || core->parent)
|
||||
return core->rate;
|
||||
|
||||
ret = core->rate;
|
||||
|
||||
if (!core->num_parents)
|
||||
goto out;
|
||||
|
||||
if (!core->parent)
|
||||
ret = 0;
|
||||
|
||||
out:
|
||||
return ret;
|
||||
/*
|
||||
* Clk must have a parent because num_parents > 0 but the parent isn't
|
||||
* known yet. Best to return 0 as the rate of this clk until we can
|
||||
* properly recalc the rate based on the parent's rate.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long clk_hw_get_rate(const struct clk_hw *hw)
|
||||
|
|
@ -524,9 +519,15 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
|
|||
EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
|
||||
|
||||
/*
|
||||
* __clk_mux_determine_rate - clk_ops::determine_rate implementation for a mux type clk
|
||||
* @hw: mux type clk to determine rate on
|
||||
* @req: rate request, also used to return preferred parent and frequencies
|
||||
*
|
||||
* Helper for finding best parent to provide a given frequency. This can be used
|
||||
* directly as a determine_rate callback (e.g. for a mux), or from a more
|
||||
* complex clock that may combine a mux with other operations.
|
||||
*
|
||||
* Returns: 0 on success, -EERROR value on error
|
||||
*/
|
||||
int __clk_mux_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
|
|
@ -3318,8 +3319,10 @@ struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw,
|
|||
* @dev: device that is registering this clock
|
||||
* @hw: link to hardware-specific clock data
|
||||
*
|
||||
* clk_register is the primary interface for populating the clock tree with new
|
||||
* clock nodes. It returns a pointer to the newly allocated struct clk which
|
||||
* clk_register is the *deprecated* interface for populating the clock tree with
|
||||
* new clock nodes. Use clk_hw_register() instead.
|
||||
*
|
||||
* Returns: a pointer to the newly allocated struct clk which
|
||||
* cannot be dereferenced by driver code but may be used in conjunction with the
|
||||
* rest of the clock API. In the event of an error clk_register will return an
|
||||
* error code; drivers must test for an error code after calling clk_register.
|
||||
|
|
@ -3575,9 +3578,10 @@ static void devm_clk_hw_release(struct device *dev, void *res)
|
|||
* @dev: device that is registering this clock
|
||||
* @hw: link to hardware-specific clock data
|
||||
*
|
||||
* Managed clk_register(). Clocks returned from this function are
|
||||
* automatically clk_unregister()ed on driver detach. See clk_register() for
|
||||
* more information.
|
||||
* Managed clk_register(). This function is *deprecated*, use devm_clk_hw_register() instead.
|
||||
*
|
||||
* Clocks returned from this function are automatically clk_unregister()ed on
|
||||
* driver detach. See clk_register() for more information.
|
||||
*/
|
||||
struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
|
||||
{
|
||||
|
|
@ -3895,6 +3899,8 @@ EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get);
|
|||
* @np: Device node pointer associated with clock provider
|
||||
* @clk_src_get: callback for decoding clock
|
||||
* @data: context pointer for @clk_src_get callback.
|
||||
*
|
||||
* This function is *deprecated*. Use of_clk_add_hw_provider() instead.
|
||||
*/
|
||||
int of_clk_add_provider(struct device_node *np,
|
||||
struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
|
||||
|
|
|
|||
|
|
@ -75,10 +75,10 @@ static int hisi_clk_set_phase(struct clk_hw *hw, int degrees)
|
|||
|
||||
spin_lock_irqsave(phase->lock, flags);
|
||||
|
||||
val = clk_readl(phase->reg);
|
||||
val = readl(phase->reg);
|
||||
val &= ~phase->mask;
|
||||
val |= regval << phase->shift;
|
||||
clk_writel(val, phase->reg);
|
||||
writel(val, phase->reg);
|
||||
|
||||
spin_unlock_irqrestore(phase->lock, flags);
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ static unsigned long clk_divider_gate_recalc_rate_ro(struct clk_hw *hw,
|
|||
struct clk_divider *div = to_clk_divider(hw);
|
||||
unsigned int val;
|
||||
|
||||
val = clk_readl(div->reg) >> div->shift;
|
||||
val = readl(div->reg) >> div->shift;
|
||||
val &= clk_div_mask(div->width);
|
||||
if (!val)
|
||||
return 0;
|
||||
|
|
@ -51,7 +51,7 @@ static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
|
|||
if (!clk_hw_is_enabled(hw)) {
|
||||
val = div_gate->cached_val;
|
||||
} else {
|
||||
val = clk_readl(div->reg) >> div->shift;
|
||||
val = readl(div->reg) >> div->shift;
|
||||
val &= clk_div_mask(div->width);
|
||||
}
|
||||
|
||||
|
|
@ -87,10 +87,10 @@ static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
spin_lock_irqsave(div->lock, flags);
|
||||
|
||||
if (clk_hw_is_enabled(hw)) {
|
||||
val = clk_readl(div->reg);
|
||||
val = readl(div->reg);
|
||||
val &= ~(clk_div_mask(div->width) << div->shift);
|
||||
val |= (u32)value << div->shift;
|
||||
clk_writel(val, div->reg);
|
||||
writel(val, div->reg);
|
||||
} else {
|
||||
div_gate->cached_val = value;
|
||||
}
|
||||
|
|
@ -114,9 +114,9 @@ static int clk_divider_enable(struct clk_hw *hw)
|
|||
|
||||
spin_lock_irqsave(div->lock, flags);
|
||||
/* restore div val */
|
||||
val = clk_readl(div->reg);
|
||||
val = readl(div->reg);
|
||||
val |= div_gate->cached_val << div->shift;
|
||||
clk_writel(val, div->reg);
|
||||
writel(val, div->reg);
|
||||
|
||||
spin_unlock_irqrestore(div->lock, flags);
|
||||
|
||||
|
|
@ -133,10 +133,10 @@ static void clk_divider_disable(struct clk_hw *hw)
|
|||
spin_lock_irqsave(div->lock, flags);
|
||||
|
||||
/* store the current div val */
|
||||
val = clk_readl(div->reg) >> div->shift;
|
||||
val = readl(div->reg) >> div->shift;
|
||||
val &= clk_div_mask(div->width);
|
||||
div_gate->cached_val = val;
|
||||
clk_writel(0, div->reg);
|
||||
writel(0, div->reg);
|
||||
|
||||
spin_unlock_irqrestore(div->lock, flags);
|
||||
}
|
||||
|
|
@ -146,7 +146,7 @@ static int clk_divider_is_enabled(struct clk_hw *hw)
|
|||
struct clk_divider *div = to_clk_divider(hw);
|
||||
u32 val;
|
||||
|
||||
val = clk_readl(div->reg) >> div->shift;
|
||||
val = readl(div->reg) >> div->shift;
|
||||
val &= clk_div_mask(div->width);
|
||||
|
||||
return val ? 1 : 0;
|
||||
|
|
@ -206,7 +206,7 @@ struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name,
|
|||
div_gate->divider.hw.init = &init;
|
||||
div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;
|
||||
/* cache gate status */
|
||||
val = clk_readl(reg) >> shift;
|
||||
val = readl(reg) >> shift;
|
||||
val &= clk_div_mask(width);
|
||||
div_gate->cached_val = val;
|
||||
|
||||
|
|
|
|||
|
|
@ -348,7 +348,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
|
|||
|
||||
temp64 = parent_rate;
|
||||
|
||||
val = clk_readl(pll->base + PLL_CFG0);
|
||||
val = readl(pll->base + PLL_CFG0);
|
||||
if (val & SSCG_PLL_BYPASS2_MASK) {
|
||||
temp64 = parent_rate;
|
||||
} else if (val & SSCG_PLL_BYPASS1_MASK) {
|
||||
|
|
@ -371,10 +371,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
u32 val;
|
||||
|
||||
/* set bypass here too since the parent might be the same */
|
||||
val = clk_readl(pll->base + PLL_CFG0);
|
||||
val = readl(pll->base + PLL_CFG0);
|
||||
val &= ~SSCG_PLL_BYPASS_MASK;
|
||||
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
|
||||
clk_writel(val, pll->base + PLL_CFG0);
|
||||
writel(val, pll->base + PLL_CFG0);
|
||||
|
||||
val = readl_relaxed(pll->base + PLL_CFG2);
|
||||
val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
|
||||
|
|
@ -395,7 +395,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw)
|
|||
u32 val;
|
||||
u8 ret = pll->parent;
|
||||
|
||||
val = clk_readl(pll->base + PLL_CFG0);
|
||||
val = readl(pll->base + PLL_CFG0);
|
||||
if (val & SSCG_PLL_BYPASS2_MASK)
|
||||
ret = pll->bypass2;
|
||||
else if (val & SSCG_PLL_BYPASS1_MASK)
|
||||
|
|
@ -408,10 +408,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index)
|
|||
struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
|
||||
u32 val;
|
||||
|
||||
val = clk_readl(pll->base + PLL_CFG0);
|
||||
val = readl(pll->base + PLL_CFG0);
|
||||
val &= ~SSCG_PLL_BYPASS_MASK;
|
||||
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
|
||||
clk_writel(val, pll->base + PLL_CFG0);
|
||||
writel(val, pll->base + PLL_CFG0);
|
||||
|
||||
return clk_sccg_pll_wait_lock(pll);
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -20,6 +20,8 @@
|
|||
#define AUDIO_MCLK_D_CTRL 0x010
|
||||
#define AUDIO_MCLK_E_CTRL 0x014
|
||||
#define AUDIO_MCLK_F_CTRL 0x018
|
||||
#define AUDIO_MST_PAD_CTRL0 0x01c
|
||||
#define AUDIO_MST_PAD_CTRL1 0x020
|
||||
#define AUDIO_MST_A_SCLK_CTRL0 0x040
|
||||
#define AUDIO_MST_A_SCLK_CTRL1 0x044
|
||||
#define AUDIO_MST_B_SCLK_CTRL0 0x048
|
||||
|
|
@ -45,21 +47,13 @@
|
|||
#define AUDIO_CLK_LOCKER_CTRL 0x0A8
|
||||
#define AUDIO_CLK_PDMIN_CTRL0 0x0AC
|
||||
#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
|
||||
#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
*/
|
||||
|
||||
#define AUD_CLKID_PCLK 0
|
||||
#define AUD_CLKID_MST0 1
|
||||
#define AUD_CLKID_MST1 2
|
||||
#define AUD_CLKID_MST2 3
|
||||
#define AUD_CLKID_MST3 4
|
||||
#define AUD_CLKID_MST4 5
|
||||
#define AUD_CLKID_MST5 6
|
||||
#define AUD_CLKID_MST6 7
|
||||
#define AUD_CLKID_MST7 8
|
||||
#define AUD_CLKID_MST_A_MCLK_SEL 59
|
||||
#define AUD_CLKID_MST_B_MCLK_SEL 60
|
||||
#define AUD_CLKID_MST_C_MCLK_SEL 61
|
||||
|
|
@ -118,10 +112,12 @@
|
|||
#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
|
||||
|
||||
/* include the CLKIDs which are part of the DT bindings */
|
||||
#include <dt-bindings/clock/axg-audio-clkc.h>
|
||||
|
||||
#define NR_CLKS 151
|
||||
#define NR_CLKS 163
|
||||
|
||||
#endif /*__AXG_AUDIO_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -303,6 +303,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
meson_clk_pll_init(hw);
|
||||
|
||||
if (meson_clk_pll_wait_lock(hw))
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_clk_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
|
|
@ -387,6 +397,22 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* The Meson G12A PCIE PLL is fined tuned to deliver a very precise
|
||||
* 100MHz reference clock for the PCIe Analog PHY, and thus requires
|
||||
* a strict register sequence to enable the PLL.
|
||||
* To simplify, re-use the _init() op to enable the PLL and keep
|
||||
* the other ops except set_rate since the rate is fixed.
|
||||
*/
|
||||
const struct clk_ops meson_clk_pcie_pll_ops = {
|
||||
.recalc_rate = meson_clk_pll_recalc_rate,
|
||||
.round_rate = meson_clk_pll_round_rate,
|
||||
.is_enabled = meson_clk_pll_is_enabled,
|
||||
.enable = meson_clk_pcie_pll_enable,
|
||||
.disable = meson_clk_pll_disable
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
|
||||
|
||||
const struct clk_ops meson_clk_pll_ops = {
|
||||
.init = meson_clk_pll_init,
|
||||
.recalc_rate = meson_clk_pll_recalc_rate,
|
||||
|
|
|
|||
|
|
@ -45,5 +45,6 @@ struct meson_clk_pll_data {
|
|||
|
||||
extern const struct clk_ops meson_clk_pll_ro_ops;
|
||||
extern const struct clk_ops meson_clk_pll_ops;
|
||||
extern const struct clk_ops meson_clk_pcie_pll_ops;
|
||||
|
||||
#endif /* __MESON_CLK_PLL_H */
|
||||
|
|
|
|||
|
|
@ -16,9 +16,7 @@
|
|||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_AO_SAR_ADC_SEL 16
|
||||
#define CLKID_AO_SAR_ADC_DIV 17
|
||||
#define CLKID_AO_CTS_OSCIN 19
|
||||
#define CLKID_AO_32K_PRE 20
|
||||
#define CLKID_AO_32K_DIV 21
|
||||
#define CLKID_AO_32K_SEL 22
|
||||
|
|
|
|||
|
|
@ -150,6 +150,318 @@ static struct clk_regmap g12a_sys_pll = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_sys_pll_div16_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.bit_idx = 24,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sys_pll_div16_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "sys_pll" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is used to debug the sys_pll range
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12a_sys_pll_div16 = {
|
||||
.mult = 1,
|
||||
.div = 16,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sys_pll_div16",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "sys_pll_div16_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "premux0" */
|
||||
static struct clk_regmap g12a_cpu_clk_premux0 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x3,
|
||||
.shift = 0,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn0_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ IN_PREFIX "xtal",
|
||||
"fclk_div2",
|
||||
"fclk_div3" },
|
||||
.num_parents = 3,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "mux0_divn_tcnt" */
|
||||
static struct clk_regmap g12a_cpu_clk_mux0_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.shift = 4,
|
||||
.width = 6,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn0_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "postmux0" */
|
||||
static struct clk_regmap g12a_cpu_clk_postmux0 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 2,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn0",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
|
||||
"cpu_clk_dyn0_div" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "premux1" */
|
||||
static struct clk_regmap g12a_cpu_clk_premux1 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x3,
|
||||
.shift = 16,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn1_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ IN_PREFIX "xtal",
|
||||
"fclk_div2",
|
||||
"fclk_div3" },
|
||||
.num_parents = 3,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "Mux1_divn_tcnt" */
|
||||
static struct clk_regmap g12a_cpu_clk_mux1_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.shift = 20,
|
||||
.width = 6,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn1_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "postmux1" */
|
||||
static struct clk_regmap g12a_cpu_clk_postmux1 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 18,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn1",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
|
||||
"cpu_clk_dyn1_div" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "Final_dyn_mux_sel" */
|
||||
static struct clk_regmap g12a_cpu_clk_dyn = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 10,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_dyn0",
|
||||
"cpu_clk_dyn1" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "Final_mux_sel" */
|
||||
static struct clk_regmap g12a_cpu_clk = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 11,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_dyn",
|
||||
"sys_pll" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_div16_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.bit_idx = 1,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpu_clk_div16_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is used to debug the cpu_clk range
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12a_cpu_clk_div16 = {
|
||||
.mult = 1,
|
||||
.div = 16,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_div16",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_div16_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_apb_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.shift = 3,
|
||||
.width = 3,
|
||||
.flags = CLK_DIVIDER_POWER_OF_TWO,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_apb_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_apb = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.bit_idx = 1,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpu_clk_apb",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_apb_div" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is set by the ROM monitor code,
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_atb_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.shift = 6,
|
||||
.width = 3,
|
||||
.flags = CLK_DIVIDER_POWER_OF_TWO,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_atb_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_atb = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.bit_idx = 17,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpu_clk_atb",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_atb_div" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is set by the ROM monitor code,
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_axi_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.shift = 9,
|
||||
.width = 3,
|
||||
.flags = CLK_DIVIDER_POWER_OF_TWO,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_axi_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_axi = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.bit_idx = 18,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpu_clk_axi",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_axi_div" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is set by the ROM monitor code,
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_trace_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.shift = 20,
|
||||
.width = 3,
|
||||
.flags = CLK_DIVIDER_POWER_OF_TWO,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_trace_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_trace = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.bit_idx = 23,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpu_clk_trace",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_trace_div" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is set by the ROM monitor code,
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pll_mult_range g12a_gp0_pll_mult_range = {
|
||||
.min = 55,
|
||||
.max = 255,
|
||||
|
|
@ -302,6 +614,118 @@ static struct clk_regmap g12a_hifi_pll = {
|
|||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* The Meson G12A PCIE PLL is fined tuned to deliver a very precise
|
||||
* 100MHz reference clock for the PCIe Analog PHY, and thus requires
|
||||
* a strict register sequence to enable the PLL.
|
||||
*/
|
||||
static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
|
||||
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
|
||||
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
|
||||
};
|
||||
|
||||
/* Keep a single entry table for recalc/round_rate() ops */
|
||||
static const struct pll_params_table g12a_pcie_pll_table[] = {
|
||||
PLL_PARAMS(150, 1),
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_pcie_pll_dco = {
|
||||
.data = &(struct meson_clk_pll_data){
|
||||
.en = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 28,
|
||||
.width = 1,
|
||||
},
|
||||
.m = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 10,
|
||||
.width = 5,
|
||||
},
|
||||
.frac = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL1,
|
||||
.shift = 0,
|
||||
.width = 12,
|
||||
},
|
||||
.l = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 31,
|
||||
.width = 1,
|
||||
},
|
||||
.rst = {
|
||||
.reg_off = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 29,
|
||||
.width = 1,
|
||||
},
|
||||
.table = g12a_pcie_pll_table,
|
||||
.init_regs = g12a_pcie_pll_init_regs,
|
||||
.init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "pcie_pll_dco",
|
||||
.ops = &meson_clk_pcie_pll_ops,
|
||||
.parent_names = (const char *[]){ IN_PREFIX "xtal" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "pcie_pll_dco_div2",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "pcie_pll_dco" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_pcie_pll_od = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_PCIE_PLL_CNTL0,
|
||||
.shift = 16,
|
||||
.width = 5,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST |
|
||||
CLK_DIVIDER_ONE_BASED |
|
||||
CLK_DIVIDER_ALLOW_ZERO,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "pcie_pll_od",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "pcie_pll_dco_div2" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12a_pcie_pll = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "pcie_pll_pll",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "pcie_pll_od" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_hdmi_pll_dco = {
|
||||
.data = &(struct meson_clk_pll_data){
|
||||
.en = {
|
||||
|
|
@ -1071,6 +1495,151 @@ static struct clk_regmap g12a_vpu = {
|
|||
},
|
||||
};
|
||||
|
||||
/* VDEC clocks */
|
||||
|
||||
static const char * const g12a_vdec_parent_names[] = {
|
||||
"fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
|
||||
"hifi_pll", "gp0_pll",
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_1_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_1_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = g12a_vdec_parent_names,
|
||||
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_1_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_1_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vdec_1_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_1 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vdec_1",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vdec_1_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_hevcf_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 9,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hevcf_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = g12a_vdec_parent_names,
|
||||
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_hevcf_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hevcf_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vdec_hevcf_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_hevcf = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vdec_hevcf",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vdec_hevcf_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_hevc_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.mask = 0x7,
|
||||
.shift = 25,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hevc_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = g12a_vdec_parent_names,
|
||||
.num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_hevc_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hevc_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vdec_hevc_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_vdec_hevc = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.bit_idx = 24,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vdec_hevc",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vdec_hevc_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/* VAPB Clock */
|
||||
|
||||
static const char * const g12a_vapb_parent_names[] = {
|
||||
|
|
@ -2167,6 +2736,39 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
|
|||
[CLKID_MALI] = &g12a_mali.hw,
|
||||
[CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
|
||||
[CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
|
||||
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
|
||||
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
|
||||
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
|
||||
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
|
||||
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
|
||||
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
|
||||
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
|
||||
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
|
||||
[CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
|
||||
[CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
|
||||
[CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
|
||||
[CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
|
||||
[CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
|
||||
[CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
|
||||
[CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
|
||||
[CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
|
||||
[CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
|
||||
[CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
|
||||
[CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
|
||||
[CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
|
||||
[CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
|
||||
[CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
|
||||
[CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
|
||||
[CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
|
||||
[CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
|
||||
[CLKID_VDEC_1] = &g12a_vdec_1.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
|
||||
[CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
|
||||
[CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
|
||||
[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
|
|
@ -2335,6 +2937,35 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
|
|||
&g12a_mali_1,
|
||||
&g12a_mali,
|
||||
&g12a_mpll_50m,
|
||||
&g12a_sys_pll_div16_en,
|
||||
&g12a_cpu_clk_premux0,
|
||||
&g12a_cpu_clk_mux0_div,
|
||||
&g12a_cpu_clk_postmux0,
|
||||
&g12a_cpu_clk_premux1,
|
||||
&g12a_cpu_clk_mux1_div,
|
||||
&g12a_cpu_clk_postmux1,
|
||||
&g12a_cpu_clk_dyn,
|
||||
&g12a_cpu_clk,
|
||||
&g12a_cpu_clk_div16_en,
|
||||
&g12a_cpu_clk_apb_div,
|
||||
&g12a_cpu_clk_apb,
|
||||
&g12a_cpu_clk_atb_div,
|
||||
&g12a_cpu_clk_atb,
|
||||
&g12a_cpu_clk_axi_div,
|
||||
&g12a_cpu_clk_axi,
|
||||
&g12a_cpu_clk_trace_div,
|
||||
&g12a_cpu_clk_trace,
|
||||
&g12a_pcie_pll_od,
|
||||
&g12a_pcie_pll_dco,
|
||||
&g12a_vdec_1_sel,
|
||||
&g12a_vdec_1_div,
|
||||
&g12a_vdec_1,
|
||||
&g12a_vdec_hevc_sel,
|
||||
&g12a_vdec_hevc_div,
|
||||
&g12a_vdec_hevc,
|
||||
&g12a_vdec_hevcf_sel,
|
||||
&g12a_vdec_hevcf_div,
|
||||
&g12a_vdec_hevcf,
|
||||
};
|
||||
|
||||
static const struct meson_eeclkc_data g12a_clkc_data = {
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@
|
|||
#define HHI_GCLK_MPEG2 0x148
|
||||
#define HHI_GCLK_OTHER 0x150
|
||||
#define HHI_GCLK_OTHER2 0x154
|
||||
#define HHI_SYS_CPU_CLK_CNTL1 0x15c
|
||||
#define HHI_VID_CLK_DIV 0x164
|
||||
#define HHI_MPEG_CLK_CNTL 0x174
|
||||
#define HHI_AUD_CLK_CNTL 0x178
|
||||
|
|
@ -166,8 +167,36 @@
|
|||
#define CLKID_MALI_0_DIV 170
|
||||
#define CLKID_MALI_1_DIV 173
|
||||
#define CLKID_MPLL_5OM_DIV 176
|
||||
#define CLKID_SYS_PLL_DIV16_EN 178
|
||||
#define CLKID_SYS_PLL_DIV16 179
|
||||
#define CLKID_CPU_CLK_DYN0_SEL 180
|
||||
#define CLKID_CPU_CLK_DYN0_DIV 181
|
||||
#define CLKID_CPU_CLK_DYN0 182
|
||||
#define CLKID_CPU_CLK_DYN1_SEL 183
|
||||
#define CLKID_CPU_CLK_DYN1_DIV 184
|
||||
#define CLKID_CPU_CLK_DYN1 185
|
||||
#define CLKID_CPU_CLK_DYN 186
|
||||
#define CLKID_CPU_CLK_DIV16_EN 188
|
||||
#define CLKID_CPU_CLK_DIV16 189
|
||||
#define CLKID_CPU_CLK_APB_DIV 190
|
||||
#define CLKID_CPU_CLK_APB 191
|
||||
#define CLKID_CPU_CLK_ATB_DIV 192
|
||||
#define CLKID_CPU_CLK_ATB 193
|
||||
#define CLKID_CPU_CLK_AXI_DIV 194
|
||||
#define CLKID_CPU_CLK_AXI 195
|
||||
#define CLKID_CPU_CLK_TRACE_DIV 196
|
||||
#define CLKID_CPU_CLK_TRACE 197
|
||||
#define CLKID_PCIE_PLL_DCO 198
|
||||
#define CLKID_PCIE_PLL_DCO_DIV2 199
|
||||
#define CLKID_PCIE_PLL_OD 200
|
||||
#define CLKID_VDEC_1_SEL 202
|
||||
#define CLKID_VDEC_1_DIV 203
|
||||
#define CLKID_VDEC_HEVC_SEL 205
|
||||
#define CLKID_VDEC_HEVC_DIV 206
|
||||
#define CLKID_VDEC_HEVCF_SEL 208
|
||||
#define CLKID_VDEC_HEVCF_DIV 209
|
||||
|
||||
#define NR_CLKS 178
|
||||
#define NR_CLKS 211
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/g12a-clkc.h>
|
||||
|
|
|
|||
|
|
@ -1703,6 +1703,456 @@ static struct clk_regmap meson8b_mali = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
|
||||
PLL_PARAMS(182, 3),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8m2_gp_pll_dco = {
|
||||
.data = &(struct meson_clk_pll_data){
|
||||
.en = {
|
||||
.reg_off = HHI_GP_PLL_CNTL,
|
||||
.shift = 30,
|
||||
.width = 1,
|
||||
},
|
||||
.m = {
|
||||
.reg_off = HHI_GP_PLL_CNTL,
|
||||
.shift = 0,
|
||||
.width = 9,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_GP_PLL_CNTL,
|
||||
.shift = 9,
|
||||
.width = 5,
|
||||
},
|
||||
.l = {
|
||||
.reg_off = HHI_GP_PLL_CNTL,
|
||||
.shift = 31,
|
||||
.width = 1,
|
||||
},
|
||||
.rst = {
|
||||
.reg_off = HHI_GP_PLL_CNTL,
|
||||
.shift = 29,
|
||||
.width = 1,
|
||||
},
|
||||
.table = meson8m2_gp_pll_params_table,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gp_pll_dco",
|
||||
.ops = &meson_clk_pll_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8m2_gp_pll = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_GP_PLL_CNTL,
|
||||
.shift = 16,
|
||||
.width = 2,
|
||||
.flags = CLK_DIVIDER_POWER_OF_TWO,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gp_pll",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "gp_pll_dco" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const mmeson8b_vpu_0_1_parent_names[] = {
|
||||
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
|
||||
};
|
||||
|
||||
static const char * const mmeson8m2_vpu_0_1_parent_names[] = {
|
||||
"fclk_div4", "fclk_div3", "fclk_div5", "gp_pll"
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vpu_0_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_0_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = mmeson8b_vpu_0_1_parent_names,
|
||||
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8m2_vpu_0_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_0_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = mmeson8m2_vpu_0_1_parent_names,
|
||||
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vpu_0_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_0_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vpu_0_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vpu_0 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vpu_0",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vpu_0_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vpu_1_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 25,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_1_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = mmeson8b_vpu_0_1_parent_names,
|
||||
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8m2_vpu_1_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 25,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_1_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = mmeson8m2_vpu_0_1_parent_names,
|
||||
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vpu_1_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_1_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vpu_1_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vpu_1 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.bit_idx = 24,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vpu_1",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vpu_1_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vpu = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
.mask = 1,
|
||||
.shift = 31,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = (const char *[]){ "vpu_0", "vpu_1" },
|
||||
.num_parents = 2,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const meson8b_vdec_parent_names[] = {
|
||||
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1"
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_1_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_1_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = meson8b_vdec_parent_names,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_1_1_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_1_1_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vdec_1_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_1_1 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vdec_1_1",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vdec_1_1_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_1_2_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VDEC3_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_1_2_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vdec_1_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_1_2 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VDEC3_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vdec_1_2",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vdec_1_2_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_1 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC3_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 15,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_1",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" },
|
||||
.num_parents = 2,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_hcodec_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 25,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hcodec_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = meson8b_vdec_parent_names,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_hcodec_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hcodec_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vdec_hcodec_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_hcodec = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VDEC_CLK_CNTL,
|
||||
.bit_idx = 24,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vdec_hcodec",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vdec_hcodec_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_2_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_2_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = meson8b_vdec_parent_names,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_2_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 7,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_2_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vdec_2_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_2 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vdec_2",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vdec_2_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_hevc_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 25,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hevc_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = meson8b_vdec_parent_names,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_hevc_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 7,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hevc_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "vdec_hevc_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_hevc_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.bit_idx = 24,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "vdec_hevc_en",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "vdec_hevc_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_vdec_hevc = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VDEC2_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 31,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vdec_hevc",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/* TODO: The second parent is currently unknown */
|
||||
.parent_names = (const char *[]){ "vdec_hevc_en" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
|
||||
static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
|
||||
|
|
@ -1966,6 +2416,22 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
|||
[CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
|
||||
[CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
|
||||
[CLKID_MALI] = &meson8b_mali_0.hw,
|
||||
[CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
|
||||
[CLKID_VPU] = &meson8b_vpu_0.hw,
|
||||
[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
|
||||
[CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
|
||||
[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
|
||||
[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
|
||||
[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
|
||||
[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
|
||||
[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
|
||||
[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
|
||||
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
|
||||
[CLK_NR_CLKS] = NULL,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
|
|
@ -2152,6 +2618,240 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
|||
[CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &meson8b_mali_1.hw,
|
||||
[CLKID_MALI] = &meson8b_mali.hw,
|
||||
[CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
|
||||
[CLKID_VPU_0] = &meson8b_vpu_0.hw,
|
||||
[CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
|
||||
[CLKID_VPU_1] = &meson8b_vpu_1.hw,
|
||||
[CLKID_VPU] = &meson8b_vpu.hw,
|
||||
[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
|
||||
[CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
|
||||
[CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
|
||||
[CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
|
||||
[CLKID_VDEC_1] = &meson8b_vdec_1.hw,
|
||||
[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
|
||||
[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
|
||||
[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
|
||||
[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
|
||||
[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
|
||||
[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
|
||||
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
|
||||
[CLK_NR_CLKS] = NULL,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_XTAL] = &meson8b_xtal.hw,
|
||||
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
||||
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
||||
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
|
||||
[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
|
||||
[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &meson8b_clk81.hw,
|
||||
[CLKID_DDR] = &meson8b_ddr.hw,
|
||||
[CLKID_DOS] = &meson8b_dos.hw,
|
||||
[CLKID_ISA] = &meson8b_isa.hw,
|
||||
[CLKID_PL301] = &meson8b_pl301.hw,
|
||||
[CLKID_PERIPHS] = &meson8b_periphs.hw,
|
||||
[CLKID_SPICC] = &meson8b_spicc.hw,
|
||||
[CLKID_I2C] = &meson8b_i2c.hw,
|
||||
[CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
|
||||
[CLKID_SMART_CARD] = &meson8b_smart_card.hw,
|
||||
[CLKID_RNG0] = &meson8b_rng0.hw,
|
||||
[CLKID_UART0] = &meson8b_uart0.hw,
|
||||
[CLKID_SDHC] = &meson8b_sdhc.hw,
|
||||
[CLKID_STREAM] = &meson8b_stream.hw,
|
||||
[CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
|
||||
[CLKID_SDIO] = &meson8b_sdio.hw,
|
||||
[CLKID_ABUF] = &meson8b_abuf.hw,
|
||||
[CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
|
||||
[CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
|
||||
[CLKID_SPI] = &meson8b_spi.hw,
|
||||
[CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
|
||||
[CLKID_ETH] = &meson8b_eth.hw,
|
||||
[CLKID_DEMUX] = &meson8b_demux.hw,
|
||||
[CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
|
||||
[CLKID_IEC958] = &meson8b_iec958.hw,
|
||||
[CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
|
||||
[CLKID_AMCLK] = &meson8b_amclk.hw,
|
||||
[CLKID_AIFIFO2] = &meson8b_aififo2.hw,
|
||||
[CLKID_MIXER] = &meson8b_mixer.hw,
|
||||
[CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
|
||||
[CLKID_ADC] = &meson8b_adc.hw,
|
||||
[CLKID_BLKMV] = &meson8b_blkmv.hw,
|
||||
[CLKID_AIU] = &meson8b_aiu.hw,
|
||||
[CLKID_UART1] = &meson8b_uart1.hw,
|
||||
[CLKID_G2D] = &meson8b_g2d.hw,
|
||||
[CLKID_USB0] = &meson8b_usb0.hw,
|
||||
[CLKID_USB1] = &meson8b_usb1.hw,
|
||||
[CLKID_RESET] = &meson8b_reset.hw,
|
||||
[CLKID_NAND] = &meson8b_nand.hw,
|
||||
[CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
|
||||
[CLKID_USB] = &meson8b_usb.hw,
|
||||
[CLKID_VDIN1] = &meson8b_vdin1.hw,
|
||||
[CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &meson8b_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
|
||||
[CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
|
||||
[CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
|
||||
[CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
|
||||
[CLKID_DVIN] = &meson8b_dvin.hw,
|
||||
[CLKID_UART2] = &meson8b_uart2.hw,
|
||||
[CLKID_SANA] = &meson8b_sana.hw,
|
||||
[CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
|
||||
[CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
|
||||
[CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
|
||||
[CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
|
||||
[CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
|
||||
[CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
|
||||
[CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
|
||||
[CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
|
||||
[CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
|
||||
[CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
|
||||
[CLKID_ENC480P] = &meson8b_enc480p.hw,
|
||||
[CLKID_RNG1] = &meson8b_rng1.hw,
|
||||
[CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
|
||||
[CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
|
||||
[CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
|
||||
[CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
|
||||
[CLKID_EDP] = &meson8b_edp.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
|
||||
[CLKID_MPLL0] = &meson8b_mpll0.hw,
|
||||
[CLKID_MPLL1] = &meson8b_mpll1.hw,
|
||||
[CLKID_MPLL2] = &meson8b_mpll2.hw,
|
||||
[CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
|
||||
[CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
|
||||
[CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
|
||||
[CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
|
||||
[CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
|
||||
[CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
|
||||
[CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
|
||||
[CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
|
||||
[CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
|
||||
[CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
|
||||
[CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
|
||||
[CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
|
||||
[CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
|
||||
[CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
|
||||
[CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
|
||||
[CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
|
||||
[CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
|
||||
[CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
|
||||
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
|
||||
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
|
||||
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
|
||||
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
|
||||
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
|
||||
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
|
||||
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
|
||||
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
|
||||
[CLKID_AXI] = &meson8b_axi_clk_gate.hw,
|
||||
[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
|
||||
[CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
|
||||
[CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
|
||||
[CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
|
||||
[CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
|
||||
[CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
|
||||
[CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
|
||||
[CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
|
||||
[CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
|
||||
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
|
||||
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
|
||||
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
|
||||
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
|
||||
[CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
|
||||
[CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
|
||||
[CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
|
||||
[CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
|
||||
[CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
|
||||
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
|
||||
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
|
||||
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
|
||||
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
|
||||
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
|
||||
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
|
||||
[CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
|
||||
[CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
|
||||
[CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
|
||||
[CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
|
||||
[CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
|
||||
[CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
|
||||
[CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
|
||||
[CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
|
||||
[CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
|
||||
[CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
|
||||
[CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
|
||||
[CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
|
||||
[CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
|
||||
[CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
|
||||
[CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
|
||||
[CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
|
||||
[CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
|
||||
[CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
|
||||
[CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
|
||||
[CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
|
||||
[CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
|
||||
[CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
|
||||
[CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
|
||||
[CLKID_MALI_0] = &meson8b_mali_0.hw,
|
||||
[CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
|
||||
[CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &meson8b_mali_1.hw,
|
||||
[CLKID_MALI] = &meson8b_mali.hw,
|
||||
[CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
|
||||
[CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
|
||||
[CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
|
||||
[CLKID_VPU_0] = &meson8b_vpu_0.hw,
|
||||
[CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
|
||||
[CLKID_VPU_1] = &meson8b_vpu_1.hw,
|
||||
[CLKID_VPU] = &meson8b_vpu.hw,
|
||||
[CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
|
||||
[CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
|
||||
[CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
|
||||
[CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
|
||||
[CLKID_VDEC_1] = &meson8b_vdec_1.hw,
|
||||
[CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
|
||||
[CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
|
||||
[CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
|
||||
[CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
|
||||
[CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
|
||||
[CLKID_VDEC_2] = &meson8b_vdec_2.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
|
||||
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
|
||||
[CLK_NR_CLKS] = NULL,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
|
|
@ -2314,6 +3014,33 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
|||
&meson8b_mali_1_div,
|
||||
&meson8b_mali_1,
|
||||
&meson8b_mali,
|
||||
&meson8m2_gp_pll_dco,
|
||||
&meson8m2_gp_pll,
|
||||
&meson8b_vpu_0_sel,
|
||||
&meson8m2_vpu_0_sel,
|
||||
&meson8b_vpu_0_div,
|
||||
&meson8b_vpu_0,
|
||||
&meson8b_vpu_1_sel,
|
||||
&meson8m2_vpu_1_sel,
|
||||
&meson8b_vpu_1_div,
|
||||
&meson8b_vpu_1,
|
||||
&meson8b_vpu,
|
||||
&meson8b_vdec_1_sel,
|
||||
&meson8b_vdec_1_1_div,
|
||||
&meson8b_vdec_1_1,
|
||||
&meson8b_vdec_1_2_div,
|
||||
&meson8b_vdec_1_2,
|
||||
&meson8b_vdec_1,
|
||||
&meson8b_vdec_hcodec_sel,
|
||||
&meson8b_vdec_hcodec_div,
|
||||
&meson8b_vdec_hcodec,
|
||||
&meson8b_vdec_2_sel,
|
||||
&meson8b_vdec_2_div,
|
||||
&meson8b_vdec_2,
|
||||
&meson8b_vdec_hevc_sel,
|
||||
&meson8b_vdec_hevc_div,
|
||||
&meson8b_vdec_hevc_en,
|
||||
&meson8b_vdec_hevc,
|
||||
};
|
||||
|
||||
static const struct meson8b_clk_reset_line {
|
||||
|
|
@ -2558,9 +3285,14 @@ static void __init meson8b_clkc_init(struct device_node *np)
|
|||
return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
|
||||
}
|
||||
|
||||
static void __init meson8m2_clkc_init(struct device_node *np)
|
||||
{
|
||||
return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
|
||||
meson8_clkc_init);
|
||||
CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
|
||||
meson8b_clkc_init);
|
||||
CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
|
||||
meson8b_clkc_init);
|
||||
meson8m2_clkc_init);
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
*
|
||||
* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
|
||||
*/
|
||||
#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
|
||||
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
|
||||
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
|
||||
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
|
||||
|
|
@ -34,7 +35,11 @@
|
|||
#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
|
||||
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
|
||||
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
|
||||
#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
|
||||
#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
|
||||
#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */
|
||||
#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */
|
||||
#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */
|
||||
#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
|
||||
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
|
||||
|
|
@ -146,8 +151,28 @@
|
|||
#define CLKID_MALI_1_SEL 178
|
||||
#define CLKID_MALI_1_DIV 179
|
||||
#define CLKID_MALI_1 180
|
||||
#define CLKID_GP_PLL_DCO 181
|
||||
#define CLKID_GP_PLL 182
|
||||
#define CLKID_VPU_0_SEL 183
|
||||
#define CLKID_VPU_0_DIV 184
|
||||
#define CLKID_VPU_0 185
|
||||
#define CLKID_VPU_1_SEL 186
|
||||
#define CLKID_VPU_1_DIV 187
|
||||
#define CLKID_VPU_1 189
|
||||
#define CLKID_VDEC_1_SEL 191
|
||||
#define CLKID_VDEC_1_1_DIV 192
|
||||
#define CLKID_VDEC_1_1 193
|
||||
#define CLKID_VDEC_1_2_DIV 194
|
||||
#define CLKID_VDEC_1_2 195
|
||||
#define CLKID_VDEC_HCODEC_SEL 197
|
||||
#define CLKID_VDEC_HCODEC_DIV 198
|
||||
#define CLKID_VDEC_2_SEL 200
|
||||
#define CLKID_VDEC_2_DIV 201
|
||||
#define CLKID_VDEC_HEVC_SEL 203
|
||||
#define CLKID_VDEC_HEVC_DIV 204
|
||||
#define CLKID_VDEC_HEVC_EN 205
|
||||
|
||||
#define CLK_NR_CLKS 181
|
||||
#define CLK_NR_CLKS 207
|
||||
|
||||
/*
|
||||
* include the CLKID and RESETID that have
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
|
|||
* Divider field is write only, so divider stat field must
|
||||
* be read so divider field can be set accordingly.
|
||||
*/
|
||||
val = clk_readl(gate->reg);
|
||||
val = readl(gate->reg);
|
||||
if (val & LPC18XX_CCU_DIVSTAT)
|
||||
val |= LPC18XX_CCU_DIV;
|
||||
|
||||
|
|
@ -155,12 +155,12 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
|
|||
* and the next write should clear the RUN bit.
|
||||
*/
|
||||
val |= LPC18XX_CCU_AUTO;
|
||||
clk_writel(val, gate->reg);
|
||||
writel(val, gate->reg);
|
||||
|
||||
val &= ~LPC18XX_CCU_RUN;
|
||||
}
|
||||
|
||||
clk_writel(val, gate->reg);
|
||||
writel(val, gate->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -352,9 +352,9 @@ static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw,
|
|||
struct lpc18xx_pll *pll = to_lpc_pll(hw);
|
||||
u32 ctrl, mdiv, msel, npdiv;
|
||||
|
||||
ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
|
||||
npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
|
||||
ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
|
||||
npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
|
||||
|
||||
if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)
|
||||
return parent_rate;
|
||||
|
|
@ -415,25 +415,25 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;
|
||||
|
||||
/* Power down PLL, disable clk output and dividers */
|
||||
ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
ctrl |= LPC18XX_PLL0_CTRL_PD;
|
||||
ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |
|
||||
LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);
|
||||
clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
|
||||
/* Configure new PLL settings */
|
||||
clk_writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
|
||||
clk_writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
|
||||
writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
|
||||
writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
|
||||
|
||||
/* Power up PLL and wait for lock */
|
||||
ctrl &= ~LPC18XX_PLL0_CTRL_PD;
|
||||
clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
do {
|
||||
udelay(10);
|
||||
stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
|
||||
stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
|
||||
if (stat & LPC18XX_PLL0_STAT_LOCK) {
|
||||
ctrl |= LPC18XX_PLL0_CTRL_CLKEN;
|
||||
clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -458,8 +458,8 @@ static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw,
|
|||
bool direct, fbsel;
|
||||
u32 stat, ctrl;
|
||||
|
||||
stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
|
||||
ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
|
||||
stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
|
||||
ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
|
||||
|
||||
direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
|
||||
fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;
|
||||
|
|
|
|||
|
|
@ -1085,13 +1085,12 @@ struct clk_hw_proto {
|
|||
};
|
||||
};
|
||||
|
||||
#define LPC32XX_DEFINE_FIXED(_idx, _rate, _flags) \
|
||||
#define LPC32XX_DEFINE_FIXED(_idx, _rate) \
|
||||
[CLK_PREFIX(_idx)] = { \
|
||||
.type = CLK_FIXED, \
|
||||
{ \
|
||||
.f = { \
|
||||
.fixed_rate = (_rate), \
|
||||
.flags = (_flags), \
|
||||
}, \
|
||||
}, \
|
||||
}
|
||||
|
|
@ -1225,7 +1224,7 @@ struct clk_hw_proto {
|
|||
}
|
||||
|
||||
static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = {
|
||||
LPC32XX_DEFINE_FIXED(RTC, 32768, 0),
|
||||
LPC32XX_DEFINE_FIXED(RTC, 32768),
|
||||
LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)),
|
||||
LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE),
|
||||
LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE),
|
||||
|
|
@ -1468,7 +1467,7 @@ static struct clk * __init lpc32xx_clk_register(u32 id)
|
|||
struct clk_fixed_rate *fixed = &clk_hw->f;
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name,
|
||||
parents[0], fixed->flags, fixed->fixed_rate);
|
||||
parents[0], 0, fixed->fixed_rate);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
|
|||
struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
|
||||
u32 val;
|
||||
|
||||
val = clk_readl(ddrclk->reg_base +
|
||||
val = readl(ddrclk->reg_base +
|
||||
ddrclk->mux_offset) >> ddrclk->mux_shift;
|
||||
val &= GENMASK(ddrclk->mux_width - 1, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static unsigned long clk_half_divider_recalc_rate(struct clk_hw *hw,
|
|||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
unsigned int val;
|
||||
|
||||
val = clk_readl(divider->reg) >> divider->shift;
|
||||
val = readl(divider->reg) >> divider->shift;
|
||||
val &= div_mask(divider->width);
|
||||
val = val * 2 + 3;
|
||||
|
||||
|
|
@ -124,11 +124,11 @@ static int clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
|
||||
val = div_mask(divider->width) << (divider->shift + 16);
|
||||
} else {
|
||||
val = clk_readl(divider->reg);
|
||||
val = readl(divider->reg);
|
||||
val &= ~(div_mask(divider->width) << divider->shift);
|
||||
}
|
||||
val |= value << divider->shift;
|
||||
clk_writel(val, divider->reg);
|
||||
writel(val, divider->reg);
|
||||
|
||||
if (divider->lock)
|
||||
spin_unlock_irqrestore(divider->lock, flags);
|
||||
|
|
|
|||
|
|
@ -1466,9 +1466,9 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
|||
tegra_pmc_clk_init(pmc_base, tegra124_clks);
|
||||
|
||||
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
|
||||
plld_base = clk_readl(clk_base + PLLD_BASE);
|
||||
plld_base = readl(clk_base + PLLD_BASE);
|
||||
plld_base &= ~BIT(25);
|
||||
clk_writel(plld_base, clk_base + PLLD_BASE);
|
||||
writel(plld_base, clk_base + PLLD_BASE);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -3557,7 +3557,7 @@ static void __init tegra210_clock_init(struct device_node *np)
|
|||
if (!clks)
|
||||
return;
|
||||
|
||||
value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
|
||||
value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
|
||||
clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
|
||||
|
||||
if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
|
||||
|
|
@ -3574,9 +3574,9 @@ static void __init tegra210_clock_init(struct device_node *np)
|
|||
tegra_pmc_clk_init(pmc_base, tegra210_clks);
|
||||
|
||||
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
|
||||
value = clk_readl(clk_base + PLLD_BASE);
|
||||
value = readl(clk_base + PLLD_BASE);
|
||||
value &= ~BIT(25);
|
||||
clk_writel(value, clk_base + PLLD_BASE);
|
||||
writel(value, clk_base + PLLD_BASE);
|
||||
|
||||
tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
|
||||
|
||||
|
|
|
|||
|
|
@ -158,7 +158,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
|
|||
clks[fclk] = clk_register_gate(NULL, clk_name,
|
||||
div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
|
||||
0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
|
||||
enable_reg = clk_readl(fclk_gate_reg) & 1;
|
||||
enable_reg = readl(fclk_gate_reg) & 1;
|
||||
if (enable && !enable_reg) {
|
||||
if (clk_prepare_enable(clks[fclk]))
|
||||
pr_warn("%s: FCLK%u enable failed\n", __func__,
|
||||
|
|
@ -287,7 +287,7 @@ static void __init zynq_clk_setup(struct device_node *np)
|
|||
SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
|
||||
|
||||
/* CPU clocks */
|
||||
tmp = clk_readl(SLCR_621_TRUE) & 1;
|
||||
tmp = readl(SLCR_621_TRUE) & 1;
|
||||
clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
|
||||
CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
|
||||
&armclk_lock);
|
||||
|
|
@ -510,7 +510,7 @@ static void __init zynq_clk_setup(struct device_node *np)
|
|||
&dbgclk_lock);
|
||||
|
||||
/* leave debug clocks in the state the bootloader set them up to */
|
||||
tmp = clk_readl(SLCR_DBG_CLK_CTRL);
|
||||
tmp = readl(SLCR_DBG_CLK_CTRL);
|
||||
if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
|
||||
if (clk_prepare_enable(clks[dbg_trc]))
|
||||
pr_warn("%s: trace clk enable failed\n", __func__);
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
|
|||
* makes probably sense to redundantly save fbdiv in the struct
|
||||
* zynq_pll to save the IO access.
|
||||
*/
|
||||
fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
|
||||
fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
|
||||
PLLCTRL_FBDIV_SHIFT;
|
||||
|
||||
return parent_rate * fbdiv;
|
||||
|
|
@ -112,7 +112,7 @@ static int zynq_pll_is_enabled(struct clk_hw *hw)
|
|||
|
||||
spin_lock_irqsave(clk->lock, flags);
|
||||
|
||||
reg = clk_readl(clk->pll_ctrl);
|
||||
reg = readl(clk->pll_ctrl);
|
||||
|
||||
spin_unlock_irqrestore(clk->lock, flags);
|
||||
|
||||
|
|
@ -138,10 +138,10 @@ static int zynq_pll_enable(struct clk_hw *hw)
|
|||
/* Power up PLL and wait for lock */
|
||||
spin_lock_irqsave(clk->lock, flags);
|
||||
|
||||
reg = clk_readl(clk->pll_ctrl);
|
||||
reg = readl(clk->pll_ctrl);
|
||||
reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
|
||||
clk_writel(reg, clk->pll_ctrl);
|
||||
while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit)))
|
||||
writel(reg, clk->pll_ctrl);
|
||||
while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
|
||||
;
|
||||
|
||||
spin_unlock_irqrestore(clk->lock, flags);
|
||||
|
|
@ -168,9 +168,9 @@ static void zynq_pll_disable(struct clk_hw *hw)
|
|||
/* shut down PLL */
|
||||
spin_lock_irqsave(clk->lock, flags);
|
||||
|
||||
reg = clk_readl(clk->pll_ctrl);
|
||||
reg = readl(clk->pll_ctrl);
|
||||
reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
|
||||
clk_writel(reg, clk->pll_ctrl);
|
||||
writel(reg, clk->pll_ctrl);
|
||||
|
||||
spin_unlock_irqrestore(clk->lock, flags);
|
||||
}
|
||||
|
|
@ -223,9 +223,9 @@ struct clk *clk_register_zynq_pll(const char *name, const char *parent,
|
|||
|
||||
spin_lock_irqsave(pll->lock, flags);
|
||||
|
||||
reg = clk_readl(pll->pll_ctrl);
|
||||
reg = readl(pll->pll_ctrl);
|
||||
reg &= ~PLLCTRL_BPQUAL_MASK;
|
||||
clk_writel(reg, pll->pll_ctrl);
|
||||
writel(reg, pll->pll_ctrl);
|
||||
|
||||
spin_unlock_irqrestore(pll->lock, flags);
|
||||
|
||||
|
|
|
|||
|
|
@ -7,26 +7,6 @@
|
|||
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
#define __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
|
||||
#define AUD_CLKID_SLV_SCLK0 9
|
||||
#define AUD_CLKID_SLV_SCLK1 10
|
||||
#define AUD_CLKID_SLV_SCLK2 11
|
||||
#define AUD_CLKID_SLV_SCLK3 12
|
||||
#define AUD_CLKID_SLV_SCLK4 13
|
||||
#define AUD_CLKID_SLV_SCLK5 14
|
||||
#define AUD_CLKID_SLV_SCLK6 15
|
||||
#define AUD_CLKID_SLV_SCLK7 16
|
||||
#define AUD_CLKID_SLV_SCLK8 17
|
||||
#define AUD_CLKID_SLV_SCLK9 18
|
||||
#define AUD_CLKID_SLV_LRCLK0 19
|
||||
#define AUD_CLKID_SLV_LRCLK1 20
|
||||
#define AUD_CLKID_SLV_LRCLK2 21
|
||||
#define AUD_CLKID_SLV_LRCLK3 22
|
||||
#define AUD_CLKID_SLV_LRCLK4 23
|
||||
#define AUD_CLKID_SLV_LRCLK5 24
|
||||
#define AUD_CLKID_SLV_LRCLK6 25
|
||||
#define AUD_CLKID_SLV_LRCLK7 26
|
||||
#define AUD_CLKID_SLV_LRCLK8 27
|
||||
#define AUD_CLKID_SLV_LRCLK9 28
|
||||
#define AUD_CLKID_DDR_ARB 29
|
||||
#define AUD_CLKID_PDM 30
|
||||
#define AUD_CLKID_TDMIN_A 31
|
||||
|
|
@ -90,5 +70,15 @@
|
|||
#define AUD_CLKID_TDMOUT_A_LRCLK 134
|
||||
#define AUD_CLKID_TDMOUT_B_LRCLK 135
|
||||
#define AUD_CLKID_TDMOUT_C_LRCLK 136
|
||||
#define AUD_CLKID_SPDIFOUT_B 151
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK 152
|
||||
#define AUD_CLKID_TDM_MCLK_PAD0 155
|
||||
#define AUD_CLKID_TDM_MCLK_PAD1 156
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD0 157
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD1 158
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD2 159
|
||||
#define AUD_CLKID_TDM_SCLK_PAD0 160
|
||||
#define AUD_CLKID_TDM_SCLK_PAD1 161
|
||||
#define AUD_CLKID_TDM_SCLK_PAD2 162
|
||||
|
||||
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
|
||||
|
|
|
|||
|
|
@ -26,7 +26,9 @@
|
|||
#define CLKID_AO_M4_FCLK 13
|
||||
#define CLKID_AO_M4_HCLK 14
|
||||
#define CLKID_AO_CLK81 15
|
||||
#define CLKID_AO_SAR_ADC_SEL 16
|
||||
#define CLKID_AO_SAR_ADC_CLK 18
|
||||
#define CLKID_AO_CTS_OSCIN 19
|
||||
#define CLKID_AO_32K 23
|
||||
#define CLKID_AO_CEC 27
|
||||
#define CLKID_AO_CTS_RTC_OSCIN 28
|
||||
|
|
|
|||
|
|
@ -131,5 +131,10 @@
|
|||
#define CLKID_MALI_1 174
|
||||
#define CLKID_MALI 175
|
||||
#define CLKID_MPLL_5OM 177
|
||||
#define CLKID_CPU_CLK 187
|
||||
#define CLKID_PCIE_PLL 201
|
||||
#define CLKID_VDEC_1 204
|
||||
#define CLKID_VDEC_HEVC 207
|
||||
#define CLKID_VDEC_HEVCF 210
|
||||
|
||||
#endif /* __G12A_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -103,10 +103,14 @@
|
|||
#define CLKID_MPLL1 94
|
||||
#define CLKID_MPLL2 95
|
||||
#define CLKID_NAND_CLK 112
|
||||
#define CLKID_ABP 124
|
||||
#define CLKID_APB 124
|
||||
#define CLKID_PERIPH 126
|
||||
#define CLKID_AXI 128
|
||||
#define CLKID_L2_DRAM 130
|
||||
#define CLKID_VPU 190
|
||||
#define CLKID_VDEC_1 196
|
||||
#define CLKID_VDEC_HCODEC 199
|
||||
#define CLKID_VDEC_2 202
|
||||
#define CLKID_VDEC_HEVC 206
|
||||
|
||||
#endif /* __MESON8B_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
|
||||
#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
|
||||
/* unused */
|
||||
#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
|
||||
#define CLK_IS_BASIC BIT(5) /* deprecated, don't use */
|
||||
#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
|
||||
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
|
||||
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
|
||||
|
|
@ -307,7 +307,6 @@ struct clk_fixed_rate {
|
|||
struct clk_hw hw;
|
||||
unsigned long fixed_rate;
|
||||
unsigned long fixed_accuracy;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
|
||||
|
|
@ -349,6 +348,9 @@ void of_fixed_clk_setup(struct device_node *np);
|
|||
* of this register, and mask of gate bits are in higher 16-bit of this
|
||||
* register. While setting the gate bits, higher 16-bit should also be
|
||||
* updated to indicate changing gate bits.
|
||||
* CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
|
||||
* the gate register. Setting this flag makes the register accesses big
|
||||
* endian.
|
||||
*/
|
||||
struct clk_gate {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -362,6 +364,7 @@ struct clk_gate {
|
|||
|
||||
#define CLK_GATE_SET_TO_DISABLE BIT(0)
|
||||
#define CLK_GATE_HIWORD_MASK BIT(1)
|
||||
#define CLK_GATE_BIG_ENDIAN BIT(2)
|
||||
|
||||
extern const struct clk_ops clk_gate_ops;
|
||||
struct clk *clk_register_gate(struct device *dev, const char *name,
|
||||
|
|
@ -417,6 +420,9 @@ struct clk_div_table {
|
|||
* CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
|
||||
* except when the value read from the register is zero, the divisor is
|
||||
* 2^width of the field.
|
||||
* CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
|
||||
* for the divider register. Setting this flag makes the register accesses
|
||||
* big endian.
|
||||
*/
|
||||
struct clk_divider {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -438,6 +444,7 @@ struct clk_divider {
|
|||
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
|
||||
#define CLK_DIVIDER_READ_ONLY BIT(5)
|
||||
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
|
||||
#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
|
||||
|
||||
extern const struct clk_ops clk_divider_ops;
|
||||
extern const struct clk_ops clk_divider_ro_ops;
|
||||
|
|
@ -499,8 +506,13 @@ void clk_hw_unregister_divider(struct clk_hw *hw);
|
|||
* register, and mask of mux bits are in higher 16-bit of this register.
|
||||
* While setting the mux bits, higher 16-bit should also be updated to
|
||||
* indicate changing mux bits.
|
||||
* CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
|
||||
* .get_parent clk_op.
|
||||
* CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
|
||||
* frequency.
|
||||
* CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
|
||||
* the mux register. Setting this flag makes the register accesses big
|
||||
* endian.
|
||||
*/
|
||||
struct clk_mux {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -519,6 +531,7 @@ struct clk_mux {
|
|||
#define CLK_MUX_HIWORD_MASK BIT(2)
|
||||
#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
|
||||
#define CLK_MUX_ROUND_CLOSEST BIT(4)
|
||||
#define CLK_MUX_BIG_ENDIAN BIT(5)
|
||||
|
||||
extern const struct clk_ops clk_mux_ops;
|
||||
extern const struct clk_ops clk_mux_ro_ops;
|
||||
|
|
@ -602,6 +615,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
|
|||
* is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
|
||||
* is set then the numerator and denominator are both the value read
|
||||
* plus one.
|
||||
* CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
|
||||
* used for the divider register. Setting this flag makes the register
|
||||
* accesses big endian.
|
||||
*/
|
||||
struct clk_fractional_divider {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -622,6 +638,7 @@ struct clk_fractional_divider {
|
|||
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
|
||||
|
||||
#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
|
||||
#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
|
||||
|
||||
extern const struct clk_ops clk_fractional_divider_ops;
|
||||
struct clk *clk_register_fractional_divider(struct device *dev,
|
||||
|
|
@ -654,6 +671,9 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
|
|||
* leaving the parent rate unmodified.
|
||||
* CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
|
||||
* rounded to the closest integer instead of the down one.
|
||||
* CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
|
||||
* used for the multiplier register. Setting this flag makes the register
|
||||
* accesses big endian.
|
||||
*/
|
||||
struct clk_multiplier {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -668,6 +688,7 @@ struct clk_multiplier {
|
|||
|
||||
#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
|
||||
#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
|
||||
#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
|
||||
|
||||
extern const struct clk_ops clk_multiplier_ops;
|
||||
|
||||
|
|
@ -712,16 +733,19 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
|
|||
unsigned long flags);
|
||||
void clk_hw_unregister_composite(struct clk_hw *hw);
|
||||
|
||||
/***
|
||||
* struct clk_gpio_gate - gpio gated clock
|
||||
/**
|
||||
* struct clk_gpio - gpio gated clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @gpiod: gpio descriptor
|
||||
*
|
||||
* Clock with a gpio control for enabling and disabling the parent clock.
|
||||
* Implements .enable, .disable and .is_enabled
|
||||
* Clock with a gpio control for enabling and disabling the parent clock
|
||||
* or switching between two parents by asserting or deasserting the gpio.
|
||||
*
|
||||
* Implements .enable, .disable and .is_enabled or
|
||||
* .get_parent, .set_parent and .determine_rate depending on which clk_ops
|
||||
* is used.
|
||||
*/
|
||||
|
||||
struct clk_gpio {
|
||||
struct clk_hw hw;
|
||||
struct gpio_desc *gpiod;
|
||||
|
|
@ -738,16 +762,6 @@ struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
|
|||
unsigned long flags);
|
||||
void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
|
||||
|
||||
/**
|
||||
* struct clk_gpio_mux - gpio controlled clock multiplexer
|
||||
*
|
||||
* @hw: see struct clk_gpio
|
||||
* @gpiod: gpio descriptor to select the parent of this clock multiplexer
|
||||
*
|
||||
* Clock with a gpio control for selecting the parent clock.
|
||||
* Implements .get_parent, .set_parent and .determine_rate
|
||||
*/
|
||||
|
||||
extern const struct clk_ops clk_gpio_mux_ops;
|
||||
struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
|
||||
const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
|
||||
|
|
@ -757,17 +771,6 @@ struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
|
|||
unsigned long flags);
|
||||
void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
|
||||
|
||||
/**
|
||||
* clk_register - allocate a new clock, register it and return an opaque cookie
|
||||
* @dev: device that is registering this clock
|
||||
* @hw: link to hardware-specific clock data
|
||||
*
|
||||
* clk_register is the primary interface for populating the clock tree with new
|
||||
* clock nodes. It returns a pointer to the newly allocated struct clk which
|
||||
* cannot be dereferenced by driver code but may be used in conjuction with the
|
||||
* rest of the clock API. In the event of an error clk_register will return an
|
||||
* error code; drivers must test for an error code after calling clk_register.
|
||||
*/
|
||||
struct clk *clk_register(struct device *dev, struct clk_hw *hw);
|
||||
struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
|
||||
|
||||
|
|
@ -993,37 +996,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index,
|
|||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
/*
|
||||
* wrap access to peripherals in accessor routines
|
||||
* for improved portability across platforms
|
||||
*/
|
||||
|
||||
#if IS_ENABLED(CONFIG_PPC)
|
||||
|
||||
static inline u32 clk_readl(u32 __iomem *reg)
|
||||
{
|
||||
return ioread32be(reg);
|
||||
}
|
||||
|
||||
static inline void clk_writel(u32 val, u32 __iomem *reg)
|
||||
{
|
||||
iowrite32be(val, reg);
|
||||
}
|
||||
|
||||
#else /* platform dependent I/O accessors */
|
||||
|
||||
static inline u32 clk_readl(u32 __iomem *reg)
|
||||
{
|
||||
return readl(reg);
|
||||
}
|
||||
|
||||
static inline void clk_writel(u32 val, u32 __iomem *reg)
|
||||
{
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
#endif /* platform dependent I/O accessors */
|
||||
|
||||
void clk_gate_restore_context(struct clk_hw *hw);
|
||||
|
||||
#endif /* CONFIG_COMMON_CLK */
|
||||
|
|
|
|||
Loading…
Reference in a new issue