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phy: cadence-torrent: Add wrapper for DPTX register access
Add wrapper functions to read, write DisplayPort specific PHY registers to improve code readability. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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ccb1b89de3
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1 changed files with 50 additions and 21 deletions
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@ -140,13 +140,31 @@ static void cdns_torrent_phy_write(struct cdns_torrent_phy *cdns_phy,
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writel(val, cdns_phy->sd_base + offset);
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writel(val, cdns_phy->sd_base + offset);
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}
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}
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/* DPTX mmr access functions */
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static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy,
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u32 offset, u32 val)
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{
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writel(val, cdns_phy->base + offset);
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}
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static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
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{
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return readl(cdns_phy->base + offset);
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}
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#define cdns_torrent_dp_read_poll_timeout(cdns_phy, offset, val, cond, \
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delay_us, timeout_us) \
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readl_poll_timeout((cdns_phy)->base + (offset), \
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val, cond, delay_us, timeout_us)
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static int cdns_torrent_dp_init(struct phy *phy)
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static int cdns_torrent_dp_init(struct phy *phy)
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{
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{
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unsigned char lane_bits;
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unsigned char lane_bits;
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struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
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struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
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writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */
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cdns_torrent_dp_write(cdns_phy, PHY_AUX_CTRL, 0x0003); /* enable AUX */
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/* PHY PMA registers configuration function */
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/* PHY PMA registers configuration function */
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cdns_torrent_dp_pma_cfg(cdns_phy);
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cdns_torrent_dp_pma_cfg(cdns_phy);
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@ -195,11 +213,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
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* used lanes
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* used lanes
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*/
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*/
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lane_bits = (1 << cdns_phy->num_lanes) - 1;
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lane_bits = (1 << cdns_phy->num_lanes) - 1;
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writel(((0xF & ~lane_bits) << 4) | (0xF & lane_bits),
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cdns_torrent_dp_write(cdns_phy, PHY_RESET,
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cdns_phy->base + PHY_RESET);
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((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
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/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
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/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
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writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN);
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cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
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/* PHY PMA registers configuration functions */
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/* PHY PMA registers configuration functions */
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cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy);
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cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy);
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@ -219,8 +237,8 @@ void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
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unsigned int reg;
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unsigned int reg;
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int ret;
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int ret;
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ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_CMN_READY, reg,
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ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, PHY_PMA_CMN_READY,
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reg & 1, 0, 500);
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reg, reg & 1, 0, 500);
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if (ret == -ETIMEDOUT)
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if (ret == -ETIMEDOUT)
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dev_err(cdns_phy->dev,
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dev_err(cdns_phy->dev,
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"timeout waiting for PMA common ready\n");
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"timeout waiting for PMA common ready\n");
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@ -391,8 +409,10 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
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* waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
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* waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
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* master lane
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* master lane
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*/
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*/
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ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN_ACK,
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ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
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read_val, read_val & 1, 0, POLL_TIMEOUT_US);
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PHY_PMA_XCVR_PLLCLK_EN_ACK,
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read_val, read_val & 1, 0,
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POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT)
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if (ret == -ETIMEDOUT)
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dev_err(cdns_phy->dev,
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dev_err(cdns_phy->dev,
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"timeout waiting for link PLL clock enable ack\n");
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"timeout waiting for link PLL clock enable ack\n");
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@ -417,28 +437,35 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
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break;
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break;
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}
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}
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writel(write_val1, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
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cdns_torrent_dp_write(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ, write_val1);
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ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_ACK,
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read_val,
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(read_val & mask) == write_val1,
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0, POLL_TIMEOUT_US);
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ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
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read_val, (read_val & mask) == write_val1, 0,
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POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT)
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if (ret == -ETIMEDOUT)
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dev_err(cdns_phy->dev,
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dev_err(cdns_phy->dev,
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"timeout waiting for link power state ack\n");
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"timeout waiting for link power state ack\n");
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writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
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cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
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ndelay(100);
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ndelay(100);
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writel(write_val2, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
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cdns_torrent_dp_write(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ, write_val2);
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ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
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ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
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read_val, (read_val & mask) == write_val2, 0,
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PHY_PMA_XCVR_POWER_STATE_ACK,
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POLL_TIMEOUT_US);
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read_val,
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(read_val & mask) == write_val2,
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0, POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT)
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if (ret == -ETIMEDOUT)
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dev_err(cdns_phy->dev,
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dev_err(cdns_phy->dev,
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"timeout waiting for link power state ack\n");
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"timeout waiting for link power state ack\n");
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writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
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cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
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ndelay(100);
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ndelay(100);
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}
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}
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@ -450,9 +477,11 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
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{
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{
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unsigned int read_val;
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unsigned int read_val;
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read_val = readl(cdns_phy->base + offset);
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read_val = cdns_torrent_dp_read(cdns_phy, offset);
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writel(((val << start_bit) | (read_val & ~(((1 << num_bits) - 1) <<
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cdns_torrent_dp_write(cdns_phy, offset,
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start_bit))), cdns_phy->base + offset);
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((val << start_bit) |
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(read_val & ~(((1 << num_bits) - 1) <<
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start_bit))));
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}
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}
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static int cdns_torrent_phy_probe(struct platform_device *pdev)
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static int cdns_torrent_phy_probe(struct platform_device *pdev)
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